JPH0442618A - A/d converter circuit - Google Patents

Abstract

PURPOSE:To decrease the distortion and delay in an analog voltage and to attain high accuracy by providing plural buffer circuits to each pre-stage of plural comparator circuits respectively, applying an analog input voltage to an input of the buffer circuit and supplying an output of the buffer circuit to the other input of each comparator circuit. CONSTITUTION:Plural comparator circuits C1 - C2N-1 whose respective one input receives a different reference voltage are divided into plural comparator circuit groups, plural buffer circuits B1, BM are provided respectively before and behind the plural comparator circuit groups and an analog input voltage AIN is applied to each input of the plural buffer circuits B1, BM. Then the output of the plural buffer circuits B1, BM is supplied to the other input of the comparator circuits C1 - C2N-1 respectively. Thus, distortion in the analog input voltage is decreased and the delay in the propagation of the analog input voltage is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an A/D that converts an analog signal into a digital signal.
This relates to converter circuits.

[Conventional technology]

FIG. 3 is a block diagram of a conventional parallel comparison type (flash type) A/D converter circuit. As shown in the figure, the analog input voltage AIN is applied to the comparator circuits C1 to C
2N-1 are connected to one input of each. In addition, reference voltage sources VR+ and VR- (however, VR+ is VR-
Assume that the potential is higher. ) is equally divided by two reference resistors R1 with equal resistance values, and a reference voltage Vrl or Vr2'-1 is obtained from the other voltage of the comparator circuits CI to C2N-1, respectively. connected to the input. Furthermore, the negative phase output of the comparator circuit C1 is connected to one input of the two-man power AND circuit A1, the positive phase output of the comparator circuit CI is connected to one input of the two-man power AND circuit A2, and the negative phase output of the comparator circuit C2 is connected to the two-man power AND circuit A2. AND
The comparator circuits CI to C2 are connected to the other input of the circuit A2, and the positive phase output of the comparator circuit C2 is input to one input of the two-man power AND circuit A3 (not shown).
One positive-phase output and the other negative-phase output of two adjacent N-1 are input to two AND circuits A1 to A21. Note that the other input of the two-man power AND circuit A1 is always fixed at a high level (power supply voltage 2) and C2. Also, two-person AND circuit AI or A2N
1 each, 2 outputs are input to the encoder circuit E1, the encoder circuit E1 encodes 2N-1 inputs into N inputs, and outputs them to the output buffer circuit 01, and the output buffer circuit 01 encodes the N inputs. Amplify the input and create data D
Output as I or DN.

Next, the operation will be explained. The comparator circuits CI or C2N-1 have two inputs, the - one being the analog input voltage A I N common to all comparator circuits C1 or LC2N-1, and the other being the comparator circuit C1.
The levels of the individual reference voltages Vrl to Vr2N-1 are compared for each of the reference voltages Vrl to C2N-1. As a result, among the comparator circuits CI to C2N-1, the reference voltage Vr
If the analog input voltage AIN has a higher level than l or Vr2N-1, it outputs a high level to its positive phase output and a low level to its negative phase output, and conversely, the reference voltage Vrl or Vr
When the analog input voltage AIN has a lower level than r2N-11, a low level is output to its positive phase output, and a high level is output to its negative phase output. Therefore, if two adjacent outputs of the comparator circuits C1 to C2N1 input to the two-man power AND circuits AI to A2N-1 are the same, the level of one positive phase output and the other negative phase output will always be the same. It will be different, two-man AND circuit AI or A2N-1
Of these, the output of those that fall under this category will be at a low level.

Furthermore, if the two adjacent outputs of the comparator circuits Ce to C21 input to the two-manufactured AND circuits AI to A2N-1 are different, the levels of one positive phase output and the other negative phase output are always the same. , and the output of the corresponding one of the two-man-powered AND circuits AI to A21 becomes high level.

By the way, two adjacent comparator circuits CI to 02N-1, for example, comparator circuits C21 and C
22 (not shown) have different outputs. In this case, 2 of the comparator circuit C21 (not shown)
When two inputs, that is, the analog input voltage AIN and the reference voltage Vr21 are compared, the level of the reference voltage Vr21 is higher than that of the analog input voltage AIN. However, since the levels of the reference voltages Vrl to Vr20 are higher than the reference voltage Vr21, the outputs of the comparator circuits CI to C21 are all the same. Further, in the above situation, two inputs of the comparator circuit C22 (not shown), namely, the analog input voltage AIN
When comparing the reference voltage Vr22 with the analog input voltage AIN, the level of the reference voltage Vr22 is lower than that of the analog input voltage AIN. However, the reference voltages Vr23 to Vr2'-1
Since the level of is lower than the reference voltage Vr22, the outputs of the comparator circuits C22 to C21 are all the same. In this way, there is only one pair of comparator circuits CI to C2N-1 in which two adjacent outputs are different, and therefore, among the two-man-powered AND circuits A1 to A2N-1, only one output is at a high level. There is only one.

Note that the two-man power AND circuits A1 to A21 shown in FIG. Similar operations can be performed as input.

Then, the encoder circuit E1 receives the analog input voltage A based on the outputs of the two manual AND circuits A1 to A21.
An N-bit digital signal obtained by A/D converting IN is output, and this digital signal is derived as digital data outputs D1 to DN via an output buffer circuit 01.

Figure 4 shows comparator circuits CI to C shown in Figure 3.
FIG. 2 is a circuit diagram showing an internal circuit of 2N-1.

As shown in the figure, the analog input voltage AIN and the reference voltage V' are level-shifted by the emitter follower circuit 2a and input to the differential amplifier 3a of the differential amplifier circuit 3 with a latch function by the potential difference between the base and emitter. In the differential amplifier circuit 3 with latch function, when the clock signal CLK is at a high level, the differential amplifier 3a inputs the input voltage A I N
, compare and amplify the levels of the reference voltage Vr, and when the clock signal CLK is at a low level, the differential amplifier 3b
Hold the output of a. The output of the differential amplifier circuit 3 with a latch function is derived as a positive phase output Q and a negative phase output Q via an emitter follower circuit 2b.

Note that the input capacitance of the comparator circuits CI to C2N-1 is the base, collector, and base of the bipolar transistor of the emitter follower circuit 2a.

This is the capacitance between the emitters and the wiring capacitance of the wiring that transmits the analog input voltage AIN to the base.

[Problem to be solved by the invention]

Since the conventional A/D converter circuit is configured as described above, in order to realize an A/D converter that outputs N-bit digital data D1 to DN, 21 humparator circuits C1 to C2 are required.
1 was necessary. Furthermore, when expanding the number of bits of the N-bit digital data D1 to DN, the number of comparator circuits C1 to 02N-1 had to be increased in proportion to 2. Therefore, as the number of comparator circuits C1 to C21 increases, the input capacitance increases, causing distortion in the analog input voltage AIN, and a delay in the propagation of the analog input voltage between the plurality of comparator circuits CI to C21. There was a problem that occurred.

This invention was made to solve the above-mentioned problems, and aims to reduce distortion and delay of analog input voltage AIN and obtain a highly accurate A/D converter circuit.

[Means to solve the problem]

The A/D converter circuit according to the present invention divides a plurality of comparator circuits, each of which has a different reference voltage applied to one input, into a plurality of comparator circuit groups, and performs a previous stage corresponding to each of the plurality of comparator circuit groups. A plurality of buffer circuits are provided in the circuit, and the analog input voltage is applied to the inputs of the plurality of buffer circuits, and the output of the plurality of buffer circuits is applied to the other one of each comparator circuit in the corresponding comparator circuit group.

[Effect]

In this invention, a plurality of comparator circuits are divided into a plurality of comparator circuit groups, an analog input voltage is applied to the inputs of buffer circuits prepared as many as the comparator circuit groups, and the output of the buffer circuit is used as the input of the comparator circuit group. As a result, the number of circuits connected to the analog input voltage is reduced, and the number of comparator circuits to be driven by each buffer circuit is also reduced, which reduces distortion of the analog input voltage and reduces the delay caused in the propagation of the analog input voltage. will also become smaller.

〔Example〕

An embodiment of this invention will be described below. FIG. 1 is a block diagram showing an embodiment of a parallel comparison type (flash type) A/D converter circuit according to the present invention. As shown in the figure, the analog input voltage AIN is connected to the inputs of the buffer circuits B1 to BM, and the output of the buffer circuit B1 is connected to the input of one of the comparator circuits C1 to CK.
The output of the buffer circuit BM is connected to one input of the comparator circuits CL to C2N-1. That is,
The analog input voltage AIN is received by M buffer circuits B1 to BM and distributed to 2N-1 comparator circuits CI to C2N-1.

Also, reference voltage sources VR+ and VR- (however, VR+ is V
It is assumed that the potential is higher than R-. ), a reference voltage Vrl or Vr2N-1 obtained by equally dividing the equal resistance value by another 2N-1 resistor R1 is connected to the other input of each of the comparator circuits c1 to C21. ing. Further, the negative phase output of the comparator circuit c1 is connected to one input of the two-man power AND circuit A1, and the positive phase input of the comparator circuit C1 is connected to one of the two-man power AND circuit A2 (not shown). The opposite phase output of the two-man power AND circuit A2 (not shown) is connected to the other input of the comparator circuit C2 (not shown).
The positive phase output of the comparator circuit C1 is input to one input of the two-power AND circuit A3 (not shown), and so on
One positive-phase output and the other negative-phase output of two adjacent 2N-1 are connected to a two-man power AND circuit AI or A2N-
1 input. In addition, two-person AND circuit Al,
The other input of AL is always at high level (power supply voltage V.0
). Also, 2N = 2N- of each of the manual AND circuits AI or A2 1
One output is input to the encoder circuit E1, and the encoder circuit E1 encodes 21 inputs into N inputs,
Output to output buffer circuit 01, output buffer circuit 01
amplifies N inputs and outputs them as data D1 to DN.

Next, the operation of one embodiment of the present invention will be explained. The comparator circuits C1 to C2N-1 have two inputs, one a common analog input voltage AIN via the buffer circuits B1 to BM.

The other side compares the levels of individual reference voltages Vrl to Vr2N1 for the comparator circuits CI to 02N1, respectively. As a result, among the converter circuits C1 to C21, if the input from the buffer circuits B1 to BM is higher than the reference voltages Vrl to Vr21, the positive phase output will have a high level, and the negative phase output will have a low level. Outputs the level and conversely the reference voltage Vrl or Vr2N-1
If the input from the buffer circuits B1 to BM is lower, its positive phase output is a low level, and its negative phase output is a high level. For this reason, two-person AND circuit AI or A
Comparator circuits CI to C2 input to 2N-1
If two adjacent outputs of N-1 are the same, the levels of one positive-phase output and the other negative-phase output will always be different. If this applies to you, the output will be at a low level.

Furthermore, if two adjacent outputs of the comparator circuits C1 to C2N1 input to the two-manufactured AND circuits AI to A2N-1 are different, the level of the positive phase output of one and the negative phase output of the other will always be the same. , the output of the two manual AND circuits A1 to A2N1 corresponding to this becomes a high level.

By the way, two adjacent comparator circuits CI to 02N-1, for example, comparator circuits C21 and C
22 (not shown) have different outputs. In this case, 2 of the comparator circuit C21 (not shown)
the analog input voltage AIN via one of the buffer circuits B1 to BM and the reference voltage v'
21, the reference voltage v'21 has a higher level than the analog input voltage AIN via one of the buffer circuits B1 to BM.

However, since the levels of the reference voltages Vrl to Vr20 are higher than the reference voltage v'21, the outputs of the comparator circuits C1 to C21 are all the same.

In addition, in the above situation, the comparator circuit C22 (
(not shown), i.e. the analog input voltage AIN via one of the buffer circuits B1 to BM.
When comparing the reference voltage v'22, the buffer circuit B1
or BM via one of the analog input voltages AI
The level of the reference voltage V'22 is lower than that of N. However, the level of the reference voltage V'23 or Vr21 is even lower than the level of the reference voltage V'22, so
The outputs of comparator circuits C22 to C2N-1 will all be the same. In this way, there is only one pair of comparator circuits C1 to C2N1 in which two adjacent outputs are different, and therefore two-man AND circuits A1 to A
There is only one out of 2 1 whose output is at a high level.

Then, the encoder circuit E1 receives the analog input voltage A based on the output of the two manual AND circuits AI to A2N-1.
An N-bit digital signal obtained by A/D converting IN is output, and this digital signal is derived as digital data outputs D1 to DN via an output buffer circuit 01.

FIG. 2 is a circuit diagram showing the internal circuits of buffer circuits B1 to BM shown in FIG. 1. As shown in the figure, since the configuration is a voltage follower in which the output of the differential amplifier circuit 1 is fed back by the emitter follower circuit 2, the analog input voltage AIN and the analog output voltage AlN1 have the same voltage value. Note that the buffer circuits B1 to BM
The input capacitance is the capacitance between the base, collector, base, and emitter of the bipolar transistor of the emitter follower circuit 1, and the wiring capacitance of the wiring that transmits the analog input voltage AIN to the base. This input capacitance is approximately equivalent to the input capacitance of the comparator circuits CI to C2N-1 shown in FIG.

As described above, in this embodiment, the comparator circuits C1 to C21 are divided into M groups, and M buffer circuits B1 to BM are provided.
Each group is connected in correspondence. Therefore, since the number of circuits to which the analog input voltage AIN is connected is reduced from 2N-1 to M, the analog input voltage AI
The input capacitance for N can be small. Further, the comparator circuit to be driven by each of the buffer circuits B1 to BM is one of all the comparator circuits C1 to C2N-1.
Since only one group is required, the input capacitance to be driven by one buffer circuit is also small. As a result, the distortion of the analog input terminal AIN is reduced, and the delay caused in the propagation of the analog input terminal is also reduced.

In addition, the two-man power AND circuits AI to A2 shown in FIG.
Even if N-1 is made into an exclusive OR circuit and both positive phase outputs of two adjacent comparator circuits C1 to C2'-1 are input to the exclusive OR circuit, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of comparator circuits to which different reference voltages are given to one input are divided into a plurality of comparator circuit groups, and a pre-stage By providing multiple buffer circuits in the , analog input terminals are provided to the multiple buffer circuits, and the output of each buffer circuit is provided to the other input of each comparator circuit in the corresponding comparator circuit group, so that the analog input voltage The number of circuits connected to the buffer circuit is reduced, and the number of comparator circuits to be driven by each buffer circuit is also reduced, which reduces the distortion of the analog input voltage and the delay between the comparator circuits that occurs in the propagation of the analog input terminal. effective.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an implementation of an A/D converter circuit according to the present invention, FIG. 2 is a circuit diagram showing an example of the buffer circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional A/D converter. FIG. 4 is a circuit diagram showing an example of the comparator circuit shown in FIG. 3. In the figure, VR1 and VR- are reference voltage sources, R1 is a reference resistor, Vrl to Vr2N-1 are reference voltages, AIN is an analog input voltage, B1 to BM are buffer circuits, and C
I to C21 are comparator circuits, A1 to A2'
-1 is a two-man power AND circuit, ■ is a power supply voltage, El is an encoder circuit C circuit, 01 is an output buffer 7 circuit, and DI or DN are digital data outputs. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A plurality of comparator circuits each having a different reference voltage given to one input, and a plurality of comparator circuits that are divided into a plurality of comparator circuit groups, and a plurality of comparator circuits provided corresponding to each of the comparator circuit groups. A buffer circuit, wherein an analog input voltage is applied to the inputs of the plurality of buffer circuits, and an output of the plurality of buffer circuits is applied to the other input of each comparator circuit in the corresponding comparator circuit group. /D converter circuit.