JPH0778763B2 - Cache memory system - Google Patents

Description

The present invention relates to a cache memory system used in a computer.

[Prior Art] The operation speed of the main memory is slower than the operation speed of the CPU. In order to improve the operation efficiency of the CPU, a method of storing data read from the main memory in a cache memory that can operate at high speed and reading the data from the cache memory when rereading the data is generally used.
Figure 6 shows, for example, CQ Publisher's "Interface" 1987 9
It is a block configuration diagram of a cache memory taken out for explanation only one way of a 4-way set associative cache memory as described on page 250 of the monthly issue.

In the figure, 1 is an address signal for accessing the cache memory, and 2, 3 and 4 are a tag address, an entry address and a word address which are part of the address signal 1, respectively. 5 is a tag address memory that holds the tag address in the cache memory, 6 is a valid bid memory that indicates whether the data held in the data memory 7 is valid or invalid, and the valid bit is' The data is valid when it is H and invalid when it is L. Reference numeral 7 is a data memory for holding the data in the cache memory. Reference numeral 8 is a comparator for comparing the tag address 2 of the address signal 1 with the tag address held in the tag address memory 5 to check whether they match, and 9 is the data memory 7 according to the word address 4. From the valid bit memory 6 and the word address 4, a control circuit controlled by the word address 4, a hit signal output from the control circuit 10, and a word selector 9 is a data signal output from the decoder, 13 is a decoder for the entry address 3, 14 is a decode signal output from the decoder 13, and 15 is a miss signal output from the control circuit 10.

Next, the operation will be described.

First, the read operation of the conventional cache memory will be described. In this example, the word address 4 is used for convenience of explanation.
Is 1 bit, the entry address 3 is 2 bits, and the tag address 2 is 3 bits. External address signal 1
Is given, the entry address 3 is assigned to the decoder 13
The contents of the tag address memory 5 selected by the decoded signal 14 obtained by the above are sent to the comparator 8, and the contents of the data memory 7 selected in the same manner are sent to the word selector 9, Select word data. In this example, two word data correspond to one entry address. Further, the contents of the selected tag address memory 5 are checked by the comparator 8 as to whether they match the tag address 2, and the result is checked by the control circuit.
Send to 10. In this example, 2 is used to indicate whether each of the two word data corresponding to one entry address is valid or invalid.
Have a bit valid bit. In the control circuit 10, the value of the valid bit corresponding to the word data selected by the word address 4 is'H ', and the data designated by the address signal 1 based on the output of the comparator 8 is present in the cache memory. At this time, the hit signal 11 is generated at a predetermined timing. This hit signal 11 is sent to the outside of the cache memory and the word selector 9 and the hit signal
When 11 is'H ', the selected word data is output as the data signal 12. When a cache miss occurs, the miss signal 15 is set to "H", the main memory outside the cache memory is activated to read the data, the data is sent to the CPU, and the data is stored in the data memory 7 in the cache memory.

Next, the write operation of the conventional cache memory will be described. When the address signal 1 is externally applied, the address hit determination is performed similarly to the read operation, and when the hit signal 11 is "H", the value of the data signal 12 is written in the data memory 7. When the hit signal 11 is'L ', nothing is done.

Here, the operation of the cache memory at startup will be described. In this cache memory, the internal register is reset after the reset signal becomes active, and then the cache memory automatically starts its operation. Since it operates immediately after resetting, there is a problem that a data group for initial value setting, which has no effect even when loaded in the cache memory, is loaded in the cache memory.

The following solutions to this problem are generally known. In other words, the cache memory is activated by writing a value to the cache activation bit of the internal register of the cache memory by a program. This solves the problem that a data group for initial value setting, which has no effect even when loaded in the cache memory, is loaded in the cache memory.

[Problems to be Solved by the Invention] In a conventional cache memory system, a cache memory is newly activated in a computer system because the cache memory is activated by writing a value to a cache activation bit of an internal register of the cache memory by a program. When incorporating, there is a problem that it is necessary to change the program up to that point.

The present invention has been made to solve the above problems, and an object thereof is to obtain a cache memory system having a mode in which a program need not be changed when a cache memory is newly installed.

[Means for Solving the Problem] A cache memory system according to claim 1 of the present invention is a cache memory system including a start register for setting a start start of a cache memory by a program, using the start register. A selection means is provided for selecting, based on an external selection signal, whether to start the operation of the cache memory or to always set the cache memory to the operating state regardless of the setting value of the start register.

The cache memory system according to claim 2 is a cache memory system including a register for setting a mode of the cache memory by a program, and an external terminal for setting the mode regardless of the register, and an external terminal for setting the mode. It is provided with a selection means for selecting which of the setting contents of the terminal and the setting contents of the register is valid based on an external selection signal.

[Operation] In the cache memory system according to claim 1 of the present invention,
When the signal for selecting the cache memory activation start method specifies activation in the activation register, the cache operation is started in the activation register, and the signal for selecting the cache memory activation start method always activates the cache memory. When the one to be set is selected, the cache memory always operates regardless of the value of the start register.

Further, in the cache memory system according to claim 2, when the signal for selecting the mode setting method of the cache memory enables the setting by the external terminal, the mode according to the setting content of the external terminal is set, and the mode of the cache memory is set. When the signal for selecting the setting method enables the setting by the register, the mode is set according to the setting contents of the register.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In addition,
The same reference numerals are used for the same or corresponding parts as in FIG. 6,
The description is omitted.

FIG. 1 is a system configuration diagram of an embodiment of the present invention. In the figure, 20 is a CPU, 21 is a cache memory, 22 is a control signal, 23 is a decoder, 24 is a chip select signal, 25 is a start mode selection signal from an external terminal, 26 is a reset signal, and 27 is a main memory. The address signal 1, the data signal 12, and the control signal 22 are connected to the CPU 20, the cache memory 21, and the main memory 27. The address signal 1 is also sent to the decoder 23, and a chip select signal 24 is output from the decoder 23 to the cache memory 21 as a decoding result. When the chip select signal 24 is at the “H” level, the activation register of the cache memory 21 can be accessed. The activation mode selection signal 25 specifies that the operation of the cache memory 21 is started using the activation register when it is at the'L 'level, and it is always at the'H' level regardless of the setting value of the activation register. Is a signal designating to set to the operating state, and corresponds to the external selection signal of claim 1. When the reset signal 26 becomes "H" level when the operation of the cache memory 21 is started using the start register, the contents of the start register are reset and the cache memory 21 becomes inactive.

The basic operation of the cache memory 21 is the same as that described in the conventional example. The activation method of the cache memory 21 and its control are different. Therefore, the cache memory 21
The starting method and its control circuit will be described with reference to FIG.

FIG. 2 is a circuit configuration diagram showing a specific example of the start register of the cache memory 21 of the present invention. In the figure, 30 is an A0 signal which is a part of the address signal 1, 31 is a D0 signal which is a part of the data signal 12, 32 is a cache memory activation signal, 33 is an AND gate, 34a to 34d are inverter gates, and 35 is A start register, 36 to 38 are N-channel transistors, 39 is an OR gate corresponding to the selecting means of claim 1, 40 is a register output signal, and 41 is GND. The cache memory activation signal 32 is an internal signal of the cache memory 21, and when the cache memory activation signal 32 becomes the “H” level, the cache memory 21 starts its operation. Cache memory start signal
The internal operation control circuit of the cache memory 21 using the 32 is well known and is not directly related to the gist of the present invention, and therefore its explanation is omitted.

In FIG. 3, the start mode selection signal 25 is set to the “L” level,
3 is a timing chart of the circuit of FIG. 2 when the operation of the cache memory 21 is started using the activation register 35. When the reset signal 26 becomes the “H” level, the N-channel transistor 38 turns on, the point A becomes the “L” level, and the register output signal 40 becomes the “L” level. Therefore, the cache memory activation signal is sent via the OR gate 39. 32 becomes'L 'level. When the AO signal 30 goes to the “H” level while the chip select signal 24 is at the “H” level, the N-channel transistor 37
Turns on and the N-channel transistor 36 turns off. Therefore, the value of the DO signal 31 is written in the activation register 35. At this time, if the value of the D0 signal 31 is'H 'level by the program, the activation register 35 is set, the register output signal 40 becomes'H' level, and the cache memory activation signal 32 becomes'H 'level via the OR gate 39. Since it is at the'level, the cache memory 21 is in the operating state.

In FIG. 4, the start mode selection signal 25 is set to the “H” level,
6 is a timing chart of the circuit of FIG. 2 when the cache memory 21 is always set to an operating state regardless of the setting value of the start register 35. In this state, since the start mode selection signal 25 is at the'H 'level, regardless of the value of the register output signal 40, that is, the set value of the start register 35, OR
The cache memory activation signal 32, which is the output of the gate 39, is always at the'H 'level.

In this example, one of the address signals 1, A0 signal 30
Although the start register 35 is selected by using, it is clear that the same effect can be obtained by selecting a plurality of registers with a plurality of address signals.

Next, a second embodiment of the present invention will be described.

In the embodiment described with reference to FIGS. 1 to 4, the mode without the start register 35 can be supported by the start mode selection signal 25 so that the cache memory can be connected (embedded) without changing the software. did. By having a register inside the cache memory 21 other than this start register, there is a high-performance cache memory in which the mode of the cache memory can be set by a program. This register contains, for example, Japanese Patent Laid-Open No. 1-1876.
There is a method of designating an instruction cache and a data cache as shown in Japanese Patent Laid-Open No. 50. The second embodiment of the present invention will be described as an example in which the cache memory can be connected (embedded) without changing the software while maintaining the performance of the high-performance cache memory in which the mode of the cache memory is set by the register. An example will be described below.

FIG. 5 is a circuit configuration diagram showing an essential part of the second embodiment of the present invention. In the figure, 25 is a start mode selection signal corresponding to the external selection signal of claim 2, 40 is a register output signal, 50 is an external mode setting terminal which is an external terminal of the cache memory 21, 51 is a mode setting signal, and 52a, 52b. Is an AND gate, 53 is an inverter gate, and 54 is an OR gate, and these constitute the selecting means 55 of claim 2.

Next, the operation of the second embodiment will be described.

When the startup mode selection signal 25 is at the “H” level, the value of the external mode setting terminal 50 which is the external terminal of the cache memory 21 is selected and output as the mode setting signal 51. When the activation mode selection signal 25 is at the'L 'level, the value of the register output signal 40 is selected and output as the mode setting signal 51. In this way, it is possible to select the method of setting the mode setting of the cache memory 21 with the value of the register or the method of setting with the external terminal, and when setting the mode of the cache memory using the register, Since the value of the external terminal becomes invalid, it is possible to use this external terminal for realizing other functions. As described above, in the second embodiment of the present invention, it is possible to realize a system in which the cache memory can be connected without changing the software while maintaining the performance of the highly functional cache memory.

In the second embodiment, the value of the register output signal 40 and the external mode setting terminal 50 are changed by the start mode selection signal 25.
However, it is also possible to select the value of the register output signal 40 and the value of the external mode setting terminal 50 by a signal other than the start mode selection signal 25. Also, although the register output signal 40 and the external mode setting terminal 50 each have one signal as an example, it is obvious that the present invention can be applied to a case where the mode of the cache memory 21 is designated by a plurality of signals.

[Effects of the Invention] As described above, according to the present invention, it is possible to configure a high-performance cache memory system that performs startup setting and mode setting by using the internal register of the cache memory, and it is not necessary to change the program. By selecting a mode, it is possible to easily change from a system without a cache memory to a system with a cache memory without changing the program.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a cache memory system according to an embodiment of the present invention, and FIG. 2 is a circuit configuration diagram showing a specific example of a start register of a cache memory system according to the present invention, FIGS. 3 and 4. Is a timing chart showing the operation of the circuit shown in FIG. 2, FIG. 5 is a circuit configuration diagram showing an essential part of another embodiment of the present invention, and FIG. 6 is a block configuration diagram of a conventional cache memory. 1 is an address signal, 2 is a tag address, 3 is an entry address, 4 is a word address, 5 is a tag address memory, 6 is a valid bid memory, 7 is a data memory, 8
Is a comparator, 9 is a word selector, 10 is a control circuit, 11 is a hit signal, 12 is a data signal, 13 is a decoder, 14 is a decode signal, 15 is a miss signal, 20 is a CPU, 21 is a cache memory, and 22 is a control. Signal, 23 is a decoder, 24 is a chip select signal, 25 is a start mode selection signal (external selection signal), 26 is a reset signal, 27 is a main memory, 30 is an A0 signal,
31 is D0 signal, 32 is cache memory start signal, 33, 52a, 5
2b is an AND gate, 34a to 34d, 53 are inverter gates, 35 is a start register, 36 to 38 are N channel transistors, 39 is
OR gate (selection means), 40 is register output signal, 41 is GN
D and 50 are external mode setting terminals (external terminals), 51 is a mode setting signal, 54 is an OR gate, and 55 is a selecting means. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A cache memory system comprising a start register for setting a start start of a cache memory by a program, regardless of whether the operation of the cache memory is started by using the start register or a set value of the start register is set. A cache memory system characterized by comprising selection means for selecting whether to always set the cache memory to an operating state based on an external selection signal. 2. A cache memory system including a register for setting a mode of a cache memory by a program, an external terminal for setting the mode regardless of the register, setting contents of the external terminal, and the register. 2. A cache memory system, comprising: selecting means for selecting which of the setting contents of 1 to be valid based on an external selection signal.