JPH08202617A - Memory interface circuit and microprocessor system - Google Patents

Abstract

PURPOSE: To increase the memory access speed in a microprocessor system which includes plural memories. CONSTITUTION: The interface circuit controls the transfer of data between a microprocessor 101 and a memory 102 and has a latch circuit 201. The circuit 201 latches an address 120 when the memory 102 is selected and also the address 120 having the contents different from the present latch output 202 is outputted from the microprocessor 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface circuit for controlling access to a memory in response to an address output from a microprocessor and a microprocessor system using the circuit.

[0002]

2. Description of the Related Art In recent years, the operating speed of CPUs has been remarkably improved. However, since the access speed of the main storage device such as DRAM is slower than the operation rate of the CPU, a high speed memory is generally used as a part of the memory. The high-speed memory is a memory in which the CPU specifies an address of the memory and the access time until the memory outputs the data to the bus is much shorter than a general memory, and a typical one is a cache memory. SRAM is used as the cache memory, but the access time is 20n
s or less, which is extremely high speed. However, since the cache memory is expensive, which is more than 10 times the price of a general DRAM, it has a drawback of increasing the price of the product.

Therefore, a method for accessing data at high speed has been developed by devising an access method in a general memory, instead of shortening the access time by the characteristic of its structure like a high speed memory. This method selects a specific row by inputting a row address, connects all the memory cells in the row to the bit line group, and then continuously accesses the bit line group to continuously access the memory cells in the same row. In addition, high-speed access is performed. Specifically, this operation mode includes a high-speed mode such as a page mode and a static mode. By effectively utilizing this function, it is possible to speed up memory access in local address access such as program code prefetch and data block transfer in the microprocessor.

The interface circuit for the page mode access is conventionally constructed as shown in FIG. Here, R is used as the memory A 102 and the memory B 108.
OM is used. These memories 102 and 108 are in an operating state because the active high level signal is constantly applied to the chip enable CE.

When the microprocessor 101 executes an access instruction to the memories 102 and 108 such as READ,
The address signal 135 to the memory is output. This address signal 135 is the page address 1 on the upper address bus.
20 and the lower address 121 on the lower address bus, and is sent to the memories 102 and 108 as they are. The page address 120 is also supplied to the comparator 104, the page address latch 103, and the decoder 106.

The page address latch 103 has an address strobe signal 12 from the microprocessor 101.
7 latches the page address 120 in synchronization with the inverted edge from the active low level to the high level, and outputs the latched page address to the comparator 104.

The comparator 104 compares the page address latched and output by the page address latch 103 with the page address 120. If they match, the same page signal 123 output to the state latch circuit 111 is set to active high level, and if they do not match, it is set to inactive low level.

The decoder 106 has a page address 120.
Is the address of the memory A 102, the chip select signal 124 is set to active high level.

The address strobe signal 127 from the microprocessor 101 takes an active low level together with the output of the address signal 135, and changes to a high level after a lapse of a fixed time. The decoder 106 completes its decode output during the active period of the address strobe signal 127.

The state latch circuit 111 latches the same page signal 123 in response to the address strobe signal 127 when the chip select signal 124 is at the active level. When the latched same-page signal 123 is at active high level, the high-speed access signal 129 of active high level is output to the wait control circuit 105, and when inactive, the low-speed access signal 130 is set to active high level. When the chip select signal 124 from the decoder 106 is inactive, the state latch circuit 111 is in the reset state regardless of the same page signal 123, and both the high speed access signal 129 and the low speed access signal 130 are inactive.

The weight control circuit 105 includes a memory A10.
Data is transferred to the data bus 12 after 2 is addressed.
6, the wait signal A132 of active high level delays the reading of the data on the data bus 126 by the microprocessor 101 by the delay time until the output to A6.
Is output to the microprocessor 101. The microprocessor 101 performs an operation of delaying the reading of the data on the data bus 126 while the wait signal 131 is at the active level, and the time during which the wait signal A 132 is active is preset in the wait control circuit 105. In response to the clock signal 134 from the microprocessor 101, the wait signal A132 is activated for the time corresponding to the predetermined number of clocks. In this conventional example, when the high speed access signal 129 is active, the wait signal A132 is inactive, and when the low speed access signal 130 is active, the wait signal A132 is activated for a time corresponding to two clocks. Since the delay time varies depending on the type of memory,
The setting value is different for each wait control circuit of each memory, and in this example, when the memory B 108 is accessed at high speed, the output control circuit 109 for the memory B 108 outputs the wait signal B
The wait signal B133 is set to be active only for a time corresponding to one clock when accessing 133 inactive and at low speed. When both the high speed access signal 129 and the low speed access signal 130 are inactive, the wait signal A132 becomes inactive.

The microprocessor 101 checks whether or not the wait signal 131 is active, for example, at each rising edge of the clock, and if it is active, the data bus 1
When the operation of reading the data on 26 is postponed and the inactivity is confirmed, the data reading operation is performed at the falling edge of the clock at the time of the confirmation.

The memory A 102 has a chip select signal 12
When both 4 and the address strobe signal 127 are at the high level, the output enable signal A125, which is the output of the AND circuit 110, becomes the active high level, so that the data can be output onto the data bus 126. The same applies to the memory B108, and when the output enable signal B128 is active, the memory B108
The data 108 can output data onto the data bus 126.

In FIG. 6, the interface between the memory A 102 and the microprocessor 101 is described in detail, and the interface between the memory A 102 and the memory B 108 having a different access speed is the memory A.
Since it has the same configuration as the interface in 102, this is simply described as the memory B output control circuit 109.

Further, in FIG. 6, the number of memories is represented by memory A.
Although only 102 and memory B108 are described,
This is for ease of explanation, and it is of course possible that a large number of various memories are connected to the microprocessor 101 via the interface circuit.

Next, the memory access of this system will be described with reference to the timing chart of FIG. FIG. 7 shows four memory accesses 1, 2, 3 and 4, which will be described in order below. (1) Access 1 The microprocessor 101 outputs the page address a of the memory A102 to access the memory A102. At this time, since the address x is latched in the page address latch 103 as the previous access to the memory B 108, the comparator 104 sets the same page signal 123 to the inactive level.

On the other hand, the decoder 106 uses the page address a.
Is decoded and the chip select signal 124 is activated. Therefore, when the address strobe signal 127 becomes inactive high level, the output enable signal A125 becomes active.
2 becomes a state in which data can be output onto the data bus 126. However, at this time, the access time peculiar to the memory A, that is, the address signal is input to the memory A 102,
Since it takes less time to output the data to the data bus 126, the memory A 102 cannot output the data to the data bus 126 in practice. However, in the output enabled state, signals other than the data of the desired address may be output to the data bus 126. However, when the wait signal 131 described later is active, the microprocessor 101 is on the data bus 126. No data is read, so there is no problem.

Since the same page signal 123 is inactive at the time when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the inactive signal and the low speed access signal 130.
To activate. When the low-speed access signal 130 becomes active, the wait signal A132 for the microprocessor 101 of the wait control circuit 105.
Is activated, the microprocessor 101 does not capture the data on the data bus 126 at the falling edge of the clock T2.

The wait control circuit 105 includes a memory A10.
2, the wait signal A13 is waited until the rise of the clock of the microprocessor 101 is counted twice.
The microprocessor 101 cannot read the data on the data bus 126 even at the clock TW1 because it is set so as not to make inactive. However, if the rising edge of TW1 is counted, it means that the rising edges of the clocks T2 and TW1 are counted twice. Therefore, the wait control circuit 105 makes the wait signal A132 inactive.

When the wait signal 131 is confirmed by the microprocessor 101 at the rising edge of the clock TW2, the wait signal 131 is inactive.
The memory A data output on the data bus 126 is read at the trailing edge of. Then, the next instruction is executed and the address signal 135 designated by the instruction is output. Here, the next page address is the page address a.
Suppose

It is assumed that the memory A 102 normally requires a time of about 4 clocks from the input of the address signal 135 to the output of data on the data bus 126. (2) Access 2 The microprocessor 101 outputs the same memory page address a to access the memory A102. At this time, the page address latch 103 is stored in the previous memory A
Since the page address a for accessing 102 is latched, the comparator 104 keeps the same page signal 123 active.

On the other hand, the decoder 106 uses the page address a.
Of the chip select signal 12
Keep 4 active. Since the output enable signal A125 becomes active when the address strobe signal 127 becomes inactive, the memory A102 becomes ready to output data onto the data bus 126. At this point, the access time peculiar to the memory A,
That is, since the time until the address signal is input to the memory A102 and the data is output to the data bus 126 is less than the time, the memory A102 cannot output the data to the data bus 126 in practice.

Since the same page signal 123 is active at the time when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the active signal and activates the high speed access signal 129. When the high-speed access signal 129 becomes active, the wait signal A132 for the microprocessor 101 of the wait control circuit 105 becomes inactive, so that the microprocessor 101 captures the data on the data bus 126 at the falling edge of the clock T2. The next instruction is executed and the address signal 135 designated by the instruction is output. Here, it is assumed that the next page address 120 is the same memory page address b for accessing the memory B108.

The normal access time of the memory A 102 is about 4 clocks, but here the page address 120 is the same as the page address a as access 1.
Therefore, in the memory A102, all the memory cells corresponding to the page address a and the bit line group are already connected, and therefore the time for newly connecting all the memory cells of the page address and the bit line group can be omitted. . Therefore, the access time can be shortened to about 2 clocks because it is only necessary to consider the time for selecting the bit line group by changing the lower address. (3) Access 3 The microprocessor 101 outputs the same memory page address b to access the memory B108. At this time, the page address latch 103 is stored in the previous memory A
Since the page address a for accessing 102 is latched, the comparator 104 inactivates the same page signal 123.

On the other hand, the decoder 106 uses the page address b
Is not for accessing the memory A 102, the chip select signal 124 is made inactive. As a result, the output enable signal A125 becomes inactive, and the memory A102 becomes incapable of outputting data to the data bus 126.

Since the chip select signal 124 is inactive, the wait control circuit 10 of the memory A 102 is
5 is reset, so its output is inactive.

On the other hand, when the wait signal B133 from the memory B output control circuit 109 dedicated to the memory B in which the page address b exists is activated, the microprocessor 101 sends the wait signal 131 via the OR circuit 107.
Make sure is active.

Since the output control circuit 109 for the memory B is set so as not to inactivate the wait signal B133 until the rising edge of the clock of the microprocessor 101 is counted once, the microprocessor 101 also operates at the clock T2. , Data bus 126
The above data cannot be read.

However, the wait signal 1 by the microprocessor 101 at the rising edge of the clock TW1
In the confirmation of 31, since the wait signal 131 is inactive, the microprocessor 101 reads the memory B data output on the data bus 126 at the falling edge of the clock TW1 and simultaneously executes the next instruction. , And outputs the address signal 135 designated by the instruction. Here, it is assumed that the next page address is the same memory page address a for accessing the memory A.

It is assumed that the memory B 108 normally requires about 3 clocks from the input of the address signal to the output of the data on the data bus 126. (4) Access 4 The microprocessor 101 outputs the same memory page address a to access the memory A102. At this time, the page address latch 103 is stored in the previous memory B
The page address b for accessing 108 is latched. Therefore, since the page address 120 for accessing the memory A 102 this time is the page address a unlike the page address b in the access 3,
The memory A 102 must newly connect all the memory cells of the page address a and the bit line group. Therefore, the access time requires about 4 clocks. The operation at this time is similar to the operation in access 1.

As described above, when the conventional interface circuit is used, when the same page address is continuously accessed, the access time can be shortened as compared with the case where different page addresses are accessed, that is, high speed access is possible. .

[0032]

However, in the above-mentioned interface circuit, the microcomputer 101 accesses the memory B 108 after the page address a of the memory A 102 is accessed, and then the memory A 10 is further accessed.
Even when the page address a of 2 is accessed, the memory A 102 again requires the normal access time of about 4 clocks for access.

An object of the present invention is to provide an interface circuit which enables high-speed continuous access to a memory to continue even when an access to another memory or I / O unit is inserted.

[0034]

SUMMARY OF THE INVENTION The present invention is a memory interface circuit having latch means for latching an address output from a microprocessor and controlling access to a memory by the output of the latch means. The output of the microprocessor is latched only when the microprocessor outputs an address different from the address latched by the latch means and which specifies the memory.

[0035]

According to the present invention, when the microprocessor accesses the second memory after accessing the first page address of the first memory among the plurality of memories, the latch in the interface circuit of the first memory is used. The circuit remains unchanged while latching the first page address.
Therefore, when the microprocessor again accesses the first page address of the first memory, all the memory cells corresponding to the first page address of the first memory and the bit line group are already connected, The time for newly connecting all the memory cells of the page address and the bit line group can be omitted. Therefore, the access time of the memory in this case can be shortened because it is sufficient to consider only the time for selecting the bit line by the lower address.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] First, a first embodiment of the present invention will be described with reference to the configuration diagram of FIG. 1 and the timing diagram of FIG.

In this embodiment, unlike the conventional example of FIG. 6 in which the page address 120 is directly input to the memory A 102, the page address 120 is input to the memory A 102 via the page address latch 201. Further, through the page address latch 201, the memory A10
2 is input, and page address latch 2
01 is characterized in that the page address 120 is latched when the address strobe enable signal 205 is active and the address strobe signal 127 is inactive.

Here, the memory A102 and the memory B1
No. 08 uses a ROM as in the conventional example. Further, the same numbers as those used in the conventional example are given to those performing the same operation as in the conventional example. Although only two memories A102 and B108 are shown in FIG. 1 for the purpose of facilitating the description, more various and many memories are provided in the microprocessor 101 via the interface circuit. Of course, you may be connected to.

It is also possible to use an interface circuit for a part of many memories.

The memory access of the present system having the above characteristics will be described with reference to the timing chart of FIG. FIG. 2 shows four memory accesses 1, 2, 3, and 4, which will be described in order below. (1) Access 1 The microprocessor 101 outputs the same memory page address a to access the memory A102. At this time, the page address latch 103 is stored in the previous memory A
Since the page address x for accessing 102 is latched, the comparator 104 outputs the same page signal 123.
To the inactive level.

On the other hand, the decoder 106 uses the page address a.
Is decoded and the chip select signal 124 is activated. Therefore, when the address strobe signal 127 becomes inactive high level, the output enable signal A125 becomes active.
Is ready to output data onto the data bus 126.
However, at this time, the access time peculiar to the memory A, that is, the time until the address signal is input to the memory A 102 and the data is output to the data bus 126 is less than the access time, so the memory A 102 actually outputs the data to the data bus 126. Can not do it. However, in the output enabled state, signals other than the data of the desired address may be output to the data bus 126. However, when the wait signal 131 described later is active, the microprocessor 101 is on the data bus 126. No data is read, so there is no problem.

Since the same page signal 123 at the time when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the inactive signal and the low speed access signal 130.
To activate. When the low-speed access signal 130 becomes active, the wait signal A132 for the microprocessor 101 of the wait control circuit 105.
Is activated, the microprocessor 101 does not capture the data on the data bus 126 at the falling edge of the clock T2.

When the address strobe signal 127 becomes inactive, the page address latch 201 latches and outputs the page address a because the AND output with the inversion signal of the same page signal 123 becomes active high level. .

The wait control circuit 105 has a memory A10.
2, the wait signal A13 is waited until the rise of the clock of the microprocessor 101 is counted twice.
The microprocessor 101 cannot read the data on the data bus 126 even at the clock TW1 because it is set so as not to make inactive. However, if the rising edge of TW1 is counted, it means that the rising edges of the clocks T2 and TW1 are counted twice. Therefore, the wait control circuit 105 makes the wait signal A132 inactive.

When the wait signal 131 is confirmed by the microprocessor 101 at the rising edge of the clock TW2, the wait signal 131 is inactive.
The memory A data output on the data bus 126 is read at the falling edge of, the next instruction is executed at the same time, and the address signal 135 designated by the instruction is output. Here, the next page address is the page address a.
Suppose

It is assumed that the memory A 102 normally requires about 4 clocks from the input of the address signal 135 to the output of data onto the data bus 126. (2) Access 2 The microprocessor 101 outputs the same memory page address a to access the memory A102. At this time, the page address latch 201 is stored in the previous memory A.
Since the page address a for accessing 102 is latched, the comparator 104 keeps the same page signal 123 active.

On the other hand, the decoder 106 uses the page address a
Of the chip select signal 12
Keep 4 active. Since the output enable signal A125 becomes active when the address strobe signal 127 becomes inactive, the memory A102 becomes ready to output data onto the data bus 126. At this point, the access time peculiar to the memory A,
That is, since the time until the address signal is input to the memory A102 and the data is output to the data bus 126 is less than the time, the memory A102 cannot output the data to the data bus 126 in practice.

Since the same page signal 123 is active when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the active signal and activates the high speed access signal 129. When the high-speed access signal 129 becomes active, the wait signal A132 for the microprocessor 101 of the wait control circuit 105 becomes inactive, so that the microprocessor 101 captures the data on the data bus 126 at the falling edge of the clock T2. The next instruction is executed and the address signal 135 designated by the instruction is output. Here, it is assumed that the next page address 120 is the same memory page address b for accessing the memory B108.

The page address latch 201 is
Since the same page signal 123 is kept active, the page address a is not newly latched even if the address strobe signal 127 changes to the inactive high level.

The normal access time of the memory A 102 is about 4 clocks, but here the page address 120 is the same as the access 1
Therefore, in the memory A102, all the memory cells corresponding to the page address a and the bit line group are already connected, and therefore the time for newly connecting all the memory cells of the page address and the bit line group can be omitted. . Therefore, the access time can be shortened to about 2 clocks because only the time for selecting the bit line group by changing the lower address is taken into consideration. (3) Access 3 The microprocessor 101 outputs the same memory page address b to access the memory B108. At this time, the page address latch 201 is stored in the previous memory A.
Since the page address a for accessing 102 is latched, the comparator 104 inactivates the same page signal 123.

On the other hand, the decoder 106 uses the page address b
Is not for accessing the memory A 102, the chip select signal 124 is made inactive. As a result, the output enable signal A125 becomes inactive, and the memory A102 becomes incapable of outputting data to the data bus 126.

Since the chip select signal 124 is inactive, the wait control circuit 10 of the memory A 102 is
5 is reset, so its output is inactive. Further, when the chip select signal 124 is inactive, the address strobe enable signal 2
Since 05 becomes an inactive low level, even if the address strobe signal 127 changes to an inactive high level, the page address latch 201 does not perform a new latch and maintains the page address a.

On the other hand, when the wait signal B133 from the memory B output control circuit 109 dedicated to the memory B in which the page address b exists is activated, the microprocessor 101 causes the wait signal 131 via the OR circuit 107.
Make sure is active.

Since the memory B output control circuit 109 is set so as not to inactivate the wait signal B133 until the rising edge of the clock of the microprocessor 101 is counted once, the microprocessor 101 also operates at the clock T2. The data on the data bus 126 cannot be read.

However, the wait signal 1 by the microprocessor 101 at the rising edge of the clock TW1
In the confirmation of 31, since the wait signal 131 is inactive, the microprocessor 101 reads the memory B data output on the data bus 126 at the falling edge of the clock TW1 and simultaneously executes the next instruction. , And outputs the address signal 135 designated by the instruction. Here, it is assumed that the next page address is the same memory page address a for accessing the memory A.

It is assumed that the memory B 108 normally requires about 3 clocks from the input of an address signal to the output of data on the data bus 126. (4) Access 4 The microprocessor 101 outputs the same memory page address a to access the memory A102. At this time, since the page address a is latched in the page address latch 201, the comparator 104 activates the same page signal 123.

On the other hand, the decoder 106 uses the page address a
Of the chip select signal 12
Activate 4 Address strobe signal 127
Becomes inactive, the output enable signal A125 becomes active.
Becomes ready to output data on the data bus 126, but at this time, the access time peculiar to the memory A, that is, the time until the address signal is input to the memory A 102 and the data is output to the data bus 126 is not satisfied. ,
Virtually memory A 102 cannot output data to data bus 126.

Since the same page signal 123 is active when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the active signal and activates the high speed access signal 129. When the high-speed access signal 129 becomes active, the wait signal A132 for the microprocessor 101 of the wait control circuit 105 becomes inactive, so that the microprocessor 101 takes in the data on the data bus 126 at the falling edge of the clock T2.

The page address latch 201 is
Since the same page signal 123 is active, the page address a is not newly latched even when the address strobe signal 127 changes to the inactive high level.

Further, the normal access time of the memory A102 is about 4 clocks, but here, all the memory cells corresponding to the page address a and the bit line group in the memory A102 are already connected, and Therefore, the time for newly connecting all the memory cells of the page address and the bit line group can be omitted. Therefore, the access time is
Since it is only necessary to consider the time for selecting the bit line group due to the change of the lower address, the time can be shortened to about 2 clocks.

Thus, by using the interface circuit of the present invention, even if different memories are accessed,
When attention is paid to the same memory, when accessing the same page address of the memory continuously, high-speed access can be continuously performed, so that the access time can be shortened as compared with the conventional example.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to the configuration diagram of FIG. 3 and the timing diagram of FIG.

In this embodiment, unlike the first embodiment, the DRA in which the memory is provided with a latch means for the address signal 135.
Address signal 13 that is input to the memory by using M
In order to reduce the number of address buses by reducing the number of 5 bits and avoid complicating the circuit configuration, the page address and the lower address are sequentially input to the memory using the same bus. Is characterized in that a control circuit for switching these addresses is provided.

The DRAM control circuit 303 of this embodiment outputs the address select signal 304 when both the low speed access signal 130 and the high speed access signal 129 are inactive, that is, when the microprocessor 310 accesses a memory other than the memory A301. The inactive low level is set and the lower address 121 is output to the memory A301. At this time, the RAS signal 307 maintains the active low level and the CAS signal 308 maintains the inactive high level. However, since the CAS signal 308 is inactive, the memory A301 is connected to the data bus 1
No output to 26.

When the low speed access signal 130 changes to active, the address select signal 304 is set to active high level and the page address 120 is set to the memory A30.
Enter 1. At this time, at the same time, the RAS signal 307 is made inactive and precharged. Then, after counting once the falling edge of the clock after the RAS signal 307 becomes inactive, the RAS signal 307 is activated, the page address 120 output to the memory A301 is decoded, and this decoded output is held. As a result, the memory A301 connects all the memory cells of the specified page address to the bit line group. When the rising edge of the next clock is counted once, the address select signal 304 is made inactive and the lower address 121 is output to the memory A301. When the falling edge of the clock is counted once, the CAS signal 308 is activated, the lower address 121 output to the memory A301 is decoded, and the decoded output is held. When the decoding of the CAS signal 308 is completed, the memory A 301 outputs the data designated by the address signal 135 onto the data bus 126.

When the high speed access signal 129 changes to active, the change of the high speed access signal 129 triggers to change the CAS signal 308 to active,
At this time, since the lower address 121 output to the memory A address 302 is decoded and the decoded output is maintained, the memory A 301 outputs the data designated by the address signal 135 onto the data bus 126.

For convenience of explanation, the memory A3 is used here.
The present invention is used for the interface circuit for 01, and the memory B 108 and the output control circuit 109 for the memory B, which is the interface circuit, are the same as those in the conventional example.

Further, the same numbers as those in the conventional example are attached to those having the same operation as in the conventional example. However, regarding the microprocessor 310, since the memory A301 of this embodiment is a DRAM, in addition to the same functions as those of the first embodiment, the READ / WRITE signal 309 is output to the memory A301 when accessing the memory A301. , And has a function of controlling reading or writing with respect to the memory A301.

The row decoder and column decoder built in the memory A301 hold the respective decode outputs when the RAS and CAS signals are active, and decode the address on the memory A address 302 when the respective signals change from inactive to active. To do.

In FIG. 3, the number of memories is the memory A301,
Although only two memories B108 are shown, this is for ease of explanation, and it is of course possible that a large number of memories of various types are connected to the microprocessor 310. Therefore, some or all of the large number of memories may be connected to the microprocessor 310 via the interface circuit of the present application.

Next, the memory access of this system will be described with reference to the timing chart of FIG. Here, for the sake of convenience, for example, the microprocessor 310 accesses the memory A301 at the same time as the address signal 135 is output by R.
It is assumed that the EAD / WRITE signal 309 is set to active high level and only data is read from the memory A301. Since the memory A301 is a DRAM, R
It goes without saying that data can be read and written according to the EAD / WRITE signal 309. FIG. 4 shows four memory accesses 1, 2, 3, and 4
Are described and will be described in order below. (1) Access 1 The microprocessor 310 outputs the same memory page address a to access the memory A301. At this time, the page address latch 305 is stored in the previous memory A.
Since the page address x for accessing 301 is latched, the comparator 104 outputs the same page signal 123.
To the inactive level.

On the other hand, the decoder 106 uses the page address a.
Is decoded and the chip select signal 124 is activated.

Since the same page signal 123 is inactive at the time when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the inactive signal and the low speed access signal 130.
To activate. The wait signal A output from the wait control circuit 105 to the microprocessor 310 when the low-speed access signal 130 becomes active
Since 132 becomes active, microprocessor 3
10 is the data bus 126 at the falling edge of the clock T2
Do not capture the above data.

When the low-speed access signal 130 becomes active, the DRAM control circuit 303 activates the address select signal 304, so that the memory A address 302 indicates the page address a, and at the same time, the RAS signal 307 is sent for precharging. Make it inactive.
After the RAS signal 307 becomes inactive, the DARM control circuit 303 counts the falling edge of the clock once to activate the RAS signal 307. Therefore, the RAS signal 307 becomes active after the falling edge of the clock T2. As a result, the page address a is decoded by the row decoder built in the memory A, and all the memory cells of the page address a are connected to the bit line group.

The wait control circuit 105 has a memory A30.
At 1, the wait signal A13 is waited until the rising edge of the clock of the microprocessor 310 is counted twice.
2 is set not to be inactive, the microprocessor 310 cannot read the data on the data bus 126 even at the clock TW1. However, when the rising edge of TW1 is counted, the rising edges of T2 and TW1 are counted twice, so the wait signal A132 is made inactive.

The DRAM control circuit 303 uses the RAS signal 30.
When the rising edge of the clock input after 7 becomes active is counted once, the address select signal 30
4 is made inactive to set the memory A address 302 to the lower address 121, so that the memory A address 302 becomes the lower address 2 when the clock TW1 rises. Then, the CAS signal 308 becomes active at the falling edge of the clock TW1, and as a result, the lower address 2
Is decoded by the column decoder built in the memory A301, and the data is output to the data bus 126.

When the wait signal 131 is confirmed by the microprocessor 310 at the rising edge of the clock TW2, the wait signal 131 is inactive.
The memory A data output on the data bus 126 is read at the time of the falling edge, the next instruction is executed at the same time, and the address signal designated by the instruction is output. Here, it is assumed that the next address signal 135 is the page address a and the lower address 3.

The page address latch 305 is
Since the same page signal 123 was initially inactive, when the chip select signal 124 becomes active and the address strobe signal 127 changes to inactive, the page address a is latched.

Further, the memory A301 is normally provided on the data bus 126 while the CAS signal 308 is active.
It is assumed that the memory keeps outputting data upward. (2) Access 2 The microprocessor 310 outputs the same memory page address a to access the memory A301. At this time, the page address latch 201 is stored in the previous memory A.
Since the page address a for accessing 301 is latched, the comparator 104 keeps the same page signal 123 active.

On the other hand, the decoder 106 uses the page address a
Of the chip select signal 12
Keep 4 active.

Since the same page signal 123 is active when the address strobe signal 127 changes to inactive, the state latch circuit 111 latches the active signal and activates the high speed access signal 129. This high-speed access signal 129 triggers the DRAM control circuit 303 to activate the CAS signal 308, so that the column decoder built in the memory A301 decodes the lower address 3 on the memory A address 302 and transfers it to the data bus 126. Output the data specified by the address. In access 2, the low-speed access signal 130 does not change from inactive to active, so the DRAM control circuit 303 uses RA
Since the S signal 307 is kept active, the row decoder built in the memory A301 continues to output the page address a decoded by the access 1, so that the data on the data bus 126 can be transferred to the data bus 126 only when the lower address is newly selected. Can be output.

The page address latch 305 is
Since the same page signal 123 remains active, no new latch is performed even if the address strobe signal 127 changes to inactive.

When the high-speed access signal 129 becomes active, the wait signal A1 output from the wait control circuit 105 to the microprocessor 101.
Since 32 becomes inactive, the microprocessor 101 causes the data bus 126 to fall at the falling edge of the clock T2.
At the same time as fetching the above data, the next instruction is executed and the address signal 135 designated by the instruction is output. Here, it is assumed that the next address signal 135 is the page address b and the lower address 4 for accessing the memory B108. (3) Access 3 The microprocessor 310 outputs the same memory page address b to access the memory B108. At this time, the page address latch 305 is stored in the previous memory A.
Since the page address a for accessing 102 is latched, the comparator 104 inactivates the same page signal 123.

On the other hand, the decoder 106 uses the page address b
Is not for accessing the memory A301, the chip select signal 124 is made inactive.

Since the chip select signal 124 is inactive, the wait control circuit 10 of the memory A301 is
5 is in the reset state, and therefore the high speed access signal 12
9 and the low speed access signal 130 are both inactive. Therefore, the DRAM control circuit 303 maintains the RAS signal 307 active and the CAS signal 308 inactive, so that the row decoder built in the memory A301 maintains the decoded output of the page address a decoded by access 1, but the CAS signal Since 308 is inactive, data cannot be output onto the data bus 126. Further, when the chip select signal 124 is inactive, the address strobe enable signal 205 becomes inactive low level. Therefore, even if the address strobe signal changes to inactive high level, the page address latch 305 performs new latching. No
The page address a is maintained.

On the other hand, when the wait signal B133 from the memory B output control circuit 109 dedicated to the memory B108 becomes active, the microprocessor 310 causes the OR circuit 1 to operate.
Confirm that the wait signal 131 is active via 07.

The output control circuit 109 for the memory B is set so that the wait signal B133 is not made inactive until the rise of the clock of the microprocessor 310 is counted once in the memory B108. Data cannot be read on the data bus 126 even at the clock T2. However, when the rising edge of T2 is counted, the memory B output circuit 109 outputs the wait signal B133.
Inactivate.

Therefore, the wait signal 1 by the microprocessor 310 at the rising edge of the clock TW1
In the confirmation of 31, since the wait signal 131 is inactive, the microprocessor 310 reads the memory B data output on the data bus 126 at the falling edge of the clock TW1 and simultaneously executes the next instruction. , Outputs the address signal specified by the instruction. Here, the next address signal 135 is the memory A30.
It is assumed that the same memory page address a for accessing 1 and the lower address 5 are used.

Here, it is assumed that the memory B 108 normally requires a time of about 3 clocks from the input of the address signal to the output of the data on the data bus 126. (4) Access 4 The microprocessor 101 outputs the same memory page address a to access the memory A102. At this time, since the page address a is latched in the page address latch 305, the comparator 104 activates the same page signal 123.

On the other hand, the decoder 106 uses the page address a
Of the chip select signal 12
Activate 4

Since the same page signal 123 is active when the address strobe signal 127 changes to active, the state latch circuit 111 latches the active signal and activates the high speed access signal 129. When the high speed access signal 129 becomes active, the DRAM control circuit 303 causes the CAS signal 30
Since 8 is activated, the column decoder incorporated in the memory 301A decodes the lower address 5 on the memory A address 302 and outputs the designated data onto the data bus 126.

Further, since the high-speed access signal 129 becomes active, the wait signal A132 output from the wait control circuit 105 to the microprocessor 310 becomes inactive, and the microprocessor 310 drops on the data bus 126 at the falling edge of the clock T2. Capture the data of.

Although the normal access time of the memory A301 is about 4 clocks, the memory A30
In 1, all the memory cells corresponding to the page address a and the bit line group are already connected, so that the time for newly connecting all the memory cells of the page address and the bit line group can be omitted. Therefore, the access time can be shortened to about 2 clocks because it is sufficient to consider only the time for selecting the bit line group by changing the lower address 121.

As described above, when the interface circuit of this embodiment is used, even if different memories are accessed, if the same page address of the memory is continuously accessed when attention is paid to the same memory, the interface circuit is continuously accessed. Since high-speed access is possible, the access time can be shortened as compared with the conventional example, and the number of bits of the address bus can be reduced as compared with the conventional example, so that the circuit configuration can be facilitated.

FIG. 5 shows a performance comparison between the conventional interface circuit and the interface circuit of the present invention.
As the present invention, the same result can be obtained by using either the first embodiment or the second embodiment.

In the conventional interface circuit, high speed access is possible when the same page of the same memory is continuously accessed, for example, when the page a of the memory A is continuously accessed. When accessed, for example, even after accessing the memory B once and then accessing the page a of the memory A again, the high speed access is not immediately performed.

However, in the present invention, when attention is paid to the same memory, if the page addresses are successively accessed, for example, page a of memory A is accessed, then memory B is accessed once, and then the page of memory A is accessed again. a
Even if the memory is accessed, if the memory A is focused on, it means that page a is continuously accessed, and in this case, the memory A continues to be accessed at high speed.

Therefore, it is possible to access at a higher speed than before.

[0100]

As described above, according to the present invention, in a microprocessor system having a plurality of memories,
Focusing on a certain memory, if the same page of the memory is continuously accessed, the access becomes a high-speed access.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a timing diagram of the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is a timing diagram of the second embodiment of the present invention.

FIG. 5 is a diagram showing a performance comparison between the present invention and a conventional example.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is a timing chart of a conventional example.

[Explanation of symbols]

 101 Microprocessor 102 Memory A (ROM) 103 Page Address Latch 104 Comparator 105 Wait Control Circuit 106 Decoder 107 OR Circuit 108 Memory B 109 Memory B Output Control Circuit 110 AND Circuit 111 State Latch Circuit 112 AND Circuit 120 Page Address 121 Lower address 122 Page address latch output 123 Same page signal 124 Chip select signal 125 Output enable signal A 126 Data bus 127 Address strobe signal 128 Output enable signal B 129 High speed access signal 130 Low speed access signal 131 Wait signal 132 Wait signal A 133 Wait signal B 134 Clock signal 135 Address signal 201 Page address latch 202 Page address latch output 203 NOT circuit 204 AND circuit 205 Address strobe enable signal 301 Memory A (DRAM) 302 Memory A address 303 DRAM control circuit 304 Address select signal 305 Page address latch 306 Page address latch output 307 RAS signal 308 CAS signal 309 READ / WRITE signal 310 Microprocessor

Claims (5)

[Claims] 1. In a memory interface circuit having latch means for latching an address output from a microprocessor and controlling access to a memory by the output of the latch means, the access address output from the microprocessor is the latch means. A memory interface circuit, wherein the latch means is provided with a control means for latching the access address only when the address is different from the output of FIG. 2. A decoder, a comparator, a memory, and a latch, wherein the decoder decodes the first page address supplied, and when the page address is an address corresponding to the memory, The output signal is set to the active level, the comparator compares the first page address and the second page address latched by the latch circuit, and when both are the same, sets the output signal to the active level, The memory interface circuit, wherein the latch circuit latches the first page address when an output signal of the decoder is at an active level and an output signal of the comparator is at an inactive level. 3. A state latch circuit and an address control circuit are further provided, the state latch circuit latches an output signal of the comparator, and the address control circuit responds to an output of the state latch circuit. 3. The memory interface circuit according to claim 2, wherein access to the memory interface is changed. 4. A memory interface circuit for a dynamic memory having page mode access, wherein a latch circuit for latching a page address to the dynamic memory and an address supplied for access are latched in the latch circuit. Means for rewriting the contents of the latch circuit to the supplied address only when different from the existing address, and means for executing page mode access to the dynamic memory using the address latched in the latch circuit and the in-page address. A memory interface circuit comprising: 5. A microprocessor having a wait function for extending the data access time of a bus cycle, a page address latch for holding a page address which is an upper address of an address output by the microprocessor, and an output of the microprocessor. Page address comparator for comparing the page address to be output with the output of the page address latch, a latch circuit for holding the information compared by the page address comparator, and a wait for the microprocessor bus cycle by the state latch circuit. Control circuit, a memory with a high-speed page function that enables high-speed access when only the lower address is changed while the page address is fixed, and the micro-program for accessing the memory with the high-speed page function. In a microprocessor system having an address decoder for decoding an address output by a processor, the state latch circuit is provided for the memory with high-speed page function, the microprocessor accesses the memory with high-speed page function, and The page address latch is updated only when the page address is different from when the memory with the high-speed page function is accessed,
A microprocessor system wherein the same page address is always supplied to the memory with a high-speed page function when the microprocessor accesses a memory other than the memory with a high-speed page function.