JPH0778069A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To delay and output data on the basis of a previously set delay value and to reduce the circuit by specifying the writing start and reading start of the data by one register. CONSTITUTION:This circuit is equipped with at least an address arithmetic means 11 which calculates a read address AddR and a write address AddR and a storage means 12 which stores data Data on the basis of the write address Addw and outputs the data Data on the basis of the read address AddR, and the address arithmetic means 11 is provided with a delay write/read register 11A. The delay write/read register 11A holds the read address AddR and write address Addw alternately on the basis of an external control signal RST and an internal control signal SC. Then when the write address Addw is re-initialized on the basis of the internal control signal SC generated when the previously set delay value DE is reached or when the delay value is varied.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Conventional Technology (FIG. 9) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Operation Embodiment (1) Description of Digital Delay Circuit (FIG. 2 to 6) (2) Description of the application circuit (FIGS. 7 and 8)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital delay circuit, and more particularly to an improvement of a circuit which delays and outputs data based on a preset delay value. 2. Description of the Related Art In recent years, with the increase in functionality and performance of information processing apparatuses, circuits for generating special effect sounds such as echo effects and synthetic sounds have been incorporated into voice processing apparatuses such as computer game machines and digital synthesizers, and digital delays have been incorporated therein. Circuit is used.

According to this, a delay write register for designating a write initial value and a delay read register for designating a read initial value are individually provided in a digital delay circuit, and both registers and other circuits are provided in an internal bus. It is connected to the. Therefore, both registers occupy a large number of memory address operation units and increase the control logic amount of them, which complicates internal bus control.

Therefore, it is possible to specify the start of data writing and the start of reading by one register, delay output of data based on a preset delay value, and reduce the size of the circuit. A circuit is desired.

[0005]

2. Description of the Related Art FIG. 9 is an explanatory diagram according to a conventional example. Figure 9
FIG. 9A is a configuration diagram of a digital delay circuit according to a conventional example, and FIG. 9B is an operation explanatory diagram thereof. For example, a digital delay circuit that delays and outputs data based on a preset delay value includes a memory address operation unit 1, a memory interface unit 2 and a delay memory 3 in FIG. 9A. The memory address calculation unit 1 is composed of a delay setting register 1A, a "+1" generator 1C, a comparison circuit 1B connected to the internal bus 1G, a delay write register 1D, a delay read register 1E and an adder 1F.

Next, the function of the delay circuit will be described.
It For example, in FIG. 9B, the delay value is DE = 5.
The storage capacity of the delay memory 3 is set to M = 10, and the read address is set.
Su Add _WIs displayed when "x" is displayed, the
Therefore, DE = 5 is set in the delay setting register 1A,
Write register 1D and delayed read register 1E
Write initial value = "0" and read initial value = "0" respectively
Is set. The setting content at this time is the write initial value = read
This is the initial value.

As a result, the data D0 is assigned to the address Add _W = “0” of the delay memory 3 designated by the initial write value.
But writing rare, "+ 1" generator 1C and the adder 1F and the write address Add _W is sequentially incremented. During this period, the output of the read address Add _R is limited. Further, the incremented write address Add _R = 0 to 5 and the delay value = 5 are sequentially compared by the comparison circuit 1B, and when they match, the delay read register 1
The initial value output of E becomes valid, the data D0 is read from the specified read address Add _R , and the “+1” generator 1
The write address Add _W and the read address Add _R are alternately incremented by C and the adder 1F, the data D1 to D4 ... Are read sequentially, and digital delay data can be output.

[0008]

By the way, according to the conventional example, the delay write register 1D for designating the write initial value is used.
And a delay read register 1E for designating a read initial value are separately provided, and both registers 1D and 1E, an adder 1F and a comparison circuit 1B are connected to an internal bus 1G.

Therefore, two of the delay write register 1D and the delay read register 1E occupy a large part of the memory address operation unit 1, or control logics such as a write initial value and a read initial value individually set in both registers 1D and 1E. This leads to an increase in quantity. In addition, in order to avoid data collision (traffic state) of the internal bus 1G, the registers 1D and 1E and the adder 1F are added.
Also, a program for controlling the input / output of the comparison circuit 1B is required, which causes the control to be complicated.

As a result, the circuit scale of the memory address operation unit 1 becomes large, which hinders the reduction of the digital delay circuit and increases the control load on the processor that controls the circuit. is there. The present invention has been made in view of the problems of the conventional example, and specifies writing start and reading start of data by one register, and delays and outputs data based on a preset delay value. It is also an object of the present invention to provide a digital delay circuit that can reduce the size of the circuit.

[0011]

FIG. 1 shows a principle diagram of a digital delay circuit according to the present invention. The digital delay circuit of the present invention, as shown in FIG.
An address calculating means 11 for calculating a read address Add _R or a write address Add _W , and the write address Add.
Storage means 1 for storing data Data based on _W and outputting data Data based on the read address Add _R
; And a 2, the address calculation unit 11 delays the write / read register 11A is provided, the read address the delayed write / read register 11A is based on an external control signal RST and the internal control signal SC Add _R or write address Add It is characterized by holding _W alternately.

In the digital delay circuit of the present invention, the write address Add _W is reset based on the internal control signal SC generated when the write address reaches the preset delay value DE or when the delay value is changed. It is characterized by being initialized. Further, the digital delay circuit of the present invention, the read address Add _R, characterized in that the preset delay value DE and the write address Add _W is initially valued if they match.

Further, in the digital delay circuit of the present invention,
The storage means 12 stores the delay value DE and the write address.
Su Add_WRead enable signal output after and match
It is characterized by outputting data Data based on Read.
To do. In the digital delay circuit of the present invention,
When the delay value DE is changed, the read address Add_ROutput
Is stopped, new delay setting value DE and write address Add _W
Read address Add after_RIs output
It is characterized by

In the digital delay circuit of the present invention, the read address Add _{R is used} when the delay value DE is changed.
The read address Ad _R is initialized after the new delay set value DE matches the write address Ad _w, and the above-mentioned object is achieved.

[0015]

[Operation] According to the digital delay circuit of the present invention, as shown in FIG.
And a delay write / read register 11A is provided in the arithmetic means 11. For example, the delay value DE is set in advance in the calculation means 11, the delay write / read register 11A is initialized by the external control signal RST, and the write address Add _W is calculated by the address calculation means 11. However, the read address Add _R is not computed, based on the write address Add _W, sequentially, data Dat
a is stored in the storage means 12.

Here, when the preset delay value DE and the write address Add _W match, the read address Add _R is initialized for the first time. Further, the write address Add _W is reinitialized based on the internal control signal SC generated at this time. After that, delayed write / read register
Read address Add _R or write address A depending on 11A
dd _W is held alternately.

Therefore, the delay value DE and the write address A
After the coincidence with dd _W , the data D is sequentially read based on the read enable signal Read output from the calculation means 11.
The ata is output from the storage unit 12, and the digital delay data can be output. If the delay value DE is changed during output of the digital delay data, for example,
The output of the read address Add _R is stopped, and the read address Add _R is output after the new delay setting value DE and the write address Add _W match, and the read address Add _R is also output.
The output of _R corresponds to the old delay setting value and the new delay setting value DE
The read address Add _R is initialized after the read address Add _R matches the write address Add _W.

Therefore, the write address Add _W is re-initialized based on the internal control signal SC generated when the delay value DE is changed, and thereafter, the delay write / read register 11A.
Thus, the digital delay data can be output based on the read address Add _R or the write address Add _W held alternately. This makes it possible to specify writing start and reading start of the data Data with the single delayed write / read register 11A, and to reduce the size of the circuit. As a result, the circuit scale of the address calculation means 11 can be reduced, and the digital delay circuit can be made compact. In addition, it greatly contributes to the reduction of the control load on the circuit and the simplification of its operation.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 7 are diagrams for explaining the digital delay circuit according to the embodiment of the present invention. (1) Description of Digital Delay Circuit FIG. 2 is a block diagram of a digital delay circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram of its delay R / W register. 4 to 6 are operation explanatory diagrams (1 to 3) of the digital delay circuit, respectively.

For example, the digital delay circuit which delays and outputs the data based on a preset delay value is composed of a memory address operation unit 21, a delay memory 22 and a memory interface unit 23 in FIG. That is,
Memory address calculation unit 21 is an embodiment of the address computation unit 11 is a circuit for calculating a read address Add _R or a write address Add _W. For example, the memory address calculation unit 21 includes a delay R / W register 21A and a comparison circuit 21.
B, "+1" generator 21C, delay setting register 21D and adder 21E.

The delay R / W register 21A is an example of the delay write / read register 11A, and includes a comparison circuit 21B and an adder.
21E and the memory interface unit 23.
The register 21A holds the read address Add _R or a write address Add _W based on an external control signal (hereinafter referred to as RST signal) and an internal control signal (hereinafter referred to as SC signal) alternately.

For example, an n-bit read address Add _R
Or write address Add _W (hereinafter simply address R / W0
~ R / Wn) which holds the delay R / W register 21
As shown in FIG. 3, A is composed of n flip-flop circuits FFn, n logic gate circuits G0 to Gn, and one two-input NOR circuit. In FIG. 3, two-input NO
The R circuit outputs the NOR logic of the RST signal and the SC signal, and the n flip-flop circuits FFn address R / W0 to R0 based on the clock signal CK and the NOR logic output.
It holds R / Wn and outputs it as output values Q0 to Qn. The delay R / W register 21A is set to the initial value = 0 via the RST signal at the time of memory access.

The comparison circuit 21B compares the write address Add _W output from the delay R / W register 21A with the delay setting register 2
The delay value DE output from 1D is compared, and the SC signal resulting from the comparison is output to the delay R / W register 21A. The comparison circuit 21B outputs a read enable signal (hereinafter referred to as a Read signal) to the memory interface unit 23 when the delay value DE and the write address Add _W match. After that, the Lead is continuously read until the delay value is reset.
The signal becomes valid.

The "+1" generator 21C outputs the clock signal CK.
Based on this, "+1" is generated and the delay setting register 21D
Hold the extended value DE. The adder 21E is the read address
ADD _ROr write address ADD_WAdd "+1" to
Increment it. The delay memory 22 is a storage means
12 is an example of the write address Add._WBased on
The data Data is stored by the read address Add._RBased on
It is a memory that outputs data Data. For example, late
The total memory 22 is a RAM (a memory that can be written / read at any time).
Memory) is used, and the memory 22 is written with the delay value DE.
Address Add_WRead that is output after and match
The data Data is output based on the signal.

The memory interface unit 23 is a circuit for connecting the memory address operation unit 21 and the delay memory 22, and has a read address Add _R and a write address A.
It controls the output of dd _W and Lead signals. As a result, when the preset delay value DE is reached or when the delay value is changed, the write address Add is added based on the SC signal generated.
_W is reinitialized and the preset delay value DE
When the read address Add _R coincides with the write address Add _W , the read address Add _R is initialized.

Next, the operation of the digital delay circuit according to the embodiment of the present invention will be described. FIG. 4 is an explanatory diagram of the delay operation (without changing the delay value) of the digital delay circuit according to the embodiment of the present invention, and FIGS. 5 and 6 are explanatory diagrams of the delay operation (with the change of the delay value). Shown respectively. Here, as a condition of the delay operation of the digital delay circuit, for example, the delay value DE = 5, and M = 10 the storage capacity of the delay memory 22, the non-output position of the read address Add _W to display the "×" The case where the delay value DE = “no change” will be described. In FIG. 4, the delay value DE = 5 is set in advance in the delay setting register 21D, and
The delay R / W register 21A is initialized by the RST signal, and the write initial value = “0” is set therein.

[+] Of the memory address operation unit 21
Write address A by 1 "generator 21C and adder 21E
dd _W is incremented. However, in FIG.
Non output position "×" in the read addresses Add _R is not computed, based on the write address Add _W = 0 to 4 ...,
The data D0 to D4 ... Are sequentially stored in the delay memory 22.

Here, a preset delay value DE = 0 to 0
.. and the write address Add _W = 5 are compared by the comparison circuit 21B, and the SC signal as the comparison result is delayed R / W.
It is output to the register 21A. As a result, the delay value DE =
5 and the write address Add _W = 5 are detected as coincident,
For the first time, the read address Add _R is initialized. Also,
Rea from the comparison circuit 21B to the memory interface unit 23
The d signal is output, and the write address Add _W = 0 is reinitialized based on the SC signal generated at this time. After that, the address R / W is incremented by the adder 21E and the like, and the read address Add _R = 0, 1, 2, ... Or the write address Add _W = 0, by the delay R / W register 21A.
1, 2, ... Are alternately held, and data D0 to D4 are sequentially output based on the Read signal output from the comparison circuit 21B to the delay memory 22 via the memory interface unit 23.
... is output.

Next, the operation when the delay setting is changed on the way will be described. For example, a case where the old delay setting value is smaller than the new delay setting value will be described. In FIG. 5A, the old delay setting value is DE = 5 and the new delay setting value is DE =
7, memory capacity M = 10, delay R / W register 21
A is write address Add _W = 9, read address Add _R
If there is a change in the delay value setting after holding = 4, the value Add _R that continues to the read address Ad _d = 4
= 5, 6, 7, 8, 9, 9, 0 is output as it is.

Further, the write address Add_WChange the delay value
Since it is initialized at times, Add _W= 0 to 6, 7 and a
Is incremented, and the new delay setting value is set to DE = 7.
Read address Add_RIs initialized
It After that, the address R / W becomes ink by the adder 21E.
Are rewritten and written by the delay R / W register 21A.
Dress dd_W= 8,9,0 ... and read address Add_R=
1, 2, 3 ... are held alternately and the delay value setting is changed.
Read signal output from the comparison circuit 21B.
The data Data is sequentially output from the delay memory 22 according to
Is output.

Further, a case where the old delay setting value is larger than the new delay setting value will be described. In FIG. 5B, for example, the old delay setting value is DE = 7 and the new delay setting value is DE =
5, memory capacity M = 10, delay R / W register 21
A is write address Add _W = 2, read address Add _R
If the setting of the delay value is changed after holding = 5, the value that continues to the read address Add _R = 5 Add _R
= 6, 7, 8, 9, 0 are output as they are.

Further, since the write address Add _W is initialized when the delay value is changed, the write address Add _W is incremented to 0 to 4, 5 and when the new delay set value matches DE = 5. At the same time, the read address Add _R is initialized. After that, the address R is added by the adder 21E or the like.
/ W is incremented, the write address Add _W = 6,7,8 ... and the read address Add _R = 1,2,3 ... are alternately held by the delay R / W register 21A, and the delay value is changed. After that, the data Data is sequentially output from the delay memory 22 based on the Read signal output from the comparison circuit 21B.

It should be noted, in a case where it is changed during the delay setting, and stops the output of the read address Add _R when delay values change, the operation to output the data after a lapse of the new delay value. In FIG. 6A, the old delay set value is DE = 5, the new delay set value is DE = 7, the memory capacity is M = 10, and the delay R / W register 21A has a write address Add _W = 9 and a read address Add. If the setting of the delay value is changed after holding _R = 4, the read address Add _R = 4
The output continues to stop.

Further, the write address Add_WChange the delay value
Since it is initialized at times, Add _W= 0 to 6, 7 and a
Is incremented, and the new delay setting value is set to DE = 7.
Read address Add_RIs initialized
It After that, the address R / W becomes ink by the adder 21E.
Are rewritten and written by the delay R / W register 21A.
Dress dd_W= 8,9,0 ... and read address Add_R=
1, 2, 3 ... are held alternately and the delay value setting is changed.
Read signal output from the comparison circuit 21B.
The data Data is sequentially output from the delay memory 22 according to
Is output.

Further, the operation of outputting the data of the read address Add _R corresponding to the old delay setting value when the delay value is changed and the delay value is changed will be described. In FIG. 6B, the old delay setting value is DE = 5.
The new delay setting value is DE = 7, the memory capacity is M = 10,
The delay R / W register 21A has a write address Add _W = 2.
If the delay value setting is changed after holding the read address Add _R = 7, the read address Add _R =
The value continuing to 7 is made to correspond to the old delay setting value DE = 5, and the value Add _R = 5, 6, 7, 8, 9 is output.

Further, since the write address Add _W is initialized when the delay value is changed, the write address Add _W is incremented from 0 to 6 and 7, and when the new delay set value matches DE = 7. At the same time, the read address Add _R is initialized. After that, the address R is added by the adder 21E or the like.
/ W is incremented, the write address Add _W = 8,9,0 ... and the read address Add _R = 1,2,3 ... are alternately held by the delay R / W register 21A, and the delay value is changed. After that, the data Data is sequentially output from the delay memory 22 based on the Read signal output from the comparison circuit 21B.

Thus, according to the digital delay circuit of the embodiment of the present invention, as shown in FIGS.
A memory address operation unit 21, a delay memory 22, and a memory interface unit 23 are provided, and the operation unit 21 is provided with a delay R / W register 21A. Therefore, the delay R
Write address Add held by / W register 21A
_{After the W} and the delay value DE set in the delay setting register 21D match, the Read output from the calculation unit 21 is performed.
Based on the signal, the data Data are sequentially transferred to the delay memory 22.
Can be read and digital delay data can be output to the outside.

Even when the delay value DE is changed during the output of the digital delay data, the write address Add _W is re-initialized based on the internal control signal SC generated at the time of the change, and thereafter the delay value DE is changed. based on the read address Add _R or a write address Add _W held alternately by R / W register 21A, it is possible to output a digital delay data.

As a result, it is possible to specify the start of writing and the start of reading of the data Data with the single delay R / W register 21A. As a result, the two registers as in the conventional example, that is, the delay write register and the delay read register do not occupy the memory address operation unit. Therefore, the circuit scale of the memory address calculation unit 21 can be reduced, and the digital delay circuit can be made compact.

Further, it is not necessary to individually set the write initial value, the read initial value, etc. in the register as in the conventional example, and it is possible to reduce the control logic amount thereof.
Further, since the internal bus as in the conventional example is unnecessary, bus control for avoiding data collision (traffic state) is not necessary. From this, it becomes possible to reduce the control load of the processor or the like that controls the circuit, and to simplify the operation and use of the circuit.

(2) Description of Application Circuit FIG. 7 is a block diagram of a digital echo output circuit to which the digital delay circuit according to the embodiment of the present invention is applied.
Shows respective operation waveform diagrams. For example, the digital echo output circuit which outputs the echo data DOUT based on the delay value DE is composed of a memory address operation unit 21, a delay memory 22, a memory interface unit 23 and an adder 25 in FIG.

That is, the memory address operation unit 21, the delay memory 22 and the memory interface unit 23 are formed of the digital delay circuit according to the embodiment of the present invention, and the echo data DOUT output from the adder 25 is delayed by the delay value DE.
And outputs the delayed data Data to the adder 25. The adder 25 adds the input data DIN and the delay data Data at the time, and outputs the echo data DOU.
This is a circuit that outputs T. The memory address calculation unit 21 and the delay memory 2 that constitute the digital delay circuit
2, the delay R / W register 21A, the comparison circuit 21B, and the “+” that compose the memory interface unit 23 and the calculation unit 21
1 "generator 21C, delay setting register 21D and adder 21E
Since the above has already been described, the description thereof will be omitted.

Next, the operation of the echo output circuit will be described with reference to FIG. For example, in FIG. 8, it is assumed that a sine wave is input as the input data DIN and the delay value DE is set in the memory address operation unit 21 in advance. The delay value is 1/4 of the sine wave period. First, RS
The delay R / W register 21A is initialized by the T signal,
The “+1” generator 21C and the adder 21E increment the write address Add _{W associated} with the input data DIN. However, the read address Add _R is not output, and the input data D is sequentially input based on the write address Add _W.
IN is stored in the delay memory 22.

Here, when the preset delay value DE and the write address Add _W match, the read address Add _R is initialized for the first time. Further, the write address Add _W is reinitialized based on the SC signal generated at this time. After that, the read address Add _R or the write address Add _W is alternately held by the delay R / W register 21A.

Therefore, the write address Add _W related to the input data DIN held by the delay R / W register 21A.
And the delay value DE set in the delay setting register 21D match, the delay data Data is sequentially output based on the Read signal output from the calculation unit 21.
2 can be read. As a result, as shown in FIG. 8, the echo data DOUT at the time is delayed based on the delay value DE, and the delayed data Data is added to the input data DIN at the same time to output the echo data DOUT.

As described above, according to the digital echo output circuit of the embodiment of the present invention, as shown in FIG. 7, the adder 25 is provided in the digital delay circuit of the present invention. For this reason, the output of the adder 25 is delayed based on the delay value DE, and the delayed data Data is added to the input data DIN at the same time to obtain the echo data DOUT.
Can be output, and an acoustic special effect such as an echo effect can be obtained.

As a result, it is possible to easily generate the special effect sound in various audio equipment such as a computer game machine and a digital synthesizer. The adder 2
By providing an envelope control means or the like in place of 5, and performing envelope control of the input data DIN and the delay data Data, it is possible to obtain another acoustic special effect without adding or subtracting multiplication processing. .

[0048]

As described above, according to the digital delay circuit of the present invention, it is provided with the address calculation means and the storage means, and the calculation means is provided with the delay write / read register. Therefore, when the preset delay value and the write address of the delayed write / read register match, the read address is initialized for the first time, and the write address is reinitialized based on the internal control signal.
After that, it becomes possible to sequentially output the data from the storage means based on the read permission signal output from the calculation means.

Also, when the delay value is changed during the output of the digital delay data, the write address is reinitialized based on the internal control signal when the delay value is changed, and thereafter,
It is possible to sequentially output data from the storage means based on the read address or write address of the delayed write / read register. As a result, it becomes possible to specify the start of data writing and the start of reading of data with one delay write / read register, and to configure a compact digital delay circuit. In addition, it greatly contributes to the reduction of the control load on the circuit and the simplification of its operability.

[Brief description of drawings]

FIG. 1 is a principle diagram of a digital delay circuit according to the present invention.

FIG. 2 is a configuration diagram of a digital delay circuit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a delay R / W register according to an embodiment of the present invention.

FIG. 4 is an operation explanatory diagram (1) of the digital delay circuit according to the embodiment of the present invention.

FIG. 5 is an operation explanatory diagram (2) of the digital delay circuit according to the embodiment of the present invention.

FIG. 6 is an operation explanatory view (No. 3) of the digital delay circuit according to the embodiment of the present invention.

FIG. 7 is a configuration diagram of a digital echo output circuit to which the digital delay circuit according to the embodiment of the present invention is applied.

FIG. 8 is an operation waveform diagram of the digital echo output circuit according to the embodiment of the present invention.

FIG. 9 is a configuration diagram of a digital delay circuit according to a conventional example and an operation explanatory diagram thereof.

[Explanation of symbols]

11 ... Address calculation means, 12 ... storage means, 11A ... delayed write / read register, Add _W ... write address, Add _R ... read address, RST ... external control signal, SC ... internal control signal, DE ... delay value, old delay Set value, new delay set value, Read ... Read enable signal, Data ... Data.

Claims (6)

[Claims] 1. At least a read address (Add _R )
Or write address as calculating means for calculating a (Add _W) (11), the write address to store the data (Data) based on (Add _W), the read address based on (Add _R) data (Data) Storage means (12) for outputting the address calculation means (1)
1) is provided with a delayed write / read register (11A), and the delayed write / read register (11A) is read address (Add _R ) or write address based on an external control signal (RST) and an internal control signal (SC). (Add _W )
A digital delay circuit characterized by holding alternately. 2. The digital delay circuit according to claim 1, wherein an internal control occurs when the write address (Add _W ) reaches a preset delay value (DE) or when the delay value is changed. A digital delay circuit characterized by being re-initialized based on a signal (SC). 3. The digital delay circuit according to claim 1, wherein the read address (Add _R ) is initialized when a preset delay value (DE) and a write address (Add _W ) match. A digital delay circuit characterized in that 4. The digital delay circuit according to claim 1, wherein the storage means (12) outputs a read enable signal (Read) after the delay value (DE) and the write address (Add _W ) match. Data based on (Data)
A digital delay circuit that outputs 5. The digital delay circuit according to claim 1, wherein the output of the read address (Add _R ) is stopped when the delay value (DE) is changed, and the new delay set value (DE) and write address (Add _W ) are added. A digital delay circuit characterized in that a read address (Add _R ) is output after a match between and. 6. The digital delay circuit according to claim 1, wherein when the delay value (DE) is changed, the output of the read address (Add _R ) corresponds to the old delay set value, and the new delay set value (DE) and the write are written. A digital delay circuit characterized in that a read address (Add _R ) is initialized after the address (Add _W ) matches.