JPH0775270B2 - Bare chip mounting structure - Google Patents
Bare chip mounting structureInfo
- Publication number
- JPH0775270B2 JPH0775270B2 JP1101274A JP10127489A JPH0775270B2 JP H0775270 B2 JPH0775270 B2 JP H0775270B2 JP 1101274 A JP1101274 A JP 1101274A JP 10127489 A JP10127489 A JP 10127489A JP H0775270 B2 JPH0775270 B2 JP H0775270B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring board
- printed wiring
- bare chip
- bare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は二以上のベアチップを相互に接続させてプリン
ト配線板上に実装するベアチップの実装構造に関する。Description: TECHNICAL FIELD The present invention relates to a bare chip mounting structure in which two or more bare chips are connected to each other and mounted on a printed wiring board.
＜従来の技術＞ OA機器用のイメージセンサ，プリントヘッド等の高機能
回路においては、高密度，薄型実装の利点及び通信回路
においては、高周波特性の利点に夫々着目してベアチッ
プ実装が採用されている。<Prior Art> In high-performance circuits such as image sensors and print heads for OA equipment, bare chip mounting has been adopted by paying attention to the advantages of high-density and thin mounting, and in communication circuits, high-frequency characteristics. There is.
通常ベアチップ実装としては、プリント配線板上にベア
チップをフェースアップ状に実装し、これ等ベアチップ
間をAu,Al線にてワイヤボンディングを行う。ワイヤボ
ンディングはAu,Al線とプリント配線板を加熱するとと
もに、超音波による振動を与え、プリント配線板のパッ
ド部とベアチップの電極面に上記Au,Al線を熱圧着して
接続させる。Usually, as bare chip mounting, bare chips are mounted face-up on a printed wiring board, and wire bonding is performed between these bare chips with Au and Al wires. In wire bonding, the Au and Al wires and the printed wiring board are heated, and at the same time, vibration due to ultrasonic waves is applied, and the Au and Al wires are thermocompression bonded to the pad portion of the printed wiring board and the electrode surface of the bare chip to connect them.
ワイヤボンディングによる具体的接続方法としては、第
５図に示す様に、ベアチップ例えばSiチップ7,LEDチッ
プ８を夫々プリント配線板６のパッド部61にAgペースト
62を介して実装する。そしてSiチップ７の電極面71とプ
リント配線板６のパッド部61間にAu,Al線から成る信号
線91を上記ワイヤボンディングによって接続する。同様
にSiチップ７の他の電極面71と他のパッド部61とを他の
信号線92によって接続する。As a concrete connection method by wire bonding, as shown in FIG. 5, bare chips such as Si chips 7 and LED chips 8 are respectively attached to the pad portions 61 of the printed wiring board 6 by Ag paste.
Implemented via 62. Then, the signal line 91 composed of Au and Al wires is connected between the electrode surface 71 of the Si chip 7 and the pad portion 61 of the printed wiring board 6 by the above wire bonding. Similarly, the other electrode surface 71 of the Si chip 7 and the other pad portion 61 are connected by another signal line 92.
一方LEDチップ８においても、その電極面81とパッド部6
1とをワイヤボンディングにより信号線93にて接続す
る。On the other hand, also in the LED chip 8, the electrode surface 81 and the pad portion 6
1 and 1 are connected by a signal wire 93 by wire bonding.
上記の実装構造においては、プリント配線板６からの信
号が信号線91を介してSiチップ７に入力され、又Siチッ
プ７からの信号は、信号線92,プリント配線板６部のパ
ッド部61を経て、信号線93からLEDチップ８に入力され
る。In the above mounting structure, the signal from the printed wiring board 6 is input to the Si chip 7 through the signal line 91, and the signal from the Si chip 7 is transmitted through the signal line 92 and the pad portion 61 of the printed wiring board 6 portion. After that, the signal is input to the LED chip 8 from the signal line 93.
又他のフェースアップ状のベアチップをワイヤボンディ
ングにて接続する実装構造としては、第６図に示すもの
がある。この実装構造では、プリント配線板６のパッド
部61上にAgペースト62を介して各Siチップ７及びLEDチ
ップ８が実装され、更に上記Siチップ７の電極面71とパ
ッド部61とを信号線94によって接続し、更にSiチップ７
の電極面71とLEDチップ８の電極面81とをワイヤボンデ
ィングによる信号線95により接続する。すなわちこの実
装構造においては、フェースアップ状に有る二つのベア
チップすなわちSiチップ７とLEDチップ８を直接信号線9
5によって接続させている。As another mounting structure for connecting another face-up bare chip by wire bonding, there is a mounting structure shown in FIG. In this mounting structure, each Si chip 7 and LED chip 8 are mounted on the pad portion 61 of the printed wiring board 6 via the Ag paste 62, and the electrode surface 71 of the Si chip 7 and the pad portion 61 are connected to the signal line. Connected by 94, and Si chip 7
The electrode surface 71 of the LED chip 8 and the electrode surface 81 of the LED chip 8 are connected by a signal line 95 by wire bonding. That is, in this mounting structure, two face-up bare chips, that is, the Si chip 7 and the LED chip 8 are directly connected to the signal line 9
Connected by 5.
上述したワイヤボンディングによるベアチップの実装構
造は、何れもベアチップ自体をフェースアップ状で搭載
し、かつプリント配線板及びベアチップ相互の接続は信
号線を介して行われたものである。In each of the bare chip mounting structures by wire bonding described above, the bare chip itself is mounted face-up, and the printed wiring board and the bare chip are connected to each other through signal lines.
＜発明が解決しようとする課題＞ しかしながら上記従来のワイヤボンディングによるベア
チップの実装構造は、以下に述べる課題を呈している。<Problems to be Solved by the Invention> However, the above-described conventional bare chip mounting structure by wire bonding presents the following problems.
その１つとしてプリント配線板とベアチップ及び各ベア
チップ相互は、全て信号線を１本毎熱圧着するものなの
で、ワイヤボンディング時の組立工数が増大し、所謂施
工手間がかかる。実例として第６図に示したベアチップ
相互を直接接続させる場合では、Siチップ,LEDチップ夫
々は１チップ当たり64個の電極数を有するものとし、こ
れをプリント配線板１上に夫々40個搭載すれば、このワ
イヤボンディング時の工数は0.6［Sec/ワイヤ］×（64
＋12）［ワイヤ／チップ］×40［チップ］＝30［分］と
なる。As one of them, the printed wiring board, the bare chip, and the respective bare chips are all thermocompression-bonded to each other, so that the number of assembling steps at the time of wire bonding is increased and so-called construction work is required. As an example, when the bare chips shown in FIG. 6 are directly connected to each other, each of the Si chip and the LED chip has 64 electrodes, and 40 of them are mounted on the printed wiring board 1. For example, the man-hour for wire bonding is 0.6 [Sec / wire] x (64
+12) [Wire / chip] x 40 [chips] = 30 [min].
又他の課題としては、ワイヤボンディングに使用される
Au,Al線は何れも通常φ25μｍ程度の極細線が用いられ
る。その為熱圧着した接続部の引張強度は、１ワイヤ当
たり５乃至10gf程度である。よってプリント配線板及び
ベアチップと信号線の接続部分に熱ストレスや外部応力
が働けば、断線等が容易に生じ、当該実装構造の機械
的，電気的信頼性を大きく低減させることになる。Another problem is that it is used for wire bonding.
For Au and Al wires, usually ultrafine wires with a diameter of about 25 μm are used. Therefore, the tensile strength of the thermocompression-bonded connecting portion is about 5 to 10 gf per wire. Therefore, if thermal stress or external stress acts on the connecting portion between the printed wiring board and the bare chip and the signal line, disconnection or the like easily occurs, and the mechanical and electrical reliability of the mounting structure is greatly reduced.
＜課題を解決するための手段＞ 本発明は、上記ワイヤボンディングによるベアチップ相
互の接続における課題を解決すべく成されたもので、二
以上のベアチップを相互に接続させてプリント配線板に
実装する実装構造において、前記ベアチップのうちの一
方がその上面に複数の電極を形成したフェースアップ型
であり、他方がその下面に複数の電極を形成したフェー
スダウン型であり、前記プリント配線板の上には、前記
一方のベアチップがその下面を該プリント配線板に接続
させた状態で設けられるとともに、該プリント配線板と
は異なる第二のプリント配線板がそのパターンを上に向
け、かつその上面を前記一方のベアチップの上面と略同
一高さとなるようにして設けられ、前記他方のベアチッ
プは、その下面の電極が前記一方のベアチップの上面の
電極に半田バンプを介して接続した状態で該一方のベア
チップ上に設けられるとともに、前記第二のプリント配
線板上にもこれのパターン上に半田バンプを介して接続
した状態で設けられたものである。<Means for Solving the Problems> The present invention has been made to solve the problems in connecting bare chips to each other by wire bonding as described above, and mounting by mounting two or more bare chips to each other on a printed wiring board. In the structure, one of the bare chips is a face-up type having a plurality of electrodes formed on its upper surface, and the other is a face-down type having a plurality of electrodes formed on its lower surface. , The one bare chip is provided with its lower surface connected to the printed wiring board, and a second printed wiring board different from the printed wiring board has its pattern facing upward, and its upper surface faces the one Of the bare chip, and the electrode of the lower surface of the other bare chip has the same height as that of the bare chip of the other bare chip. Is provided on the one bare chip in a state where it is connected to the electrode on the upper surface of the chip via a solder bump, and is also connected to the pattern on the second printed wiring board via a solder bump. It is provided.
＜作用＞ 一方のベアチップの上面と他方のベアチップの下面にそ
れぞれ形成された電極間が半田バンプを介して接続され
ているので、両電極間で半田バンプが溶融し、一体化す
るため両電極の接続強度が極めて大きいものとなる。<Operation> Since the electrodes formed on the upper surface of one bare chip and the lower surface of the other bare chip are connected via the solder bumps, the solder bumps are melted between both electrodes and integrated so that both electrodes are integrated. The connection strength will be extremely high.
また、他方のベアチップが、一方のベアチップにだけで
なく第二のプリント配線板にも半田バンプを介してその
パターンに接続した状態で設けられていることから、他
方のベアチップが第二のプリント配線板にも電気的に導
通可能となり、これにより引張強度が低くしたがって機
械的，電気的信頼性に劣るワイヤボンディングを用いる
ことなく、高強度であり機械的，電気的信頼性に優れた
半田バンプによって他方のベアチップが一方のベアチッ
プ、及び第二のプリント配線板に実装されたものとな
る。Further, since the other bare chip is provided not only on one bare chip but also on the second printed wiring board in a state of being connected to the pattern via solder bumps, the other bare chip is provided on the second printed wiring board. It is possible to conduct electricity to the board as well, and this makes it possible to use solder bumps with high strength and excellent mechanical and electrical reliability without the use of wire bonding, which has low tensile strength and thus has poor mechanical and electrical reliability. The other bare chip is mounted on the one bare chip and the second printed wiring board.
さらに、第二のプリント配線板が、その上面を一方のベ
アチップの上面と略同一高さとなるようにしてプリント
配線板上に設けられていることから、これら第二のプリ
ント配線板と一方のベアチップとに跨がるようにして設
けられる他方のベアチップは、傾くことなくプリント配
線板に対し略平行に実装されたものとなり、これにより
実装構造全体が安定したものとなる。Further, since the second printed wiring board is provided on the printed wiring board so that its upper surface is substantially flush with the upper surface of one bare chip, these second printed wiring board and one bare chip are provided. The other bare chip provided so as to straddle and is mounted substantially parallel to the printed wiring board without tilting, and thus the entire mounting structure is stable.
＜実施例＞ 次に図面に基づき本発明のベアチップの実装構造を詳細
に説明する。<Example> Next, a bare chip mounting structure of the present invention will be described in detail with reference to the drawings.
第１図は、ガラスエポキシ基板上にCuのベタパターン11
を設けたプリント配線板１に、LEDチップ3,Siチップ４
を夫々実装した状態を示す図である。LEDチップ３は、
その上面31に発光部32を有する。そして上面31に電極面
（電極）33を設けた所謂フェースアップ仕様のものであ
る。又他方のベアチップとしてのSiチップ４は、下面41
に電極面（電極）42を設けた所謂フェースダウン仕様の
ものである。上記LEDチップ３は、プリント配線板１に
対して高温半田13により接続されている。又プリント配
線板１上には外層板用のプリプレグ12を介して重ね基板
（第二のプリント配線板）２が設けられる。この重ね基
板２の上面にもCuのベタパターン（パターン）21が形成
される。Figure 1 shows a solid Cu pattern 11 on a glass epoxy substrate.
LED chip 3 and Si chip 4 on the printed wiring board 1
It is a figure which shows the state which each mounted. LED chip 3
The upper surface 31 has a light emitting portion 32. The upper surface 31 is provided with an electrode surface (electrode) 33, which is a so-called face-up type. The other bare chip, the Si chip 4, has a lower surface 41
This is a so-called face-down specification in which an electrode surface (electrode) 42 is provided on the. The LED chip 3 is connected to the printed wiring board 1 by high temperature solder 13. Further, a laminated substrate (second printed wiring board) 2 is provided on the printed wiring board 1 via a prepreg 12 for an outer layer board. A solid Cu pattern 21 is also formed on the upper surface of the laminated substrate 2.
通常LEDチップ３の上面31とベタパターン21は略同面に
なる様形成される。Usually, the upper surface 31 of the LED chip 3 and the solid pattern 21 are formed so as to be substantially on the same surface.
斯かるLEDチップ３の上面31と重ね基板２のベタパター
ン21上にSiチップ４を実装する。The Si chip 4 is mounted on the upper surface 31 of the LED chip 3 and the solid pattern 21 of the stacked substrate 2.
このSiチップ４はその下面41に電極面42が形成される。
よって重ね基板２のベタパターン21に設けたパッドと、
上記電極面42とが接続し、又LEDチップ３の上面31に設
けた電極面33と他の電極面42が夫々接続する。An electrode surface 42 is formed on the lower surface 41 of the Si chip 4.
Therefore, with the pad provided on the solid pattern 21 of the stacked substrate 2,
The electrode surface 42 is connected, and the electrode surface 33 provided on the upper surface 31 of the LED chip 3 and another electrode surface 42 are connected.
第２図は上記LEDチップ３の上面31に設けた電極面33を
示す図である。すなわち一方のベアチップであるLEDチ
ップ３において、その上面31に所定数の電極面33,33が
形成される。通常この電極面33はAl板にて形成される。
当該電極面33にはTi34及びPt35が積層される。そして最
上面のPt35を除き、上面31はパッシュベーション樹脂36
によって被覆される。電極面33のTi34とPt35は、後述す
る半田バンプの侵入を防ぎ、かつ接着性を向上させる層
構造を成している。FIG. 2 is a view showing the electrode surface 33 provided on the upper surface 31 of the LED chip 3. That is, a predetermined number of electrode surfaces 33, 33 are formed on the upper surface 31 of the LED chip 3 which is one bare chip. Usually, this electrode surface 33 is formed of an Al plate.
Ti34 and Pt35 are laminated on the electrode surface 33. And except for Pt35 on the top surface, the upper surface 31 is a pervasive resin 36.
Is covered by. The Ti 34 and Pt 35 on the electrode surface 33 form a layer structure that prevents intrusion of solder bumps, which will be described later, and improves adhesion.
第３図は、他方のベアチップ、すなわちSiチップ４の下
面41に形成された半田バンプ５を説明する概略図であ
る。下面41には、上記のLEDチップ３に設けた電極面33,
33と同ピッチＰで、同様のAl板等から成る電極面42,42
が設けられる。この電極面42,42上には、Alカレント膜4
3,Ti44,Pt45が層構造を成して形成される。そしてこのP
t45上には共晶半田から成る電極、すなわち半田バンプ
5,5が形成される。当該下面41は、この半田バンプ5,5を
除きパッシュベーション樹脂46によって被覆される。FIG. 3 is a schematic diagram for explaining the solder bumps 5 formed on the lower surface 41 of the other bare chip, that is, the Si chip 4. The lower surface 41 has an electrode surface 33 provided on the LED chip 3,
Electrode surfaces 42, 42 made of the same aluminum plate, etc. with the same pitch P as 33
Is provided. The Al current film 4 is formed on the electrode surfaces 42, 42.
3, Ti44 and Pt45 are formed in a layered structure. And this P
Electrodes made of eutectic solder on t45, that is, solder bumps
5,5 are formed. The lower surface 41 is covered with a passivation resin 46 except for the solder bumps 5, 5.
通常Pt45の表面にPb及びSnの電解メッキが施され、この
メッキ処理後にリフローソルダーリングによって上記半
田バンプ5,5が形成される。半田バンプ5,5は、LEDチッ
プ３の電極面33,33と同ピッチＰを成す。又Alカレント
膜43,Ti44,Pt45の三層は、前記同様Siチップ４内に半田
バンプ５が侵入するのを防止するとともに、半田バンプ
５との接着性を向上させるものである。Usually, Pb and Sn are electrolytically plated on the surface of Pt45, and the solder bumps 5, 5 are formed by reflow soldering after the plating process. The solder bumps 5, 5 have the same pitch P as the electrode surfaces 33, 33 of the LED chip 3. The three layers of the Al current film 43, Ti44 and Pt45 prevent the solder bumps 5 from entering the Si chip 4 and improve the adhesiveness to the solder bumps 5 as in the above.
斯かる構成のLEDチップ３とSiチップ４をプリント配線
板１上に実装する場合について説明する。A case where the LED chip 3 and the Si chip 4 having such a configuration are mounted on the printed wiring board 1 will be described.
先ず第１図に示す如く、一方のベアチップであるLEDチ
ップ３を搭載するベタパターン11の所定部分に、転写等
の手段によって高温半田13を供給する。次いで高温半田
13上にLEDチップ３を搭載し、リフローソルダーリング
によって当該高温半田13を加熱溶融し、半田付けを行
う。更に重ね基板２のベタパターン21上においては、Si
チップ４の半田バンプ５を搭載する部分に印刷等によっ
てフラックスを供給する。First, as shown in FIG. 1, high temperature solder 13 is supplied to a predetermined portion of a solid pattern 11 on which one bare chip LED chip 3 is mounted by means of transfer or the like. Then high temperature solder
The LED chip 3 is mounted on 13 and the high-temperature solder 13 is heated and melted by reflow soldering to perform soldering. Furthermore, on the solid pattern 21 of the laminated substrate 2, Si
Flux is supplied to the portion of the chip 4 where the solder bumps 5 are mounted by printing or the like.
そして第４図に示す如く、LEDチップ３の上面31に対し
てSiチップ４の下面41を対向させ、LEDチップ３の電極
面33上にSiチップ４の半田バンプ5,5を載置する。而る
後に、キュア炉を用いて上記フラックスを硬化させ、更
にリフローソルダーリングによりキュア炉又はホットプ
レート等の加熱手段で上記半田バンプ5,5を溶融させ
る。この半田バンプ５の溶融によってLEDチップ３とSi
チップ４との両電極面33,42は接続される。上記２回目
のリフローソルダーリングにおいてもLEDチップ３は高
温半田13によりプリント配線板１に実装されている為、
位置ズレ等を生じない。Then, as shown in FIG. 4, the lower surface 41 of the Si chip 4 is opposed to the upper surface 31 of the LED chip 3, and the solder bumps 5, 5 of the Si chip 4 are mounted on the electrode surface 33 of the LED chip 3. After that, the flux is hardened by using a cure oven, and the solder bumps 5, 5 are melted by reflow soldering by a heating means such as a cure oven or a hot plate. By melting the solder bumps 5, the LED chip 3 and the Si
Both electrode surfaces 33 and 42 of the chip 4 are connected. Even in the second reflow soldering, the LED chip 3 is mounted on the printed wiring board 1 by the high temperature solder 13,
No misalignment.
又上記２回目のリフローソルダーリング終了後にプリン
ト配線板１の洗浄工程が行われる。After the second reflow soldering is completed, the printed wiring board 1 is washed.
以上の如く本発明のベアチップの実装構造では、２回の
リフローソルダーリングによってベアチップ相互の接続
が可能となる。これによりベタパターン21からの信号
は、半田バンプ５を介してSiチップ４に入力され、又Si
チップ４からの信号は、他の半田バンプ５を介してLED
チップ３に送られ、このLEDチップ３から更にベタパタ
ーン21に出力される。As described above, in the bare chip mounting structure of the present invention, the bare chips can be connected to each other by performing the reflow soldering twice. As a result, the signal from the solid pattern 21 is input to the Si chip 4 via the solder bumps 5, and
The signal from the chip 4 is sent to the LED via another solder bump 5.
It is sent to the chip 3 and is further output from the LED chip 3 to the solid pattern 21.
尚上記実施例中プリント配線板１に重ね基板２を設けた
が、この重ね基板２の代わりにLEDチップ３の上面31と
略同面に所謂ダミーチップを設けることも可能である。Although the printed wiring board 1 is provided with the laminated substrate 2 in the above-described embodiments, a so-called dummy chip may be provided on the substantially same surface as the upper surface 31 of the LED chip 3 instead of the laminated substrate 2.
＜発明の効果＞ 以上説明した様に本発明のベアチップの実装構造は、ベ
アチップと第二のプリント配線板及び他のベアチップと
の間が半田バンプを介して直接接続されているため、１
半田バンプあたり10〜20gfとなって従来のワイヤボンデ
ィングに比べ倍近い強度を有するものとなり、したがっ
て機械的，電気的信頼性に優れたものとなる。すなわ
ち、他方のベアチップが、一方のベアチップにだけでな
く第二のプリント配線板にも半田バンプを介してそのパ
ターンに接続した状態で設けられていることから、他方
のベアチップが第二のプリント配線板にも電気的に導通
可能となり、これにより引張強度が低くしたがって機械
的，電気的信頼性に劣るワイヤボンディングを用いるこ
となく、高強度であり機械的，電気的信頼性に優れた半
田バンプによって他方のベアチップが一方のベアチッ
プ、及び第二のプリント配線板に実装されたものとなる
ため、この実装構造は機械的，電気的信頼性に優れたも
のとなるのである。<Effects of the Invention> As described above, in the bare chip mounting structure of the present invention, the bare chip is directly connected to the second printed wiring board and other bare chips through solder bumps.
Since each solder bump has a strength of 10 to 20 gf, which is almost double that of conventional wire bonding, it has excellent mechanical and electrical reliability. That is, since the other bare chip is provided not only on one bare chip but also on the second printed wiring board in a state of being connected to the pattern through solder bumps, the other bare chip is provided on the second printed wiring board. It is possible to conduct electricity to the board as well, and this makes it possible to use solder bumps with high strength and excellent mechanical and electrical reliability without the use of wire bonding, which has low tensile strength and thus has poor mechanical and electrical reliability. Since the other bare chip is mounted on the one bare chip and the second printed wiring board, this mounting structure has excellent mechanical and electrical reliability.
また、第二のプリント配線板が、その上面を一方のベア
チップの上面と略同一高さとなるようにしてプリント配
線板上に設けられていることから、これら第二のプリン
ト配線板と一方のベアチップとに跨がるようにして設け
られる他方のベアチップは、傾くことなくプリント配線
板に対し略平行に実装されたものとなり、これにより実
装構造全体が安定したものとなる。したがって、この実
装構造は不測の衝撃を受けた場合などにも断線等が生じ
る恐れが少なく、よって機械的，電気的信頼性に優れた
ものとなる。Further, since the second printed wiring board is provided on the printed wiring board so that its upper surface is substantially flush with the upper surface of one bare chip, these second printed wiring board and one bare chip are provided. The other bare chip provided so as to straddle and is mounted substantially parallel to the printed wiring board without tilting, and thus the entire mounting structure is stable. Therefore, this mounting structure is less likely to be broken even when it receives an unexpected shock, and thus has excellent mechanical and electrical reliability.
しかも組立工数は、２分（フラックス硬化）＋３分（リ
フローソルダ）＋５分（洗浄工程）＝10分で終了し、従
来のワイヤボンディングによる組立工数に比して約70％
の工数時間削減になる。Moreover, the assembly man-hour is completed in 2 minutes (flux hardening) + 3 minutes (reflow solder) + 5 minutes (cleaning process) = 10 minutes, which is about 70% of the conventional assembly process by wire bonding.
It reduces the man-hours of.
第１図は、本発明の実装構造を示す図、 第２図は、LEDチップの電極面を示す図、 第３図は、Siチップの半田バンプを説明する図、 第４図は、対向状態のLEDチップとSiチップを示す図、 第５図は、従来のワイヤボンディングによる実装構造を
示す図、 第６図は、他のワイヤボンディングによる実装構造を示
す図である。 １……プリント配線板,11……ベタパターン， ２……重ね基板（第二のプリント配線板）， 21……ベタパターン（パターン）， ３……LEDチップ（一方のベアチップ）,31……上面， 33……電極面（電極）， ４……Siチップ（他方のベアチップ）,41……下面， 42……電極面（電極）,5……半田バンプ。FIG. 1 is a view showing a mounting structure of the present invention, FIG. 2 is a view showing an electrode surface of an LED chip, FIG. 3 is a view explaining solder bumps of a Si chip, and FIG. 4 is a facing state. FIG. 5 is a view showing an LED chip and a Si chip, FIG. 5 is a view showing a conventional mounting structure by wire bonding, and FIG. 6 is a view showing another mounting structure by wire bonding. 1 ... Printed wiring board, 11 ... Solid pattern, 2 ... Stacked board (second printed wiring board), 21 ... Solid pattern (pattern), 3 ... LED chip (one bare chip), 31 ... Top surface, 33 ... Electrode surface (electrode), 4 ... Si chip (other bare chip), 41 ... Bottom surface, 42 ... Electrode surface (electrode), 5 ... Solder bump.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 33/00 Ｎ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 25/18 33/00 N
Claims (1)
リント配線板上に実装するベアチップの実装構造におい
て、 前記ベアチップのうちの一方がその上面に複数の電極形
成したフェースアップ型であり、他方がその下面に複数
の電極を形成したフェースダウン型であり、 前記プリント配線板の上には、前記一方のベアチップが
その下面を該プリント配線板に接続させた状態で設けら
れるとともに、該プリント配線板とは異なる第二のプリ
ント配線板がそのパターンを上に向け、かつその上面を
前記一方のベアチップの上面と略同一高さとなるように
して設けられ、 前記他方のベアチップは、その下面の電極が前記一方の
ベアチップの上面の電極に半田バンプを介して接続した
状態で該一方のベアチップ上に設けられるとともに、前
記第二のプリント配線板上にもこれのパターン上に半田
バンプを介して接続した状態で設けられてなることを特
徴とするベアチップの実装構造。1. A bare chip mounting structure in which two or more bare chips are connected to each other and mounted on a printed wiring board, wherein one of the bare chips is a face-up type in which a plurality of electrodes are formed on an upper surface of the bare chip. Is a face-down type in which a plurality of electrodes are formed on the lower surface of the printed wiring board, and the one bare chip is provided on the printed wiring board with its lower surface connected to the printed wiring board. A second printed wiring board different from the board is provided so that its pattern faces upward and its upper surface is substantially flush with the upper surface of the one bare chip, and the other bare chip is an electrode on the lower surface thereof. Is provided on the one bare chip in a state of being connected to an electrode on the upper surface of the one bare chip via a solder bump, and Mounting structure of the bare chip, characterized by comprising provided in a state of also connected via a solder bump on this pattern on a printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1101274A JPH0775270B2 (en) | 1989-04-20 | 1989-04-20 | Bare chip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1101274A JPH0775270B2 (en) | 1989-04-20 | 1989-04-20 | Bare chip mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02278893A JPH02278893A (en) | 1990-11-15 |
| JPH0775270B2 true JPH0775270B2 (en) | 1995-08-09 |
Family
ID=14296303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1101274A Expired - Fee Related JPH0775270B2 (en) | 1989-04-20 | 1989-04-20 | Bare chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0775270B2 (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6024584A (en) * | 1996-10-10 | 2000-02-15 | Berg Technology, Inc. | High density connector |
| WO1998034285A1 (en) | 1997-01-31 | 1998-08-06 | Matsushita Electronics Corporation | Light emitting element, semiconductor light emitting device, and method for manufacturing them |
| US7026718B1 (en) | 1998-09-25 | 2006-04-11 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| JP4580730B2 (en) * | 2003-11-28 | 2010-11-17 | ルネサスエレクトロニクス株式会社 | Offset junction type multi-chip semiconductor device |
| JP5052130B2 (en) * | 2004-06-04 | 2012-10-17 | カミヤチョウ アイピー ホールディングス | Semiconductor device having three-dimensional laminated structure and method for manufacturing the same |
| US6979238B1 (en) | 2004-06-28 | 2005-12-27 | Samtec, Inc. | Connector having improved contacts with fusible members |
| JP5354765B2 (en) | 2004-08-20 | 2013-11-27 | カミヤチョウ アイピー ホールディングス | Manufacturing method of semiconductor device having three-dimensional laminated structure |
| US8366485B2 (en) | 2009-03-19 | 2013-02-05 | Fci Americas Technology Llc | Electrical connector having ribbed ground plate |
| EP2624034A1 (en) | 2012-01-31 | 2013-08-07 | Fci | Dismountable optical coupling device |
| USD727268S1 (en) | 2012-04-13 | 2015-04-21 | Fci Americas Technology Llc | Vertical electrical connector |
| US9257778B2 (en) | 2012-04-13 | 2016-02-09 | Fci Americas Technology | High speed electrical connector |
| US8944831B2 (en) | 2012-04-13 | 2015-02-03 | Fci Americas Technology Llc | Electrical connector having ribbed ground plate with engagement members |
| USD718253S1 (en) | 2012-04-13 | 2014-11-25 | Fci Americas Technology Llc | Electrical cable connector |
| USD727852S1 (en) | 2012-04-13 | 2015-04-28 | Fci Americas Technology Llc | Ground shield for a right angle electrical connector |
| USD751507S1 (en) | 2012-07-11 | 2016-03-15 | Fci Americas Technology Llc | Electrical connector |
| US9543703B2 (en) | 2012-07-11 | 2017-01-10 | Fci Americas Technology Llc | Electrical connector with reduced stack height |
| USD745852S1 (en) | 2013-01-25 | 2015-12-22 | Fci Americas Technology Llc | Electrical connector |
| USD720698S1 (en) | 2013-03-15 | 2015-01-06 | Fci Americas Technology Llc | Electrical cable connector |
| IT201600084419A1 (en) * | 2016-08-10 | 2018-02-10 | St Microelectronics Srl | PROCEDURE FOR MAKING SEMICONDUCTOR, EQUIPMENT AND CORRESPONDENT CIRCUIT DEVICES |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0178069U (en) * | 1987-11-14 | 1989-05-25 |
-
1989
- 1989-04-20 JP JP1101274A patent/JPH0775270B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02278893A (en) | 1990-11-15 |
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