JPH0772507A - Thin film transistor panel - Google Patents

Abstract

PURPOSE:To make the capacity value of a compensating capacitor sufficiently large and to sufficiently secure the opening rate of a liquid crystal display element. CONSTITUTION:Respective gate lines 30 have projection parts 30a formed opposite pixel electrodes 22 in rows adjacent to respective pixel electrode rows that the gate lines 30 correspond to across their edge parts and a reverse-side gate insulating film 25, and a 1st compensating capacitor Cs1 is formed of the projection parts 30a of the gate lines 30, pixel electrodes 22, and the gate insulating film 25 between them; and electrodes 34 for capacitor formation which face the pixel electrodes 22 are provided on the top surface sides of said edge parts of the pixel electrodes 22 across the inter-layer insulating film 32, and a 2nd compensating capacitor Cs2 is formed of the electrodes 34 for capacitor formation, pixel electrodes 22, and the inter-layer insulating film 32 between them. Then the electrodes for capacitor formation are connected to the gate lines 30 and the 1st compensating capacitor Cs1 and 2nd compensating capacitor Cs2 are connected in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix liquid crystal display device using thin film transistors (TFTs) as active devices is provided with a group of pixel electrodes, a plurality of gate lines and data lines, and a plurality of thin film transistors corresponding to the respective pixel electrodes on a transparent substrate. The TFT panel and a counter panel provided with a counter electrode facing the pixel electrode group on the transparent substrate are joined together via a frame-shaped seal material, and a liquid crystal is formed in a region surrounded by the seal material of both panels. It is configured by enclosing.

FIG. 7 is a plan view of a part of a conventional TFT panel used in the active matrix liquid crystal display device. In the pixel electrode array pattern of the TFT panel, pixel electrodes are arranged linearly in the row direction and column direction, or the pixel electrodes are arranged linearly in the row direction and zigzag in the column direction. There are various patterns such as a mosaic array pattern, but in FIG.
1 shows a TFT panel having a pattern in which pixel electrodes are linearly arranged in a row direction and a column direction.

This TFT panel includes a plurality of pixel electrodes 2 arranged in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing) on a transparent substrate 1 made of glass or the like, and each of these pixels. A plurality of thin film transistors 3 respectively connected to the electrodes 2, a plurality of gate lines 10 wired to correspond to each pixel electrode row and supplying a gate signal to the thin film transistors 3 of that row, and a plurality of pixel electrode columns respectively. And a plurality of data lines 11 that are connected to each other and supply a data signal to the thin film transistors 3 in that column.

The thin film transistor 3 is formed by forming a gate electrode 4 on the substrate 1, a gate insulating film 5 covering the gate electrode 4, and a gate electrode 4 on the gate insulating film 5 so as to face the gate electrode 4. An i-type semiconductor film 6 made of a-Si (amorphous silicon) and an n-type semiconductor film (not shown) made of a-Si doped with impurities are formed on the i-type semiconductor film 6. It is composed of a source electrode 8 and a drain electrode 9.

The gate line 10 is wired on the substrate 1 along the pixel electrode row, and the gate electrode 4 of each thin film transistor 3 is connected to the gate line 10.
It is integrally formed by protruding to one side.

The gate insulating film 5 of the thin film transistor 3 is a transparent film made of Si N (silicon nitride) or the like. The gate insulating film 5 covers the gate line 10 and is formed on almost the entire surface of the substrate 1. Has been done.

Each pixel electrode 2 is formed on the gate insulating film 5 and is connected to the source electrode 8 of the thin film transistor 3 at its edge. The pixel electrode 2 is formed of a transparent conductive film such as ITO, and the source electrode 8 of the thin film transistor 3 is formed so as to overlap the end edge portion of the pixel electrode 2 with the pixel electrode 2. It is connected.

On the other hand, the data line 11 is wired on an interlayer insulating film (transparent film) 12 made of SiN or the like formed so as to cover the thin film transistor 3, and the data line 11 is connected to the interlayer insulating film 12. It is connected to the drain electrode 9 of the thin film transistor 3 through the contact hole 13 provided in the. The interlayer insulating film 12 is formed over the entire length of the wiring portion of the data line 11, and the portion of the interlayer insulating film 12 corresponding to each pixel electrode 2 exposes almost the entire pixel electrode 2. An opening is provided.

By the way, in the active matrix liquid crystal display device using the TFT panel, a reference potential signal is applied to the counter electrode of a counter panel (not shown), and a gate signal (scanning signal) is sequentially applied to each gate line 10 of the TFT panel. At the same time, a data signal having a voltage corresponding to the image data is applied to each data line 11 to drive the display.

That is, in the active matrix liquid crystal display element, a gate signal is applied to the thin film transistors 3 in each row during the selection period of the pixels in each row, and a data signal is applied to the thin film transistors 3 in each column in synchronization with this to drive the display. When the thin film transistor 3 is turned on by applying a gate signal during the selection period, a voltage corresponding to the data signal is applied between the pixel electrode 2 and the counter electrode through the thin film transistor 3, and the charge is applied to the pixel electrode. 2 and the counter electrode and the liquid crystal between them are stored in the pixel capacitor.

Then, in the non-selection period, the charges accumulated in the pixel capacitor are held in the pixel capacitor by turning off the thin film transistor 3, and the voltage corresponding to the amount of charge becomes the holding voltage of the pixel capacitor, and this pixel is The liquid crystal rises according to the holding voltage of the capacitor.

However, in this case, when the thin film transistor 3 is turned off, the voltage charged according to the data signal between the pixel electrode 2 and the counter electrode is the pixel capacitance and the gate of the thin film transistor 3 out of the voltage change of the gate signal. A voltage corresponding to the capacity ratio between the source-source capacity (the capacity between the gate electrode 4 and the source electrode 8) is reduced. This voltage drop is larger as the gate-source capacitance is larger than the pixel capacitance.

Therefore, in the active matrix liquid crystal display element, the TFT panel is provided with a compensation capacitor for compensating for the decrease in the voltage held in the pixel capacitor, and the holding voltage between the pixel electrode 2 and the counter electrode is provided. To ensure sufficient.

In FIG. 7, Cs is the above-mentioned compensation capacitance, and this compensation capacitance Cs is, for each pixel electrode row, the pixel electrode 2 of that row and the row next to this pixel electrode row (usually the previous row). 2) and the gate insulating film 5 between them.

That is, each gate line 10 is sandwiched between the lower surface of its edge and the gate insulating film 5 with respect to each pixel electrode 2 in the row adjacent to each pixel electrode row to which the gate line 10 corresponds. An overhanging portion 10a facing each other is formed, and the overhanging portion 10a of the gate line 10, the pixel electrode 2 and the gate insulating film 5 between them form the compensation capacitance Cs.

FIG. 8 is an equivalent circuit diagram of one pixel portion of the TFT panel. The compensation capacitance Cs is the pixel capacitance C which is composed of the pixel electrode 2, the counter electrode and the liquid crystal between them.
Connected in parallel to LC.

If the compensation capacitance Cs is provided, the capacitance obtained by combining the pixel capacitance CLC and the compensation capacitance Cs becomes sufficiently larger than the gate-source capacitance Cgs of the thin film transistor 3, and the thin film transistor 3 is in the non-selection period. Pixel capacitance CLC according to the voltage change of the gate signal when turned off
The change in voltage becomes small. Therefore, the voltage (holding voltage) held in the pixel capacitor CLC in the non-selection period after the gate signal is changed to the low potential can be kept high, so that the liquid crystal is applied to the voltage (data It is possible to operate at a voltage close to (voltage corresponding to the signal).

[0019]

However, the above-mentioned conventional TFT panel has a problem that when the capacitance value of the compensation capacitance Cs is increased, the aperture ratio of the liquid crystal display element is reduced and the screen becomes dark.

This is because the gate line 10 is formed of a low resistance metal film made of Cr (chromium), Al (aluminum), Al alloy or the like, and since these metal films do not transmit light, the gate line 10 When the compensation capacitor Cs is formed by making the overhanging portion 10a of the above face the pixel electrode 2,
The aperture area of the pixel (the area of the region through which light can pass) becomes smaller accordingly.

That is, FIG. 9 shows the opening area of one pixel in the above-mentioned conventional TFT panel. This opening area is the area of the pixel electrode 2 from which the overhanging portion 10a of the gate line 10 is opposed. It is the area excluding the area (the area of the hatched region in the figure).

In the conventional TFT panel, the capacitance value of the compensation capacitance Cs is the overhanging portion 10 of the gate line 10.
Since it is determined by the area where a and the pixel electrode 2 face each other, in order to increase the capacitance value of the compensation capacitance Cs, the gate line 10
The facing area between the overhanging portion 10a and the pixel electrode 2 must be increased. Therefore, when the capacitance value of the compensation capacitance Cs is increased, the aperture area of the pixel, that is, the aperture ratio is reduced, and the screen becomes dark.

An object of the present invention is to provide a TFT panel in which the capacitance value of the compensation capacitor can be made sufficiently large and the aperture ratio of the liquid crystal display element can be sufficiently secured.

[0024]

A TFT panel of the present invention comprises a plurality of pixel electrodes arranged in a row direction and a column direction on a transparent substrate, and a plurality of thin film transistors connected to the respective pixel electrodes. , A plurality of gate lines wired corresponding to each pixel electrode row and supplying a gate signal to the thin film transistors in that row, and a plurality of gate lines wired corresponding to each pixel electrode column and supplying a data signal to the thin film transistors in that column And a data line of a pixel electrode of a row adjacent to the pixel electrode row corresponding to the gate line, and the insulating film is sandwiched between one side of the pixel electrode and the pixel electrode of the row adjacent to the pixel electrode row. Forming opposing overhanging portions, the overhanging portions of the gate line, the pixel electrode and an insulating film between them form a first compensation capacitance, and the edge portion of the pixel electrode is formed. A capacitance forming electrode facing the pixel electrode is provided on the other surface side across another insulating film, and a second compensation capacitance is formed by the capacitance forming electrode, the pixel electrode and the insulating film between them. At the same time, the capacitance forming electrode is connected to the gate line to connect the first compensation capacitance and the second compensation capacitance.
It is characterized by connecting in parallel with the compensation capacity of.

[0025]

According to the present invention, for each pixel electrode, the first compensation capacitor composed of the overhanging portion of the gate line corresponding to the adjacent pixel electrode row, the pixel electrode and the insulating film between them, and the capacitor forming capacitor are formed. Since a second compensation capacitance composed of an electrode, a pixel electrode and an insulating film between them is provided and these two compensation capacitances are connected in parallel, the capacitance value of the compensation capacitance for one pixel is equal to It is the sum of the capacitance values of the two compensation capacitances. Therefore, even if the individual capacitance values of the first compensation capacitance and the second compensation capacitance are small, the capacitance value of the compensation capacitance can be made sufficiently large.

Further, in the present invention, since the overhanging portion of the gate line faces one surface of the edge portion of the pixel electrode, and the capacitance forming electrode faces the other surface of the edge portion of the pixel electrode, Since the first compensation capacitance and the second compensation capacitance are vertically overlapped with each other, the opening area of the pixel is larger than the area of the pixel electrode by the extension of the gate line and the pixel electrode of the capacitance forming electrode. The facing area of the pixel electrode is reduced by the facing area of the pixel electrode.

Since the individual capacitance values of the first compensation capacitance and the second compensation capacitance may be small, the overhanging portion of the gate line and the facing area between the capacitance forming electrode and the pixel electrode are both small. Well, the aperture area of the pixel is
According to the present invention, the capacitance value of the compensation capacitance is sufficiently increased because the pixel electrode facing area, which has the larger facing area with respect to the pixel electrode among the overhanging portion of the gate line and the capacitance forming electrode, is reduced. In addition, the aperture ratio of the liquid crystal display element can be sufficiently secured.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In the TFT panel of this embodiment, pixel electrodes are linearly arranged in the row direction and the column direction.

FIG. 1 is a plan view of a part of the TFT panel, FIG. 2 is an enlarged sectional view taken along line II-II of FIG. 1, and FIG. 3 is I of FIG.
FIG. 4 is an enlarged sectional view taken along line II-III, and FIG. 4 is an enlarged sectional view taken along line IV-IV in FIG.

This TFT panel has a plurality of pixel electrodes 22 arranged in a row direction (horizontal direction in the figure) and a column direction (vertical direction in the figure) on a transparent substrate 21 made of glass or the like, and each of these pixels. A plurality of thin film transistors 23 respectively connected to the electrodes 22, a plurality of gate lines 30 wired to correspond to each pixel electrode row and supplying a gate signal to the thin film transistors 23 in that row, and each corresponding to each pixel electrode column. And a plurality of data lines 31 that are connected to each other and supply a data signal to the thin film transistors 30 in that column.

As shown in FIGS. 1 and 2, the thin film transistor 23 has a gate electrode 2 formed on a substrate 21.
4 and a gate insulating film 25 covering the gate electrode 24,
An i-type semiconductor film 26 of a-Si formed on the gate insulating film 25 so as to face the gate electrode 24.
And an impurity doped a on the i-type semiconductor film 26
It is composed of a source electrode 28 and a drain electrode 29 formed via an n-type semiconductor film 27 made of -Si.

The gate line 30 has Cr, A
The gate line 30 is formed on the substrate 21 along the row of pixel electrodes, and the gate electrode 24 of each thin film transistor 23 is formed of the low resistance metal film made of Al, Al alloy, or the like. The line 30 is integrally formed by projecting to one side thereof.

The gate insulating film 25 of the thin film transistor 23 is a transparent film made of SiN or the like,
The gate insulating film 25 is formed on almost the entire surface of the substrate 21 so as to cover the gate line 30 as well.

Each pixel electrode 22 is formed on the gate insulating film 25 and is connected to the source electrode 28 of the thin film transistor 23 at its edge. The pixel electrode 22 is formed of a transparent conductive film such as ITO, and the source electrode 28 of the thin film transistor 23 is formed with the pixel electrode 22 by overlapping its end portion on the end edge portion of the pixel electrode 22. It is connected.

Further, the data line 31 has Cr, Al
, A low resistance metal film made of Al alloy or the like, and the data line 31 is formed by the thin film transistor 2 described above.
Wiring is performed on the interlayer insulating film (transparent film) 32 made of Si 3 N or the like formed so as to cover 3 and is connected to the drain electrode 29 of the thin film transistor 23 in the contact hole 33 provided in the interlayer insulating film 32. The interlayer insulating film 32 is formed on the wiring portion of the data line 31 over the entire length thereof, and the pixel electrode 22 is almost entirely exposed at the portion of the interlayer insulating film 32 corresponding to each pixel electrode 22. An opening is provided.

On the other hand, in FIGS. 1, 3 and 4, C
s1 is a first compensation capacitance, and this compensation capacitance Cs1 is, for each pixel electrode row, the pixel electrode 22 of that row and the gate of the row next to this pixel electrode row (the previous row in this embodiment). It is formed by the line 30 and the gate insulating film 25 between them.

That is, each gate line 30 is sandwiched between the lower surface of the edge and the gate insulating film 25 with respect to each pixel electrode 22 in the row adjacent to each pixel electrode row to which the gate line 30 corresponds. An overhanging portion 30a facing each other is formed, and the overhanging portion 30a of the gate line 30, the pixel electrode 22 and the gate insulating film 25 between them form the first compensation capacitance Cs1.

Further, in FIG. 1, FIG. 3 and FIG.
Cs2 is a second compensation capacitance formed for each pixel electrode 22, and this compensation capacitance Cs2 is on the upper surface side of the above-mentioned edge portion of the pixel electrode 22 (edge portion facing the overhanging portion 30a of the gate line 30). By providing a capacitance forming electrode 34 facing the pixel electrode 22 across the interlayer insulating film 32, the capacitance forming electrode 34, the pixel electrode 22 and the interlayer insulating film 32 between them are formed. .

For this reason, the interlayer insulating film 32 is formed so as to cover the edge portion of the pixel electrode 22 (pixel electrode 22).
Is formed in such a shape). In addition, the capacitance forming electrode 34 is formed of the interlayer insulating film 32.
It is formed of the same metal film as that of the data line 31 which is wired above.

Further, the edge portion of the pixel electrode 22 is formed in a shape in which both end portions thereof are cut out, and both end portions of the capacitance forming electrode 34 are subjected to interlayer insulation in correspondence with the cutout portion of the pixel electrode 22. Overhang 3 of gate line 30 in contact hole 35 formed in film 32 and gate insulating film 25.
0a. Therefore, the first compensation capacitance Cs1 and the second compensation capacitance Cs2 are connected in parallel.

FIG. 5 is an equivalent circuit diagram of one pixel portion of the above TFT panel, which is an extension portion 30a of the gate line 30.
The first compensation capacitance Cs1 formed by the pixel electrode 22 and the gate insulating film 25 between the pixel electrode 22 and the pixel electrode 22, and the pixel capacitance CLC formed by the pixel electrode 22, the counter electrode of the counter panel (not shown) and the liquid crystal therebetween. The capacitance forming electrode 34, the pixel electrode 22 and the interlayer insulating film 32 therebetween are connected in parallel.
The second compensation capacitor Cs2 formed by (1) and (2) is connected in parallel with the first compensation capacitor Cs1. That is, these compensation capacitors Cs1 and Cs2 are connected in parallel with the pixel capacitor CLC.

In this embodiment, the gate line 30
The facing area between the overhanging portion 30a of the pixel electrode 22 and the facing area between the capacitance forming electrode 34 and the pixel electrode 22 is made substantially equal, and the overhanging portion 30a of the gate line 30 is formed.
And the thickness of the gate insulating film 25 between the pixel electrode 22 and the interlayer insulating film 3 between the capacitance forming electrode 34 and the pixel electrode 22.
The second compensation film Cs1 and the second compensation capacitor Cs2 are formed to have substantially the same thickness by forming the second compensation film Cs1 and the second compensation film Cs1 to have substantially the same film thickness.

That is, the above TFT panel is provided with two compensation capacitors, a first compensation capacitor Cs1 and a second compensation capacitor Cs2, for each pixel electrode 22. CLC and compensation capacitance Cs1, Cs2
Since the combined capacitance with the capacitance Cgs is sufficiently larger than the gate-source capacitance Cgs of the thin film transistor 23, the rate at which the voltage of the pixel electrode 22 decreases in accordance with the voltage change of the gate signal becomes small, and the pixel capacitance CLC in the non-selection period is reduced. It is possible to reduce the decrease in the holding voltage held.

In the above-mentioned TFT panel, each pixel electrode 22 is composed of the overhanging portion 30a of the gate line 30 corresponding to the adjacent pixel electrode row, the pixel electrode 22 and the gate insulating film 25 between them. 1 compensation capacity Cs1
And a second compensation capacitance Cs2 composed of the capacitance forming electrode 34, the pixel electrode 22 and the interlayer insulating film 32 therebetween, and these two compensation capacitances Cs1 and Cs2 are connected in parallel. The capacitance value of the compensation capacitance for one pixel is the sum of the capacitance values of the two compensation capacitances Cs1 and Cs2. Therefore, the individual capacitance values of the first compensation capacitance Cs1 and the second compensation capacitance Cs2 are small. Also, the capacitance value of the compensation capacitance can be made sufficiently large.

In the TFT panel, the overhanging portion 30a of the gate line 30 faces one surface of the edge portion of the pixel electrode 22, and the capacitance forming electrode 34 is used as the pixel electrode 22.
Of the edge, that is, the overhanging portion 30a of the gate line 30.
Since the first compensation capacitor Cs1 and the second compensation capacitor Cs2 are vertically overlapped with each other, the opening area of the pixel is equal to the pixel electrode 22. Area of the gate line 30 overhanging portion 30a
And the pixel electrode 22.
Since it is only reduced by the facing area with
According to the FT panel, it is possible to make the capacitance value of the compensation capacitance sufficiently large and also to secure a sufficient aperture ratio of the liquid crystal display element.

That is, FIG. 6 shows the opening area of one pixel in the above-mentioned TFT panel. In this embodiment, the projecting portion 30a of the gate line 30 and the pixel electrode 22 are shown.
Since the facing area of the pixel electrode 22 and the facing area of the capacitance forming electrode 34 and the pixel electrode 22 are substantially equal to each other,
The amount of decrease in the opening area of the pixel with respect to the area of the pixel area is either one of the overhang portion 30a of the gate line 30 and the capacitance forming electrode 34, for example, the facing area between the overhang portion 30a of the gate line 30 and the pixel electrode 22 (in the figure Only the area of the hatched area). The decrease in the opening area is calculated by adding the two capacitances Cs1 and Cs2 to the compensation capacitance C of the conventional TFT panel shown in FIGS.
When the capacitance value is the same as that of s, the reduction of the opening area in the conventional TFT panel is about 1/2.

As described above, since the individual capacitance values of the first compensation capacitance Cs1 and the second compensation capacitance Cs2 may be small, the overhanging portion 30a of the gate line 30, the capacitance forming electrode 34, and the pixel electrode. The facing area of the pixel electrode 22 may be small, and the opening area of the pixel is small by the facing area of one of the overhanging portion 30a of the gate line 30 and the capacitance forming electrode 34 and the pixel electrode 22. Therefore, according to the above-mentioned TFT panel, the capacitance value of the compensation capacitor can be made sufficiently large and the aperture ratio of the liquid crystal display element can be sufficiently secured.

In the above embodiment, the capacitance forming electrode 34 for forming the second compensation capacitance Cs2 with the pixel electrode 22 is formed of the same metal film as the data line 31. The formation electrode 34 can be formed by using the process of forming the data line 31, and the thin film transistor 23 is formed on the insulating film between the capacitance formation electrode 34 and the pixel electrode 22 in the data line wiring portion. Since the interlayer insulating film 32 is used, the TFT is provided with the second compensation capacitance Cs2 in addition to the first compensation capacitance Cs1.
The panel can be manufactured in a small number of steps.

In the above embodiment, the gate line 30 is used.
Although the facing area between the overhanging portion 30a and the pixel electrode 22 is substantially equal to the facing area between the capacitance forming electrode 34 and the pixel electrode 22, the facing area of the overhanging portion 30a of the gate line 30 and the capacitance The area of the forming electrode 34 facing the pixel electrode may be different from each other, and in that case, the opening area of the pixel is equal to that of the overhanging portion 30 a of the gate line 30 and the pixel electrode 22 of the capacitance forming electrode 34. It is only reduced by the facing area of the pixel electrode having the larger facing area.

Further, in the above embodiment, the capacitance forming electrode 3
4 at both ends of the gate line 30
Although it is connected to 0a, the capacitance forming electrode 34 may be connected to another portion of the gate line 30, and the number of the connecting portions may be arbitrary.

Further, in the TFT panel of the above-mentioned embodiment, the pixel electrodes 22 are arranged linearly in the row direction and the column direction. In the present invention, however, the pixel electrodes are arranged linearly in the row direction. T of various pixel electrode array patterns such as a mosaic array pattern arranged in a zigzag in the column direction.
It can be widely applied to FT panels.

[0052]

According to the TFT panel of the present invention, each gate line is sandwiched between the pixel electrode of the row adjacent to each pixel line to which the gate line corresponds and the one surface of the edge portion and the insulating film. Opposing overhanging portions are formed, the overhanging portions of the gate line, the pixel electrode and the insulating film between them form a first compensation capacitance, and another insulating film is formed on the other surface side of the edge portion of the pixel electrode. A capacitance forming electrode facing the pixel electrode is provided across the film, and a second compensation capacitance is formed by the capacitance forming electrode, the pixel electrode, and an insulating film between the electrode and the capacitance forming electrode. Since the first compensation capacitance and the second compensation capacitance are connected in parallel by connecting to the gate line, the capacitance value of the compensation capacitance is sufficiently increased, and the aperture ratio of the liquid crystal display element is sufficiently secured. can do.

[Brief description of drawings]

FIG. 1 is a plan view of a part of a TFT panel according to an embodiment of the present invention.

FIG. 2 is an enlarged sectional view taken along line II-II of FIG.

FIG. 3 is an enlarged sectional view taken along line III-III in FIG.

4 is an enlarged sectional view taken along the line IV-IV in FIG.

FIG. 5 is an equivalent circuit diagram of one pixel portion of a TFT panel according to an embodiment of the present invention.

FIG. 6 is a diagram showing an opening area of one pixel of a TFT panel according to an embodiment of the present invention.

FIG. 7 is a plan view of a part of a conventional TFT panel.

FIG. 8 is an equivalent circuit diagram of one pixel portion of a conventional TFT panel.

FIG. 9 is a diagram showing an opening area of one pixel of a conventional TFT panel.

[Explanation of symbols]

 21 ... Substrate 22 ... Pixel electrode 23 ... Thin film transistor 24 ... Gate electrode 25 ... Gate insulating film 26 ... i-type semiconductor layer 27 ... N-type semiconductor layer 28 ... Source electrode 29 ... Drain electrode 30 ... Gate line 30a ... Overhang part 31 ... Data Line 32 ... Interlayer insulating film 34 ... Capacitance forming electrode Cs1 ... First compensation capacitance Cs2 ... Second compensation capacitance

Claims (1)

[Claims] 1. A plurality of pixel electrodes arranged in a row direction and a column direction on a transparent substrate, a plurality of thin film transistors connected to the respective pixel electrodes, and wirings corresponding to the respective pixel electrode rows. A plurality of gate lines for supplying a gate signal to the thin film transistors in that row, and a plurality of data lines wired corresponding to each pixel electrode column and supplying a data signal to the thin film transistors in that column, and The gate line is formed with an overhanging portion that faces the pixel electrode of the row adjacent to the pixel electrode row to which the gate line corresponds, with one surface of the edge portion sandwiching an insulating film. A first compensation capacitor is formed by the overhang portion of the line, the pixel electrode and an insulating film between the pixel electrode and the pixel electrode with another insulating film sandwiched on the other surface side of the edge portion of the pixel electrode. A capacitance forming electrode facing the pole is provided, and a second compensation capacitance is formed by the capacitance forming electrode, the pixel electrode and an insulating film therebetween, and the capacitance forming electrode is connected to the gate line. A thin film transistor panel, wherein the first compensation capacitance and the second compensation capacitance are connected in parallel.