JPH077248B2 - Driving method of display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and a driving method for a flat panel display device, and more particularly to a driving circuit and a driving circuit for a display device which receives a digital image signal and performs gradation display corresponding to the digital value. It relates to a driving method.

[0002]

2. Description of the Related Art When driving a liquid crystal display device, a special display drive circuit is used because the response speed of liquid crystal is very low as compared with a fluorescent substance used in a CRT (cathode ray tube) display device. That is, in the liquid crystal display drive circuit, the image signals sent from moment to moment are not given to each picture element as they are, but the image signal sampled corresponding to each picture element within one horizontal period is held during that horizontal period. , Is output all at once at the beginning of the next horizontal period or at an appropriate time in the middle.
Then, after the output of the image signal voltage to each picture element is started, the signal voltage is held for a time sufficiently exceeding the response speed of the liquid crystal.

In order to hold this signal voltage, a conventional drive circuit uses a capacitor. FIG. 13 shows a signal voltage output circuit (source driver) for supplying a driving voltage to N picture elements on one scanning line selected by a scanning signal.
As shown in FIG. 14, the signal voltage output circuit for the nth picture element includes an analog switch SW ₁ , a sampling capacitor C _SMP , an analog switch SW ₂ , a hold capacitor C _H , and an output buffer amplifier A. There is. The operation of the conventional signal voltage output will be described with reference to these circuit diagrams and the signal timing diagram of FIG.

The analog image signal v _S input to the analog switch SW ₁ is a sampling clock signal T _SMP1 corresponding to each of N picture elements on one scanning line selected for each horizontal synchronizing signal H _syn. ~ T _{S MPN} is sequentially sampled. By this sampling, the instantaneous voltages V _{SMP1 to} V _SMPN of the image signal v _S at each time point are applied to the sampling capacitors C _SMP . The nth sampling capacitor C _SMP is charged by the value V _SMPn of the image signal voltage corresponding to the nth picture _element and holds that value. The signal voltages V _{SMP1 to} V _SMPN thus sequentially sampled and held during one horizontal period are transferred from the sampling capacitors C _SMP to the hold capacitors C _H by the output pulse OE which is simultaneously applied to all the analog switches SW _2. Moved, via the buffer amplifier A,
Is output to the source lines O ₁ ~ O _N connected to each picture element.

Although the drive circuit described above is for the case where an image signal is given in analog, there are some problems as follows in order to increase the capacity and the definition of the liquid crystal panel. It is clear.

(A1) When the charge charged in the sampling capacitor C _SMP is transferred to the hold capacitor C _H ,
The following equation holds between the voltage V _H appearing on the hold capacitor C _H and the sampled voltage V _SMP .

[0007]

[Equation 1]

Therefore, in order for the voltage V _H held by the hold capacitor C _H to be substantially the same value as the sampled voltage V _SMP , the condition C _SMP >> C _H must be satisfied. That is, the sampling capacitor C
_It is necessary to use _SMP with a large value above a certain level. However, if the value of the sampling capacitor C _SMP is too large, it is necessary to take a long time for charging it, that is, one sampling time. But,
Since the number of picture elements corresponding to one horizontal period increases as the liquid crystal display device becomes larger or finer, one sampling time needs to be shortened in inverse proportion to it. For these reasons, the analog sampling method has limitations in increasing the size and high definition of the liquid crystal display device.

(A2) The analog image signal is supplied to the source driver through the bus line, but the frequency band of the image signal becomes wider and the wiring capacity of the bus line becomes larger as the display device becomes larger and finer. . Therefore,
A wide band power amplifier is required on the side of the circuit for supplying the image signal, which causes a cost increase.

(A3) When a plurality of analog image signal supply bus lines are provided as in the case of color image display using R, G and B video signals, it is possible to increase the capacity and definition of the display panel. Accordingly, the above-mentioned wide band amplifier is required to have extremely high performance and quality in which there is no phase difference between a plurality of image signals and variation in amplitude characteristics and frequency characteristics does not occur.

(A4) Unlike the case of displaying on a CRT, the driving circuit in the matrix type display device samples an analog image signal according to a clock and displays it on picture elements arranged in a matrix. At this time, signal delay in the drive circuit including delay in the bus line is unavoidable, so it is very difficult to ensure the accuracy of the sampling position with respect to the analog image signal. In particular, in the case of computer graphics in which the relationship between the image signal and the address of the display pixel must be strictly matched, the display position of the image caused by the signal delay and the deterioration of the frequency characteristic occurring in the driving system. Deviation and image bleeding are important problems.

Many of these problems that occur when using analog image signals are solved by making the image signals digital data. When the image signal is given as digital data, a driving circuit as shown in FIGS. 16 and 17 is used. Note that, here, for simplification, the image signal data is assumed to be composed of 2 bits (D ₀ , D ₁ ). That is, the image signal data has four values of _{0 to 3} , and the signal voltage applied to each picture element is one of the four levels of V _{0 to} V ₃ . FIG. 16 is a circuit diagram of a digital source driver circuit corresponding to the analog source driver circuit shown in FIG. 13, and shows the entire source driver which supplies a driving voltage to N picture elements. FIG. 17 shows a portion for the nth picture element,
This circuit includes a first-stage D flip-flop (sampling flip-flop) M _SMP and a second-stage flip-flop (hold flip-flop) provided for each bit (D ₀ , D ₁ ) of image signal data. M _H, 1 single decoder DEC, respectively by the analog switches ASW ₀ ~ASW ₃ provided comprised between four external voltage sources V ₀ ~V ₃ and the source line O _n. Various types of digital image signal data can be used in addition to the D flip-flop.

This digital source driver operates as follows. The image signal data D ₀ and D ₁ are taken into the sampling flip-flop M _SMP at the rising time of the sampling pulse T _SMPn corresponding to the n-th picture element and held there. When the sampling for one horizontal period is completed, the output pulse OE changes to the hold flip-flop M _H.
The image signal data D ₀ and D _{1 which} are given to the holding flip-flop M _H and are held in the sampling flip-flop M _SMP are taken into the hold flip-flop M _H and output to the decoder DEC. The decoder DEC decodes the 2-bit image signal data D ₀ and D ₁ and sets any one of the analog switches ASW _{0 to} ASW ₃ to be conductive in accordance with the value (0 to 3) of the four external voltages. outputs one of the V ₀ ~V ₃ to the source line O _n.

[0014]

The source driver for sampling with the digital image signal has the problem (A1) that occurs when sampling with the analog image signal.
Although the problem of (A4) is solved, there are still the following problems to be solved.

(D1) As the number of bits of digital image signal data increases, the size of the memory cells, decoders, etc., which constitute the drive circuit, rapidly increases, and the chip size and cost increase significantly.

(D2) A voltage source supplied from the outside (see FIG. 1).
6 and V _{0 to} V _{3 in} FIG. 17 need to be directly connected to the source line of the liquid crystal panel to drive the source line when selected by the analog switch. Therefore, it is necessary to have a performance that can sufficiently drive a heavy load such as a liquid crystal panel, and an LSI that constitutes a drive circuit.
It is difficult to create it internally, and it needs to be supplied from the outside, which causes a cost increase. In particular, as the number of data bits increases, the number of voltage sources increases with a power of 2, and as the number of bits increases, the cost increases significantly. For example, when image signal data is given by 4 bits (D ₀ , D ₁ , D ₂ , D ₃ ) and 16 gradations are displayed, the source driver becomes as shown in FIG. 19 and 2 ⁴ = A 16-level signal voltage (V _{0 to} V ₁₅ ) is required. Therefore, the number of voltage sources required in this case is 16.

(D3) The number of voltage sources increases by a power of 2 as described above. Therefore, the number of input terminals of the LSI constituting the drive circuit also increases by the same number. For example, when the data is changed from 5 bits to 6 bits, the number of the voltage sources, that is, the number of input terminals is increased from 2 ⁵ = 32 to 2 ⁶ = 64, which is 32 at a stretch. Therefore, it is practically difficult to create an LSI. In addition, even if it is possible to create an LSI, a problem in mounting or production occurs,
This leads to a situation where actual mass production is impossible.

When increasing the number of bits of the image signal data, the number of analog switches increases by a power of two. Further, since the ON resistance of the analog switch is inserted between the voltage source and the source line, it is desirable to make the ON resistance of the analog switch as small as possible. For this reason, the size of the analog switch on the chip cannot be made too small, which hinders the miniaturization of the chip.

Further, since the power consumption of the voltage source is quite large, the power consumption of the entire drive circuit is large.

The present invention has been made from such a viewpoint, and an object thereof is to provide a display device, a driving method and a driving circuit for the display device which can solve the above-mentioned problems. .

[0021]

SUMMARY OF THE INVENTION The present invention is a display having display picture elements arranged in a matrix, scanning lines connected to the display picture elements, and signal lines connected to the display picture elements. A panel, a means for sequentially supplying a scanning voltage for selecting the display pixel to different scanning lines for each scanning period, and a driving voltage for driving the selected display pixel on the signal line. And a drive circuit having means for supplying to the display device, and a drive method of a display device capable of multi-gradation display, wherein an oscillating voltage having an oscillating component oscillating during the one scanning period is used as the drive voltage. The oscillating voltage output operation to be output from the drive circuit to the signal line, and the drive voltage by passing through a circuit system existing on the path from the signal line to the display pixel and operating as a low pass filter. Of the averaged voltage that suppresses the vibration component of The above-mentioned problem is solved by performing an averaging voltage applying operation to be applied to the selected display picture element and using the averaged voltage as a halftone driving voltage necessary for halftone display driving of the display picture element. There is provided a novel and useful method for driving a display device.

The present invention also provides a display panel having display picture elements arranged in a matrix, scanning lines connected to the display picture elements, and signal lines connected to the display picture elements, and the display panel. The scanning voltage for selecting the picture element is set for each scanning period,
Multi-gradation display is possible, which includes a drive circuit having means for sequentially supplying different scan lines and means for supplying a drive voltage for driving the selected display pixel to the signal line. A method of driving a display device, wherein one of a plurality of voltages supplied from a power supply and each having a substantially constant value during the one scanning period is used as the driving voltage from the driving circuit to the signal line. It oscillates during the one scanning period obtained by alternately outputting and applying the drive voltage to the selected display pixel and two selected voltages selected from the plurality of voltages. An oscillating voltage having an oscillating component is output as the drive voltage from the drive circuit to the signal line, and passes through a circuit system that exists on the path from the signal line to the display pixel and that operates as a low-pass filter. The vibration component of the drive voltage Operation for applying the pressure was averaged voltage to the display picture element is the selected, by selectively perform, can effectively solve the problems described above. Also,
Vibration oscillating during the one scanning period obtained by alternately switching between an output state in which one of two selected voltages selected from the plurality of voltages is output as the oscillating voltage and an output state in which both are simultaneously output. An oscillating voltage having a component can also be used.

Further, according to the present invention, display picture elements arranged in a matrix, switching elements provided in each of the display picture elements, and a scanning line connected to the display picture element via the switching element. A liquid crystal display panel having a signal line connected to the display pixel through the switching element,
Means for sequentially supplying a scanning voltage for selecting the display picture element to different scanning lines for each scanning period, and supplying a driving voltage for driving the selected display picture element to the signal line. And a driving circuit including a driving means, the driving voltage being determined according to a digital signal value indicating a gradation input to the driving circuit. And an oscillating voltage output operation for outputting an oscillating voltage having an oscillating component that oscillates while the switching element is in an ON state to the signal line as the drive voltage from the drive circuit, and the signal line. From the display pixel to the display pixel, the averaged voltage that suppresses the vibration component of the drive voltage is passed to the selected display pixel by passing through a circuit system that operates as a low-pass filter. Averaging voltage applied When, by performing, it is possible to effectively solve the problems described above.

In each of the above-mentioned configurations, the following is also possible.

The frequency of a driving voltage having an oscillating component or a clock signal for forming the oscillating voltage is set to a predetermined value or more, and the oscillation amplitude of each driving voltage is a high level constant voltage value or a low level constant voltage value. It is desirable to set it so as to periodically oscillate.

It is preferable that the predetermined value is equal to or higher than the cutoff frequency of the low pass filter means. It is preferable that the low-pass filter means is substantially formed by the signal line, the picture element, and the switching element.

An element forming the low pass filter means may be connected to the signal line.

[0028]

Consider the voltage v (t) whose waveform changes at a period 2π as shown in FIG. The waveform shown in FIG. 6 is merely an example, and any voltage waveform can be handled in the present invention as long as it is a periodic function. By the way, a function f with a period of 2π
(X) can be represented by the following Fourier series under the condition that integration is possible.

[0029]

[Equation 2]

Since it is clear that an actual voltage waveform can be integrated, the periodic voltage v (t) can be expressed by the following equation 3.

[0031]

[Equation 3]

[0032] In several 3, a _0/2 are constants. Thus, the number 3 is oscillating voltage has a period 2π v (t) is the DC component a _0/2, the fundamental frequency component of the period 2 [pi, second harmonic component, third harmonic component or the like is applied to the endless It shows that it is a voltage. Therefore, if the voltage v (t) is passed through a low-pass filter having a cutoff frequency period sufficiently longer than 2π, the second term of Equation 3 is removed, and a DC component a _0/2 is obtained as the output of the filter. To be

[0033] By the way, the DC component a _0/2 of v (t) is

[0034]

[Equation 4]

It is represented by Formula 4 is a value obtained by integrating a periodic function having a period of 2π from −π to + π, that is, by integrating the period over one period, and further dividing the period by the period. The DC component of the voltage v (t) is the voltage v (t). ) Is an average value. Therefore, it is understood that the average value of the periodic oscillating voltage v (t) is obtained as the output from the filter having the above characteristics.

FIG. 7 shows an equivalent circuit of the signal line to be driven in the present invention. In the figure, R _S is the resistance of the signal line, C _S
Indicates the capacity of the signal line. V _COM indicates the voltage of the counter electrode. The actual picture element C _LC is represented as a capacity C _LC connected in parallel to the signal line capacity C _S as shown by the broken line in the figure, but since C _S >> C _LC , the picture element C _LC is C _LC may be ignored as an equivalent circuit of the signal line. That is, picture element C _LC
It can be considered that the voltage applied to the same voltage has the same value as the voltage at the connection point A between the resistance R _S and the capacitance C _S shown in FIG.

Considering the equivalent circuit of FIG. 7 from another point of view, it is understood that this is a first-order low-pass filter itself composed of a resistor R _S and a capacitor C _S.
Therefore, when the above periodic oscillating voltage v (t) is applied to the input side of this low-pass filter, the period 2π of v (t) becomes
If the period of the cutoff frequency of this low-pass filter determined by the resistance R _S and the capacitance C _S is sufficiently short, the voltage applied to the point A, that is, the pixel is sufficiently close to the average voltage of the periodic oscillation voltage v (t).

The transfer function T (jω) in the circuit of FIG. 7 is

[0039]

[Equation 5]

It is expressed as

When (1 / C _S R _S ) = ω ₀ ,

[0042]

[Equation 6]

When normalized by dividing by ω ₀ ,

[0044]

[Equation 7]

Here, ω / ω ₀ is a normalized frequency.

The amplitude characteristic | T | of this transfer function is

[0047]

[Equation 8]

It becomes From this, FIG. 18 is obtained. From FIG. 18, for example, when ω / ω ₀ = 100, point A in FIG.
It can be seen that the amplitude appearing at is 1/100.

In the display device, the value of ω / ω ₀ is not unconditionally determined, and the voltage difference ΔV (= │V _n -V _{n + 1} between adjacent levels.
|) And the required display quality. For example, if ΔV = 5V and an error of up to 0.05V is recognized in the required display quality, the above value of ω / ω ₀ = 100 or more is required.

In this case, it is understood that if C _S R _S = 10 × 10 ⁻⁶ , the frequency of the oscillating voltage should be 1.6 MHz or more (see the following formula 9).

[0051]

[Equation 9]

The present invention, on the contrary, positively utilizes the unnecessary capacitance and resistance caused by the signal line, which are unavoidably attached to the structure of a flat panel display such as a liquid crystal display.
The characteristics of the display device may be adapted to the driving according to the present invention, the design of the display device itself may be taken into consideration, or a special filter circuit element or element may be added to the signal line to have an optimum cutoff frequency. It is also possible to have a second-order low-pass filter characteristic.

The oscillating voltage output from the drive circuit to the signal line changes as shown in FIG. 47 due to the low pass filter. That is, the oscillating voltage shown in (a) becomes a voltage signal averaged as shown in (c) from the state shown in (b). Further, regarding the relationship between the gate signal and the oscillating voltage, when the gate signal is on as shown in FIG. 48B, the oscillating voltage as shown in FIG. 48A is generated.

[0054]

EXAMPLES Examples of the present invention will be described below. In the following, a matrix type liquid crystal display device will be described as an example of a display device, but the present invention is also applicable to other types of display devices.

First Embodiment FIG. 1 shows a block diagram of a display device according to the present invention. In FIG. 1, the display unit 100 has MxN arranged in M rows and N columns.
Individual picture elements P (j, i) (j = 1,2, ..., M; i = 1,2, ..., N) and switching elements T (j, i) connected to the picture elements. ) (J = 1,2, ...,
M; i = 1,2, ..., N). The source driver 101 and the gate driver 102 are drive circuits for driving the display unit 100. N signal lines Oi (i = 1,2, ..., N)
Are output terminals S of the source driver 101, respectively.
(i) (i = 1,2, ..., N) and the switching element T (j, i) are connected. The M scanning lines Lj (j = 1,2, ..., M) are output terminals G (j) (j = 1,2 ,.
.., M) and the switching element T (j, i) are connected. The switching element T (j, i) is a thin film transistor (T
FT; thin film transistor) can be used. Also, other switching elements may be used. In the description below, the switching element is a thin film transistor, so the signal line Oi is connected to the source line Oi.
The scanning line Lj is referred to as a gate line Lj.

Output terminal G (j) of the gate driver 102
To the gate line Lj, a voltage whose voltage level is high is sequentially output during a certain specific period. Hereinafter, the specific period is defined as one horizontal period jH (j = 1,2, ...,
M). Also, one horizontal period jH for j = 1, 2, ..., M
The period obtained by adding all the lengths of is called a vertical period.

When the voltage level of the voltage output from the output terminal G (j) to the gate line Lj is high level, the switching element T (j, i) is turned on. When the switching element T (j, i) is in the ON state, the picture element P (j, i) is charged according to the voltage output from the output terminal S (i) of the source driver 101 to the source line Oi. It The voltage level of the charged voltage is maintained at a constant voltage level during the one vertical period, and the voltage of the voltage level is applied to the pixel.

FIG. 2 shows the relationship between the digital video data DA, the sampling pulse Tsmpi, and the output pulse signal OE in the j-th one horizontal period jH defined by the horizontal synchronizing signal Hsym. As shown in FIG. 2, sampling pulses Tsmp1, Tsmp2, ... Tsmpi ,.
By applying TsmpN to the source driver 101, digital video data DA ₁ , DA ₂ , ... DA _i ,
· · · DA _N are respectively incorporated in the source driver 101. The source driver 101 uses the j-th pulse signal OEj (j = 1, 1, which is defined by the output pulse signal OE).
2, ..., M) is applied, the voltage is output from the output terminal S (i) in response to this.

FIG. 3 shows the horizontal synchronizing signal Hsym, the digital video data DA, the output pulse signal OE, the output timing of the source driver, and the gate in one vertical period defined by the vertical synchronizing signal Vsym. The relationship with the driver output timing is shown. In FIG. 3, SOURCE (j) indicates the voltage level of the voltage output at the timing shown in FIG. 2 according to the digital video data given in one horizontal period jH. Where the SOURCE
(j) is hatched to collectively represent the voltage levels of the voltages output from the N output terminals of the source driver 101. While the SOURCE (j) is output to the source line Oi, the jth output terminal G (j) of the gate driver
The voltage level of the voltage output from becomes high level,
All N switching elements T (j, i) (i = 1,2, ..., N) connected to the j-th gate line Lj are turned on. As a result, the picture element P (j, i) is charged according to the voltage output to the source line Oi. By repeating the above M times for each j = 1, 2, ..., M, the image in one vertical period (in the case of non-interlace, this image becomes one screen) is displayed. To be done.

Thereafter, after the j-th pulse signal OEj is given to the output pulse signal OE, the next pulse signal O
The period until Ej + 1 is given is defined as one output period. One output period is SOURCE (j) (j = 1,2, ...
・, M) Match each period.

FIG. 4 shows that in addition to the timing of each signal shown in FIGS. 2 and 3, the picture element P (j, i) corresponds to the timing.
Indicates the voltage level of the voltage applied to (j = 1,2, ..., M).

FIG. 5 shows an example of the waveform of the voltage signal output to the source line Oi in one output period by the driving method of the present invention. Conventionally, the voltage level of the voltage signal output to the source line Oi was constant during one output period (FIG. 46). On the other hand, in the present invention, the voltage signal output to the source line Oi has a vibration component that vibrates during one output period.

FIG. 8 shows four values corresponding to 2-bit data values.
It is a circuit diagram for one output of a source driver in a drive circuit when a level voltage is applied.

In FIG. 8, the operations of the sampling flip-flop M _SMP , the hold flip-flop M _H , and the decoder DEC, the image signal T _SMPn , the output pulse OE, and the outputs Y _{0 to} Y ₃ of the decoder DEC are shown in FIG. 17 as in the conventional circuit.

On the output side of the decoder DEC, an inverter 801, AND circuits 802 and 803, and 4-input O are provided.
An R circuit 804 is provided. The output Y _{0 of the} decoder DEC is connected to the input of the OR circuit 804 via the inverter 801. Decoder DEC outputs Y ₂ and Y ₃
Are respectively connected to one inputs of AND circuits 802 and 803. The outputs of the AND circuits 802 and 803 are connected to the input of the OR circuit 804. Decoder DE
The output Y ₄ of C is directly connected to the input of the OR circuit 804. The OR circuit 804 outputs the output of the voltage value V _D if any one of its inputs is “1”, and the output thereof becomes the ground level V _GND if all of the inputs are “0”. . The output of the OR circuit 804 is connected to the _nth source line O _n , and the OR circuit 804 is configured to be able to sufficiently drive the load on the source line O _n . To the other inputs of the AND circuits 802 and 803,
Signals TM ₁ and TM _{2 which} will be described later are provided respectively.

The waveforms of the signals TM ₁ and TM ₂ are shown in FIG.
Further, FIG. 10 shows an enlarged portion of the signal TM ₁ . The signals TM ₁ and TM ₂ are rectangular wave pulse signals in which periods of “1” and periods of “0” alternately appear. Signal T
In M ₁ , the ratio between the “1” period and the “0” period of the pulse, that is, the duty ratio n: m is 1: 2. Further, in the signal TM ₂ , the duty ratio n: m is set to 2: 1.

When image signal data (D ₁ , D ₀ ) = (0, 0) is input to such a source driver, the output Y _{0 of the} decoder DEC becomes “1” and the other output Y ₁ ,
Y ₂ and Y ₃ are “0”. Therefore, the inputs of the OR circuit 804 are all "0", and the output thereof is V _GND as shown in FIG.

Image signal data (D ₁ , D ₀ ) = (0, 1)
Is input, the output Y _{1 of the} decoder DEC becomes “1” and the other outputs Y ₀ , Y ₂ and Y ₃ become “0”. Therefore, one of the inputs of the OR circuit 804 becomes "1" in the same cycle as the signal TM ₁ . Therefore, the output of the OR circuit 804 has a pulse waveform that oscillates between V _D and V _GND at the same duty ratio as the duty ratio (n: m = 1: 2) of the signal TM ₁ ((( b)).

Image signal data (D ₁ , D ₀ ) =
When (1, 0) is input, the output Y _{2 of the} decoder DEC
There "1", the other output Y _0, Y ₁ and Y ₃ is "0". Therefore, one of the inputs of the OR circuit 804 is the signal TM.
It becomes "1" in the same cycle as ₂ . Therefore, the OR circuit 80
The output of 4, the duty ratio of the signal TM ₂ (n: m =
The pulse waveform oscillates between V _D and V _GND with the same duty ratio as (2: 1) ((c) of FIG. 11).

Image signal data (D ₁ , D ₀ ) = (1, 1)
Is input, the output Y _{3 of the} decoder DEC becomes “1” and the other outputs Y ₀ , Y ₁ and Y ₂ become “0”. Therefore, the output of the OR circuit 804 becomes V _D as shown in FIG.

The image signal data (D ₁ , D ₀ ) is (0, 1)
Alternatively, in the case of (1, 0), the average voltage value of the output of the OR circuit 804, that is, the average value of the voltage applied to the source line O _n is

[0072]

[Equation 10]

It is represented by

When the ground level V _GND is 0 V, the _equation 10 is

[0075]

[Equation 11]

It becomes

As described above, the duty ratio n: m of the signal TM ₁ is 1: 2, and the duty ratio n: m of the signal TM ₂ is:
Since m is set to 2: 1, image signal data (D
The average voltage of the output of the OR circuit 804 when ( ₁ , D ₀ ) is (0, 1) is (1/3) V _D , and the image signal data (D ₁ , D
_{When 0} ) is (1,0), the average voltage is (2/3) V _D.

From the above, it is necessary that the frequencies of the signals TM ₁ and TM ₂ are sufficiently higher than the cutoff frequency of the low-pass filter of the source line itself, and the driving capability of the OR circuit 804 is sufficient to drive the source line. For example, the voltage applied to the point A of the source line, that is, the pixel is (D ₁ , D ₀ ) =
0 when (0,0), (1/3) V _D when (D1, D0) = (0,1), and (2 when (D ₁ , D ₀ ) = (1,0) / 3) When V _D , (D ₁ , D ₀ ) = (1, 1), it becomes V _D. Therefore, the voltage level corresponding to the digital data is applied to the picture element.

Second Embodiment FIG. 12 shows a second embodiment. In this embodiment, the outputs Y _{0 to} Y ₃ of the decoder DEC are AND circuits 1201 respectively.
~ 1204 is one of the inputs. AND circuit 12
Signals TM _{0 to} TM ₃ are input to the other inputs of 01 to 1204, respectively. AND circuits 1201-120
The output of 4 is input to the 4-input OR circuit 1205. The output of the OR circuit 1205 is given to the source line O _n . In this embodiment, by appropriately setting the duty ratios of the signals TM _{0 to} TM ₃ , it is possible to apply a voltage of any value between the voltage V _D and the ground level V _GND to the picture element. That is, when the signal TM ₀ to Tm respectively V ₀ ~V ₃ the average voltage value determined by the duty ratio of _3, the relationship between the image signal data (D _1, D ₀₎ and the voltage applied to the picture element following It becomes like Table 1.

[0080]

[Table 1]

As described above, according to this embodiment, four kinds of arbitrary voltages can be applied to the picture element.

A vibration signal is generated by appropriately combining two or more signals having different duty ratios according to the image signal data, and the vibration signal is superimposed on a single or a plurality of DC voltage levels, or the vibration signal is generated. It is also possible to selectively output those DC voltages. In this case, it is possible to realize gradation display of more levels by using a small number of DC voltage levels.

Both the present embodiment and the conventional example of FIG. 17 have the same circuit when viewed from the picture element to which the voltage is supplied. However, comparing the two, the analog switch used in the conventional example and the voltage source V ₀ supplied from the outside are used.
~ V ₃ is unnecessary in this embodiment. In this embodiment, four AND circuits 1201 to 120 are used instead of them.
4 and an OR circuit 1205 are provided. All of these circuits are basically logic circuits. Further, in this embodiment, a signal generation circuit (not shown) for generating the signals TM _{0 to} TM ₃ is required, but such a circuit can be easily realized inside the LSI, and the description thereof will be omitted. .

Third Embodiment FIG. 20 shows the configuration of one output section of the drive circuit in one embodiment of the present invention. In this embodiment, the image signal data is 3 bits for simplicity. In addition, in the following description, the number in "" indicates a decimal number, and the number in "" indicates a binary number.

The operations of the sampling memory M _SMP and the hold memory M _H shown in FIG. 20 are similar to those shown in FIG. That is, the image signal data D ₀ , D ₁ and D
₂ is taken into the sampling memory M _SMP at the rise of the sampling pulse T _SMPn and transferred to the hold memory M _H at the rise of the output pulse OE. In this embodiment, the outputs of the hold memory M _H are connected to the inputs d ₀ , d ₁ and d ₂ of the selection control circuit SCOL. A clock pulse signal t is also input to the selection control circuit SCOL. The selection control circuit SCOL outputs five outputs S ₀ , S ₂ , S ₄ , S ₆ , and S ₈ , which are analog switches ASW ₀ , ASW ₂ , ASW ₄ , ASW ₆ , and ASW, respectively.
It is a control signal for SW ₈ . Further, at the input terminal of each analog SW, five voltages V ₀ , V ₂ , V ₄ , V ₆ and V ₈ (V ₀ <V ₂ <V ₄ <V ₆ <V ₈ ) having different levels are provided.
Alternatively, V ₈ <V ₆ <V ₄ <V ₂ <V ₀ ) is supplied from the outside. Such a device for supplying a plurality of types of voltage is well known, and therefore, illustration and description thereof will be omitted. Table 2 below shows the relationship between the inputs and outputs of the selection control circuit SCOL. It should be noted that the blank portion in Table 2 indicates 0.
Further, “t” in Table 2 is “1” when the signal t is “1” and “0” when the signal t is “0”, and “t bar” is the signal t.
Is "0" when the signal is "1", and "1" when the signal t is "0".

[0086]

[Table 2]

The operation of the selection control circuit SCOL will be described with reference to Table 2.

When the value of the image signal data is "0",
The output S ₀ of the selection control circuit SCOL is selected and the first analog switch ASW ₀ is turned on. Therefore, the voltage V ₀ is output to the source line On. When the value of the image signal data is “2”, the output S ₂ of the selection control circuit SCOL is selected and the second analog switch ASW ₂ is turned on. Therefore, the voltage V ₂ is output to the source line On. Similarly, when the value of the image signal data is “4”, the output S ₄ of the selection control circuit SCOL is selected, the third analog switch ASW ₄ is turned on, and the voltage V ₄ is output to the source line On. , When the value of the image signal data is “6”, the output S _{6 of the} selection control circuit SCOL
Is selected and the fourth analog switch ASW ₆ is turned on.
However, the voltage V ₆ is output to the source line On.

Further, when the value of the image signal data is "1", the signal t is directly output to the output S ₀ of the selection control circuit SCOL, and t bar, that is, the inverted signal of the signal t is output to the output S _2. Is output. In other words, when the signal t is “1”, the first analog switch ASW ₀ is turned on, the voltage V ₀ is output to the source line On, and when the signal t is “0”, t bar = “1”. Therefore, the _second analog switch ASW ₂ is turned on, and the voltage V ₂ is applied to the source line On.
Is output. Since the signal t is a clock pulse signal as described above, the voltage output from the drive circuit to the source line On is the voltage V ₀ and the voltage V ₀ at the same cycle as the clock pulse of the signal t as shown in FIG. the oscillating voltage which oscillates between _two. In FIG. 21, the duty of the signal t is 5
When it is 0% (that is, when the period of the voltage V ₀ is the same as the period of the voltage V ₂ ), the source line On from the driving circuit.
It shows the oscillating voltage output to.

Similarly, when the value of the image signal data is "3", the second analog switch ASW ₂ and the third analog switch ASW ₄ are alternately turned on, and the voltage V ₂ and the voltage V
_When a voltage oscillating between ₄ is output and the value of the image signal data is “5”, the third analog switch ASW ₄ and the fourth analog switch ASW ₆ are alternately turned on, and the voltage V ₄ and the voltage V ₄ When a voltage oscillating between V ₆ is output and the value of the image signal data is “7”, the fourth analog switch ASW ₆ and the fifth analog switch ASW ₈ are alternately turned on, and the voltage V ₆ A voltage that oscillates between the voltages V ₈ is output.

The output terminal of the drive circuit of FIG. 20 is connected to the source line On of the TFT liquid crystal panel. Next, the case where the oscillating voltage shown in FIG. 21 is output to the source line On will be described.

FIG. 22 shows an equivalent circuit when the above driving circuit is connected to the TFT liquid crystal panel. In FIG. 22, R
_ASW is the ON resistance of the analog switch, r _CONCT is the connection resistance between the drive circuit and the source line of the liquid crystal panel, and r and c are the resistance and capacitance existing as distributed constants in the source line of the liquid crystal panel, respectively. is there. Also, V
_COM has a counter voltage applied to a counter electrode (not shown) of the liquid crystal panel.

Now, consider the load seen from the output terminal portion (indicated by A in FIG. 22) of the drive circuit. In this case, the distribution constant can be considered by replacing it with the lumped constants r _ST and C. FIG. 23 shows an equivalent circuit in which the equivalent circuit of FIG. 22 is replaced with a lumped constant.

The time constant of the scanning line of the liquid crystal panel which is usually observed is a value as this lumped constant. Where R _ASW +
If r _CONCT + r _{ST is represented} by one resistor R, the equivalent circuit shown in FIG. 24 can be obtained. The equivalent circuit shown in FIG. 24 is considered as an equivalent circuit of the load of the one output section of the drive circuit.

The capacitance C of the picture element shown by the broken line in FIG.
_LC has a much smaller value than the capacitance C, and the capacitance C _LC of the picture element can be ignored from the operation of the equivalent circuit. Therefore, it can be considered that the pixel is charged to the same potential as the potential at the point B in FIG.

Here, the voltage Vin input to the circuit of FIG. 24 when the image signal data is "1" (that is, the oscillating voltage output from the drive circuit to the source line On (FIG. 21)).
think of. The oscillating voltage shown in FIG. 21 is shown again in FIG. 25 together with the coordinate axes. In FIG. 25, the time axis τ is normalized so that the cycle of the oscillating voltage is 2π.

By the way, in general, a function f (x) having a period of 2π
Is represented by a Fourier series such as the following Expression 12 under the condition that integration is possible.

[0098]

[Equation 12]

It is clear that the voltage waveform that actually exists can be integrated, and the voltage v (τ) shown in FIG.
Is an odd function, the voltage v (τ) can be expressed by the following Expression 13.

[0100]

[Equation 13]

[0101] Here, a _0/2 is

[0102]

[Equation 14]

It is represented by Equation 14 is the voltage v (τ)
Represents the average value of (V ₀ + V ₂ ) in FIG.
/ 2, that is, an intermediate voltage between the voltage V ₀ and the voltage V ₂ .

From the above, the voltage v (τ) is a voltage in which (V ₀ + V ₂ ) / 2 as a direct current component and the fundamental frequency component of the period 2π and its harmonic components are infinitely superposed. I understand.

Therefore, if the voltage v (τ) is passed through an appropriate low-pass filter to suppress the periodic component to a necessary and sufficient level, a DC component (V ₀ +
It is clear that V ₂ ) / 2 is obtained.

By the way, as is apparent from FIG. 24, the load of the voltage v (τ) is a first-order low-pass filter. That is, the voltage at the point B in FIG. 24 is the output of the low pass filter composed of the resistor R and the capacitor C. Therefore, by giving the selection control circuit SCOL a signal t having a frequency equal to or higher than a certain frequency determined by the characteristics of the first-order low-pass filter determined by the values of the resistor R and the capacitance C, practically sufficient ( It is possible to apply a voltage close to V ₀ + V ₂ ) / 2 to the picture element. The same applies when the image signal data is "3", "5", or "7".

Next, consider the relationship between the time constant determined by the values of the resistance R and the capacitance C and the cycle of the oscillating voltage. The transfer function T (jw) between the input and the point B in FIG. 24 is

[0108]

[Equation 15]

[0109]

[Equation 16]

[0110]

[Equation 17]

Here, ω / ω ₀ is the normalized frequency.

The amplitude characteristic | T | of this transfer function is

[0113]

[Equation 18]

It becomes From this, if the relationship between the amplitude and the normalized frequency is expressed in dB,

[0115]

[Formula 19]

As a result, the amplitude characteristic of FIG. 18 is obtained. From FIG. 18, for example, when ω / ω ₀ = 10,
It can be seen that the amplitude appearing at point B of 4 is 1/10.

In the present invention, how to determine the value of ω / ω ₀ cannot be unconditionally determined. It's the adjacent original 2
It depends on the voltage difference ΔV (ΔV = | V _n −V _{n + 1} |) and the required display quality. For example, if ΔV = 1V and an error of up to 0.1V is recognized in the required display quality, the value of ω / ω ₀ = 10 described above is sufficient.

In this case, it is understood that if CR = 5 × 10 ⁻⁶ , the frequency of the oscillating voltage should be 320 kHz or more. In an actual panel, the CR value is, for example, 5-10.
It is a value such as × 10 ^-6 . Also, one output period is 30 μs when used as a display device of a computer, for example.
It is a value of about ec. In this case, if an oscillating voltage of 320 kHz is applied, one oscillating voltage period is included in one output period. The upper limit of the frequency of the signal t is theoretically not limited, but in reality, the analog switch ASW ₀ ~.
Limited by the characteristics of ASW ₈ .

The frequency of the signal t is 100 kHz to 25 MH.
Experiments were conducted to drive an actual liquid crystal panel as various values in the range of z. However, as compared with the case where a voltage whose level is (V _n + V _{n + 1} ) / 2 is directly applied to the scanning line, V _n , V _{n + 1}
There was no difference in display quality depending on the conditions such as the voltage.

As is apparent from the above, the permissible range of the frequency of the oscillating voltage in the present invention is extremely wide.

The values of the resistance R and the capacitance C in FIG. 24 vary depending on the liquid crystal panel. In addition, actually, among the picture elements arranged on the source line, the output terminal portion A
For those near and far (Fig. 22), see Fig. 24.
In some cases, the values of the resistance R and the capacitance C in the equivalent circuit must be different from each other. However, as described above, in the present invention, the allowable range of the frequency is extremely large. Therefore, by giving the smallest value as the value of the resistance R and the capacity C in the equivalent circuit, variations due to the liquid crystal panel and the scanning line All variations due to the position of can be absorbed.

FIG. 26 shows the configuration of the selection control circuit SCOL shown in FIG. The circuit of FIG. 26 is obtained by obtaining the following formula from the logic table of Table 2 and expanding the formula into a logic circuit.

[0123]

[Equation 20]

Fourth Embodiment FIG. 27 and FIG. 28 are circuit diagrams of a drive circuit in another embodiment and a selection control circuit SCOL used in that embodiment, respectively. In this embodiment, the voltage V ₈ in FIG. 20 is replaced with the voltage V ₇ , and the analog switch ASW ₈ is replaced with the analog switch ASW _{7. When} the image signal data is “7”, the voltage V ₇ remains unchanged. It is supposed to be output. The logical table for this example is shown in Table 3 below. In the embodiment of FIG. 20, the voltage V ₈ does not become the pixel voltage as it is, but in the embodiment of FIG. 27, the voltage V ₇ is used as it is as an output. As an actual drive circuit, the embodiment of FIG. 27 is more rational.

[0125]

[Table 3]

Fifth Embodiment FIG. 29 shows a circuit diagram for one output in the embodiment when the image signal data is 4 bits, and FIG. 29 shows the selection control circuit SCO.
The logical table of L is shown in Table 4 below.

[0127]

[Table 4]

In this example, as shown in Table 5 below,
A display level of 16 gradations can be obtained from 9 levels of voltage.

[0129]

[Table 5]

Sixth Embodiment FIG. 30 shows a circuit diagram for one output of the source driver when the image signal data is 6 bits. In FIG. 30, the selection control circuit SCOL is supplied with signals having four different duty ratios t ₁ , t ₂ , t ₃ , and t ₄ . FIG. 31 shows the waveforms of these four signals. Table 6 below shows a logic table of the selection control circuit SCOL.

[0131]

[Table 6]

When the value of the image signal data is not a multiple of 8, the oscillating voltage is output to the source line On as shown in FIG. In this way, 64
A gradation display level can be obtained.

Seventh Embodiment FIG. 33 shows a circuit diagram for one output of the source driver when the image signal data is 8 bits. In FIG. 33, the selection control circuit SCOL is supplied with signals having 16 different duty ratios t _{1 to} t ₁₆ . FIG. 34 shows the waveforms of these 16 signals. By following the logic table similar to Table 6, as shown in Table 7, a display level of 256 gradations can be obtained from the voltage of 9 levels.

[0134]

[Table 7]

Eighth Embodiment FIG. 35 shows the basic structure for one output in the drive circuit of the display device of the present invention. This circuit is provided for each bit (D3, D2, D1, D) of digital video signal data.
0) first-stage sampling memory Ms provided for each
mp, the second-stage hold memory MH, one selection control circuit SCOL to which the first clock signal t1 is externally applied, and a 5-level constant voltage V from an external voltage source.
Analog switches ASW0, ASW4, ASW8, AS to which 0, V4, V8, V12, and V16 are respectively applied
It is composed of W12 and ASW16.

The selection control circuit SCOL includes an inverter E, an AND circuit F and an OR circuit G as shown in FIG.
And the hold memory M.
Based on the signals d3, d2, d1, d0 input from H and the clock signal t1 input from the outside, a voltage determined as described later is output terminals S0, S4, S8,
Output from S12 and S16. This selection control circuit SCO
The output terminals S0, S4, S8, S12, S16 of L are connected to the analog switches ASW0, ASW4, ASW8, AS.
It is connected to the control input terminals of W12 and ASW16.
In this embodiment, the clock signal t1 has a duty ratio of 1: 1.

Table 8 shows the selection control circuit S in this embodiment.
The logical table of COL is shown.

[0138]

[Table 8]

In Table 8, the left column is a decimal display, the center column is the data d0, d1, d2, d3 input to the selection control circuit SCOL, and the right column is the output terminal S.
0, S4, S8, S12, S16. The output signal t1 becomes 1 when the clock signal t1 is 1 and becomes 0 when the clock signal t1 is 0. The analog switches ASW0 and ASW of FIG.
4, ASW8, ASW12, and ASW16 are turned on when the input signal is 1.

FIG. 36 shows an example in which the selection control circuit SCOL is developed into an actual circuit based on Table 8. This is shown in Table 8
Based on the above, the following logical expression is obtained, and the circuit configuration is satisfied.

[0141]

[Equation 21]

Although the circuit of FIG. 36 is not particularly minimized, in the actual LSI design, this selection control circuit SCOL requires only the number of outputs, and the total number becomes enormous. Therefore, the circuit of the selection control circuit SCOL needs to be minimized as much as possible.

In the above description, the clock signal t1 has been described as being input from the outside, but of course it may be produced anywhere as long as the same clock signal can be obtained. However, manufacturing in the selection control circuit SCOL is a huge waste because the number of selection control circuits SCOL is large. In that sense, L that constitutes the drive circuit
Each selection control circuit SCOL is made at somewhere in SI.
It is desirable to supply to. The original clock for producing the clock signal t1 may be used by appropriately dividing the sampling clock or the like originally supplied to the drive circuit, or may be supplied from the outside. When supplied from the outside, the cycle of the oscillating voltage can be adjusted arbitrarily, so that the number of input terminals of the LSI increases by one, but the advantage is also large.

In the drive circuit having such a configuration, the outputs shown in the right column of Table 8 are obtained. That is, data expressed in decimal is 0 (d0 = d1 = d2 = d3 = 0), 4 (d0 = d
1 = d3 = 0, d2 = 1), 8 (d0 = d1 = d2 =
1, d3 = 0), 12 (d0 = d1 = 0, d2 = d3 =
In the case of 1), the output terminals S0, S4, S8, S
Only 12 becomes active, and the voltages V0, V4, V8, and V12 supplied to them are output as they are.

Further, the data is 2 (d1 = 1, d0 = d2
= D3 = 0), 6 (d0 = d3 = 0, d1 = d2 =
1), 10 (d0 = d2 = 0, d1 = d3 = 1), 14
When (d0 = 0, d1 = d2 = d3 = 1), according to the logic table, the output terminals S0 and S4 of the selection control circuit SCOL,
S4 and S8, S8 and S12, S12 and S16 are 1 at the same time
Becomes At this time, for example, the equivalent circuit from the output terminals S4 and S8 of the selection control circuit SCOL to the output terminal of the drive circuit is the resistance r of the analog switches ASW4 and ASW8.
If they are equal, the result is as shown in FIG. Therefore, when S4 and S8 are 1 at the same time, it can be seen that the output voltage when there is no load is (V4 + V8) / 2. This means that if S0 and S4 are 1 at the same time, and if S8 and S4
The same applies when 12, S12 and S16 simultaneously become 1, and the output voltage in each case is (V0 + V4) /
2, (V8 + V12) / 2, (V12 + V16) / 2.

Further, the data is 1 (d0 = 1, d1 = d2
= D3 = 0), 5 (d0 = d2 = 1, d1 = d3 =
0), 9 (d0 = d3 = 1, d1 = d2 = 0), 13
When (d1 = 0, d0 = d2 = d3 = 1), the output terminals S0 and S4, S4 and S8, S8 and S1 follow the logic table.
2, one of S12 and S16 becomes 1, and the other switches to 0 and 1 based on the clock signal t1. That is, there are times when both become 1 at the same time and times when only one becomes 0. The timing of switching to 0 and 1 based on the clock signal t1 needs to be switched at least once during one output period.

For example, when the case where the data is 5 will be described as an example, the output voltage when there is no load is the output terminals S4 and S4.
When 8 are 1 at the same time, it becomes (V4 + V8) / 2, while in this example, when only the output terminal S8 is 0, V4
Becomes Therefore, as shown in FIG. 38, V4 and (V4
An oscillating voltage reciprocating between + V8) / 2 is obtained. At this time, since the source line constituting the display device connected to the output terminal functions as a first-order low-pass filter composed of the resistor R and the capacitor C as described above, the oscillating voltage is averaged. It As a result, the voltage at point B in FIG. 39, which is the circuit configuration in which the load of the source line is connected to FIG. 37, is {V4 + (V4 + V8) / 2} / 2 =
(3V4 + V8) / 4.

This is also the case when the data is 1, 9, and 13, and the output voltage in each case is (3V0
+ V4) / 4, (3V8 + V12) / 4, (3V12 +
V16) / 4.

Further, the data is 3 (d0 = d1 = 1, d2
= D3 = 0), 7 (d0 = d1 = d2 = 1, d3 =
0), 11 (d0 = d1 = d3 = 1, d2 = 0), 15
When (d0 = d1 = d2 = d3 = 1), according to the logic table, the output terminals S0 and S4, S4 and S8, S8 and S12,
One of S12 and S16 becomes 1 and the other switches to 0 and 1 based on the clock signal t1. That is, also in this case, there is a time when both are 1 at the same time and a time when only one is 0. The timing of switching to 0 and 1 based on the clock signal t1 needs to be switched at least once during one output period.

For example, in the case where the data is 7, the output voltage when there is no load is the output terminals S4 and S4.
When 8 is 1 at the same time, it becomes (V4 + V8) / 2, while in this example, when only the output terminal S4 is 0, V8
Becomes Therefore, an oscillating voltage reciprocating between V8 and (V4 + V8) / 2 is obtained. At this time, since the source line functions as a first-order low-pass filter as described above, the oscillating voltage is averaged, whereby the oscillating voltage is averaged.
The voltage at point B of 9 is {V8 + (V4 + V8) /
2} / 2 = (V4 + 3V8) / 4.

The same applies to the case where the data is 3, 11, and 15, and the output voltage in each case is (V0
+ 3V4) / 4, (V8 + 3V12) / 4, (V12 +
3V16) / 4.

Table 9 shows the relationship between the voltage and data obtained in this example.

[0153]

[Table 9]

The left side of the right column in Table 9 shows the case of this embodiment, and the right side shows the case of FIG. 19 described later.

Therefore, according to the present invention, three gray scales are added between two gray scales when the display device is driven with the approaching two-level gray scale display voltage applied from the outside as it is. be able to. Therefore, the number of external voltage sources can be significantly reduced.

For example, in the conventional case where the data shown in FIG. 19 is 4 bits, 16 external power supplies are required. On the other hand, in the case of the present invention, two levels of gradation display voltage are used. Since three gradations can be added between the two gradations that are driven as they are, the number of external power supplies is 5 as shown in FIG. In addition, the external power supply required for 5 bits can be reduced from 32 to 9 and the external power supply required for 6 bit can be reduced from 64 to 17; Can be reduced.

Although the clock signal t1 has a duty ratio of 1: 1 in the above embodiment, the duty ratio may be changed. When changing the duty ratio, it becomes possible to change two gradation levels except the central gradation level among the three gradations added between the two gradations, which are constant in each output period. It is possible to match or approach the desired gradation.

Ninth Embodiment FIG. 40 shows the basic structure of the drive circuit of the display device of the present invention corresponding to one output. This circuit is provided for each bit (D3, D2, D1, D) of digital video signal data.
0) first-stage sampling memory Ms provided for each
mp, the second-stage hold memory MH, one selection control circuit SCOL to which the first clock signal t1 and the second clock signal t2 are externally applied, and a constant voltage of 5 levels from an external voltage source. V0, V4, V8, V12, V
16 are given to the analog switches ASW0,
It is composed of ASW4, ASW8, ASW12, and ASW16.

The selection control circuit SCOL includes an inverter E, an AND circuit F and an OR circuit G as shown in FIG.
And the hold memory M.
Based on signals d3, d2, d1 and d0 input from H and clock signals t1 and t2 input from the outside and having different duty ratios, voltages determined as described later are output terminals S0, S4, Output from S8, S12, and S16. The output terminals S0, S of the selection control circuit SCOL
4, S8, S12, S16 are analog switches AS
It is connected to the control input terminals of W0, ASW4, ASW8, ASW12, and ASW16. In this embodiment, FIG.
As shown in FIG. 3, the clock signal t1 has a duty ratio n: m of 3: 1 and the clock signal t2 has a duty ratio n: m of 1: 1.

Table 10 shows a logic table of the selection control circuit SCOL in this embodiment.

[0161]

[Table 10]

In Table 10, the left column is a decimal display, the center column is the data d0, d1, d2, d3 input to the selection control circuit SCOL, and the right column is the output terminal S.
0, S4, S8, S12, S16. The output signal t1 is 1 when the clock signal t1 is 1, and 0 when the clock signal t1 is 0. The same applies to the output signal t2. In addition, all blanks indicate 0. Figure 40
Analog switches ASW0, ASW4, ASW8, A
SW12 and ASW16 are turned on when the input signal is 1.

FIG. 41 shows the selection control circuit SCOL.
An example of expansion to an actual circuit based on is shown. This is a circuit configuration that obtains the following logical expression based on Table 10 and satisfies it.

[0164]

[Equation 22]

Although the circuit of FIG. 41 is not particularly minimized, in the actual LSI design, this selection control circuit SCOL requires only the number of outputs, and the total number becomes enormous. Therefore, the circuit of the selection control circuit SCOL needs to be minimized as much as possible.

Further, in the above description, the clock signals t1 and t2 have been described as being input from the outside, but of course they may be produced anywhere as long as the same clock signal is obtained. However, manufacturing in the selection control circuit SCOL is a huge waste because the number of selection control circuits SCOL is large. In that sense, each selection control circuit S is manufactured at somewhere in the LSI that constitutes the drive circuit.
It is desirable to supply to COL. The original clocks for producing the clock signals t1 and t2 may be used by appropriately dividing the sampling clock or the like originally supplied to the drive circuit, or may be supplied from the outside. When supplied from the outside, the cycle of the oscillating voltage can be adjusted arbitrarily, so that the number of input terminals of the LSI increases by one, but the advantage is also large.

In the drive circuit having such a configuration, Table 10
The output shown in the right column of is obtained. That is, when the data expressed in decimal is 0, 4, 8, and 12, the output terminal S
Only 0, S4, S8, and S12 are activated, and the voltages V0, V4, V8, and V12 supplied to them are output as they are.

Also, if the data is 2, 6, 10, 14 (4n
+2, where n = 0, 1, 2, 3), it is based on the clock signal t2. For example, when the data is 2, the output terminals S0 and S4 are controlled to be turned on / off based on the clock signal t2, but when one output terminal S0 is turned on, the other output terminal S4 is turned off, When one output terminal S0 is off, the other output terminal S4 is on. At this time, since the duty ratio n: m of the clock signal t2 is 1: 1, the analog switch ASW0
Is on and the analog switch ASW4 is off, and then the analog switch AS
W0 is turned off and the analog switch ASW4 is turned on repeatedly. As a result, as shown in FIG. 43A, the voltages V4n and V4n are applied to the source line On at the same time.
An oscillating voltage that reciprocates between 4n + 4 (both n = 0) at a time ratio of 1: 1 is applied. Therefore, in the picture element of the display device connected to the source line On, a voltage (V0 + V) having a value obtained by averaging the oscillating voltage through the low pass filter including the resistance and the capacitance of the source line On described above.
4) / 2 is given.

This is the same when the data is 6, 10, and 14, and the voltage applied to the picture element is (V
4 + V8) / 2, (V8 + V12) / 2, (V12 + V
16) / 2. That is, the data is 4n + 2 (n =
In the case of 0, 1, 2, 3), the voltage applied to the picture element is 1/2 of the sum of V4n and V4n + 4.

Further, the data is 1, 5, 9, 13 (4n +
1, but when n = 0, 1, 2, 3), the clock signal t
It is based on 1. For example, when the data is 1,
The output terminals S0 and S4 are controlled to be turned on / off based on the clock signal t1, but when one output terminal S0 is turned on, the other output terminal S4 is turned off and one output terminal S0 is turned off. At this time, the other output terminal S4 is turned on. At this time, the clock signal t1 has a duty ratio n:
Since m is 3: 1, after the analog switch ASW0 is on and the analog switch ASW4 is off, the analog switch ASW0 is off and the analog switch ASW4 is on for a time corresponding to 1/3 of that state. Repeatedly become the state of. As a result, the voltage V4n is applied to the source line On as shown in FIG.
And V4n + 4 (both n = 0), the former is 3/4,
An oscillating voltage is applied which causes the latter to reciprocate at a time ratio of 1/4. Therefore, the picture element of the display device connected to the source line On is given a voltage (3V0 + V4) / 4 of a value obtained by averaging the oscillating voltage through the low pass filter.

The same applies to the case where the data is 5, 9, and 13, and the output voltage in each case is (3V4 +
V8) / 4, (3V8 + V12) / 4, (3V12 + V
16) / 4. That is, the data is 4n + 1 (n =
In the case of 0, 1, 2, 3), the voltage applied to the picture element is 1/4 of the sum of 3V4n and V4n + 4.

The data is 3, 7, 11, 15 (4n + 3,
However, when n = 0, 1, 2, 3), it is based on the clock signal t1. For example, when the data is 3, the output terminals S0 and S4 are turned on based on the clock signal t1.
Although controlled to be off, when one output terminal S0 is on, the other output terminal S4 is off, and when one output terminal S0 is off, the other output terminal S4 is on.
At this time, since the duty ratio n: m of the clock signal t1 is 3: 1, the analog switch ASW0 is turned on,
After the analog switch ASW4 is off,
The analog switch ASW0 is turned off and the analog switch ASW4 is turned on for a time corresponding to three times that state. As a result, as shown in FIG. 43 (c), the voltages V4n and V4n
An oscillating voltage that reciprocates between 4n + 4 (both n = 0) at a time ratio of 1/4 for the former and 3/4 for the latter is applied. Therefore, a voltage (V0 + 3V4) / 4 of a value obtained by averaging the oscillating voltage through the low pass filter is applied to the picture element of the display device connected to the source line On.

This is also the case when the data is 7, 11, and 15, and the output voltage in each case is (V4 +
3V8) / 4, (V8 + 3V12) / 4, (V12 + 3
V16) / 4. That is, the data is 4n + 3 (n =
In the case of 0, 1, 2, 3), the voltage applied to the picture element is ¼ of the sum of V4n and 3V4n + 4.

Table 11 shows the relationship between the voltage and data obtained by this example.

[0175]

[Table 11]

The left side of the right column in Table 11 shows the case of this embodiment, and the right side shows the case of FIG. 19 described later.

Therefore, according to the present invention, three gradations are added between two gradations when the display device is driven with the approaching gradation display voltages of two levels applied from the outside. be able to. Therefore, the number of external voltage sources can be significantly reduced.

For example, in the conventional case where the data shown in FIG. 19 is 4 bits, 16 external power supplies are required. On the contrary, in the case of the present invention, two levels of gradation display voltage are used. Since three gradations can be added between the two gradations that are driven as they are, the number of external power supplies is 5 as shown in FIG.

Tenth Embodiment FIG. 61 shows an example of voltages V0 to V7 for realizing visually correct 8 gradations in a TFT type liquid crystal panel.
There is a linear characteristic between V1 and V6. Therefore, also in the drive circuit of the fourth embodiment, voltages of accurate gradation can be obtained for V3 and V5. For V7,
Since it is given independently, it can also be adjusted to the correct voltage. However, V1 is a problem. In other words, since there is a non-linear characteristic between V1 and V0, when V0 and V2 are adjusted to an accurate gradation, a voltage difference of ΔV1 occurs at V1 as shown in the figure. Conversely, V
If V0 is matched so that 2 and V1 are accurate, a voltage difference of ΔV0 will occur with respect to V0, as shown in the figure.
That is, one of V1 and V0 has to be shifted from the accurate gray scale, and the above-mentioned difference occurs.

A drive circuit of a display device capable of obtaining an accurate gradation by the oscillating voltage average value driving method even in the above-mentioned non-linear characteristic part will be described below.

FIG. 49 shows a basic structure corresponding to one output in the drive circuit of the display device of the present invention. This circuit is for each bit (D2, D
1, D0), the first-stage sampling memory Msmp, the second-stage hold memory MH, the first clock signal t1 and the second clock signal t2 from the outside.
And a constant voltage V0, V2, V4, V of five levels from an external voltage source.
Analog switch ASW to which 6 and V7 are applied respectively
0, ASW2, ASW4, ASW6, ASW7. In addition, each analog switch ASW0, AS
The control input terminals of W2, ASW4, ASW6, and ASW7 are the output terminals S0, S2, S of the selection control circuit SCOL.
4, S6, S7 are connected. Incidentally, FIG. 48B shows a gate signal. FIG. 48A shows an example of the waveform of the video signal applied to the pixel electrode when the gate signal is ON.

In this embodiment, the selection control circuit SCOL has the first clock signal t with a duty ratio of 1: 1.
In addition to 1, the second clock signal t2 is supplied.
This second clock signal t2 is used to generate the voltage V1.

FIG. 50A shows the second clock signal t2.
And (b) shows the waveform of the output V1 produced based on the signal t2. In the case of the present embodiment, the duty ratio n: m of the second clock signal t2 is 1: 2. Therefore, the oscillating voltage waveform of V1 is also output so that V0: V2 becomes 1: 2. In this case, the average voltage is (V0
Since it is + 2V2) / 3, it is possible to set the voltage applied to the picture element to a value itself that exactly provides the original gradation.

That is, in the case of the present embodiment, it is possible to give an accurate gradation even in the non-linear characteristic portion of the picture element by the oscillating voltage average value driving method.

Table 12 shows a logic table of the selection control circuit SCOL in this embodiment.

[0186]

[Table 12]

In Table 12, d0, d1 and d2 are data input to the selection control circuit SCOL, and are S0 to S7.
Is the output. Further, in Table 12, t1 in the table
Indicates that the clock signal t1 becomes 1 when the clock signal t1 is 1, and becomes 0 when the clock signal t1 is 0, and the bar t in the table indicates the opposite. The same applies to t2 and bar t2 in the table. The analog switch AS of FIG.
It is assumed that W0 to ASW7 are turned on when their control inputs S0 to S7 are 1.

FIG. 51 shows the selection control circuit SCOL.
An example of development into an actual circuit based on 2 will be shown. this is,
The following logical expression is obtained based on Table 12, and the circuit configuration is satisfied. This circuit is an inverter D
And an AND circuit E and an OR circuit F.

[0189]

[Equation 23]

The circuit of FIG. 51 is not particularly minimized, but in actual LSI design, this selection control circuit SCOL requires only the number of outputs, and the total number becomes enormous. Therefore, the circuit of the selection control circuit SCOL needs to be minimized as much as possible.

In the above description, the first and second clock signals t1 and t2 have been described as being input from the outside, but of course, if the same clock signal is obtained, it can be produced anywhere. Good. However, the selection control circuit SC
Fabrication in the OL is a huge waste because of the large number of selection control circuits SCOL. In that sense, it is desirable that the drive circuit is manufactured at one place somewhere in the LSI and supplied to each selection control circuit SCOL. Also,
The original clock for producing the first and second clock signals t1 and t2 may be used by appropriately dividing the sampling clock or the like originally supplied to the driving circuit, or may be supplied from the outside. Good. When supplied from the outside, the oscillating voltage cycle can be adjusted arbitrarily, so LS
Although there is a disadvantage that the number of I input terminals increases by one, the advantage is also large.

Although the second clock signal t2 has a duty ratio n: m of 1: 2 in the above embodiment, the duty ratio n: m is used when a desired gradation is obtained. May have a duty ratio other than 1: 1.

Eleventh Embodiment FIG. 52 is a diagram showing a drive circuit according to another embodiment of the present invention, and shows the basic structure corresponding to one output of the drive circuit. In this embodiment, the clock signal t3 having a duty ratio n: m of 1: 2 is supplied to the selection control circuit SCOL (see FIG. 53). The selection control circuit SCOL has four outputs S0, S2, S5, and S7, which are analog switches ASW0, ASW2, and ASW5, respectively.
It is an input to the control terminal of ASW7. Each analog switch ASW0, etc. is externally connected to V0, V2,
A constant voltage of V5 and V7 is supplied.

Table 13 shows the selection control circuit S in this embodiment.
The logical table of COL is shown.

[0195]

[Table 13]

In the drive circuit having such a configuration, Table 14
The output shown in the right column of is obtained.

[0197]

[Table 14]

That is, the data represented by the decimal system is 0 (d0
= D1 = d2 = 0), 2 (d0 = d2 = 0, d1 =
1), 5 (d0 = d2 = 1, d1 = 0), 7 (d0 = d
1 = d2 = 1), S0, S2, S5,
Only S7 becomes active, and the voltages V0, V2, V5, and V7 supplied to them are output as they are.

On the other hand, if the data is 1 (d0 = 1, d2 = d1
= 0), 3 (d0 = d1 = 1, d2 = 0), 4 (d0 =
d1 = 0, d2 = 1), 6 (d0 = 0, d1 = d2 =
In the case of 1), the analog switch ASW0 shown in FIG. 52 is turned on in synchronization with the clock signal t3 according to the logic table.
Repeated OFF, the oscillating voltage is output. For example, when the data is 1, the average voltage is (V0 + 2V2) / 3. The average voltage when the data is 4 is (V2 + 2V
5) / 3, and the average voltage when the data is 6 is (2V5
+ V7) / 3, and the average voltage when the data is 3 is (2
It becomes V2 + V5) / 3.

FIG. 54 shows the selection control circuit SCOL of this embodiment.
The circuit example of is shown. This selection control circuit SCOL is shown in Table 13
The following logical expression is obtained and expanded into an actual circuit.

[0201]

[Equation 24]

The circuit of FIG. 54 is not particularly minimized, but in the actual LSI design, this selection control circuit SCOL requires only the number of outputs, so the total number becomes enormous. . Therefore, it is preferable to minimize this circuit as much as possible. Therefore, this embodiment is
When applied to a liquid crystal panel having the characteristics shown in FIG.
When the voltages shown in FIG. 61 are given as the voltages of V0, V2, V5, and V7, V1, V3, V4, and V6 have the same values as V1, V3, V4, and V6 in FIG. 61, respectively. That is clear. That is, the circuit of this embodiment is
It can be seen that the same effect as the conventional drive circuit shown in FIG. 60 is obtained.

Therefore, in the case of this embodiment, the non-linear characteristic part of the picture element is compensated for the non-linearity, and in the linear part, two more gradations are realized between the original voltages. This makes it possible to further reduce the number of voltage sources that need to be supplied from the outside.

The clock signal t3 may be input from the outside or may be produced inside the LSI. However,
Manufacturing in the selection control circuit SCOL is a huge waste because the number of selection control circuits SCOL is large. In that sense, it is preferable that the drive circuit is manufactured at one place somewhere in the LSI and supplied to each selection control circuit SCOL. As the clock for producing the clock signal t3, a sampling clock or the like originally supplied to the drive circuit may be appropriately divided and used.

In the above embodiment, the clock signal t3 has a duty ratio n: m of 1: 2. However, when the desired gradation is obtained, the duty ratio n: m is 2: 1.
You may use the thing of.

Twelfth Embodiment FIG. 55 is a circuit diagram of one output of the source driver in the drive circuit when a 4-level voltage corresponding to the value of 2-bit video signal data is applied. In FIG. 55, the operations of the sampling memory Msmp, the hold memory MH, and the decoder DEC, and the sampling pulse Ts
mpn, output pulse OE, output S0 of decoder DEC
S3 is the same as that in the conventional circuit of FIG.

On the output side of the decoder DEC, an inverter 5501, AND circuits 5502 and 5503, and 4 are provided.
An input OR circuit 5504 is provided. Decoder DE
The output S0 of C is supplied to the OR circuit 5 via the inverter 5501.
It is connected to the input of 504. The outputs S1 and S2 of the decoder DEC are connected to one inputs of AND circuits 5502 and 5503, respectively. AND circuit 5502
The outputs of and 5503 are connected to the input of the OR circuit 5504. The output S3 of the decoder DEC is directly connected to the input of the OR circuit 5504. OR circuit 5504
Outputs an output of voltage value VD if any of its inputs is "1", and its output is at ground level Vgnd if all of its inputs are "0". Also,
The output of the OR circuit 5504 is the nth source line On.
The OR circuit 5504 is designed to be able to sufficiently drive the load on the source line On. AND circuit 5
The other input of 502 and 5503 has a clock signal T
4 and T5 are given respectively.

The waveforms of the clock signals T4 and T5 are shown in FIG.
Shown in (a) and (b). Further, FIG. 57 shows the signal T4 in an enlarged manner. The clock signals T4 and T5 are rectangular wave pulse signals in which periods of "1" and periods of "0" alternately appear. In the clock signal T4, the ratio between the period of "1" and the period of "0" of the pulse, that is, the duty ratio n: m is 1: 2. In the signal T5, the duty ratio n: m is set to 2: 1.

When video signal data (D1, D0) = (0, 0) is input to such a source driver, the output S0 of the decoder DEC becomes "1" and the other outputs S1, S2 and S3. Becomes "0". Therefore, the inputs of the OR circuit 5504 are all "0", and the output thereof is Vgnd as shown in FIG. 58 (a).

Image signal data (D1, D0) = (0,
When 1) is input, the output S1 of the decoder DEC becomes "1" and the other outputs S0, S2 and S3 become "0". Therefore, one of the inputs of the OR circuit 5504 is the signal T
It becomes "1" in the same cycle as 4. Therefore, the OR circuit 55
The output of 04 is the duty ratio of the clock signal T4 (n:
The pulse waveform oscillates between VD and Vgnd with the same duty ratio as (m = 1: 2) ((b) of FIG. 58).

Image signal data (D1, D0) =
When (1, 0) is input, the output S2 of the decoder DEC
Becomes "1" and the other outputs S0, S1 and S3 become "0". Therefore, one of the inputs of the OR circuit 5504 becomes "1" in the same cycle as the signal T5. Therefore, OR
The output of the circuit 5504 has the same duty ratio as the duty ratio (n: m = 2: 1) of the clock signal T5, and VD and V
It has a pulse waveform that oscillates between gnd (FIG. 58 (c)).

Image signal data (D1, D0) = (1,
When 1) is input, the output S3 of the decoder DEC becomes "1" and the other outputs S0, S1 and S2 become "0". Therefore, the output of the OR circuit 4 becomes VD as shown in FIG.

The image signal data (D1, D0) is (0,
In the case of 1) or (1,0), the average voltage value of the output of the OR circuit 5504, that is, the average value of the voltage applied to the source line is

[0214]

[Equation 25]

It is represented by

When the ground level Vgnd is set to 0V,
Number 25 is

[0217]

[Equation 26]

[0218]

As described above, since the duty ratio n: m of the clock signal T4 is set to 1: 2 and the duty ratio n: m of the clock signal T5 is set to 2: 1, the video signal data (D1, D0). ) Is (0, 1) OR circuit 55
The average voltage of the output of 04 becomes (1/3) VD, and the average voltage when the video signal data (D1, D0) is (1,0) becomes (2/3) VD.

From the above, the frequencies of the clock signals T4 and T5 are sufficiently higher than the cutoff frequency of the low-pass filter of the source line itself, and the driving capability of the OR circuit 5504 is sufficient to drive the source line On. if there is,
The point A of the source line, that is, the voltage applied to the pixel is
0 when (D1, D0) = (0,0), (D1, D
When 0) = (0,1), (1/3) VD, (D1, D
0) = (1,0), (2/3) VD, (D1, D
When 0) = (1,1), it becomes VD. Therefore, the voltage level corresponding to the digital data is applied to the picture element.

Therefore, also in this embodiment, a 4-level voltage can be produced from a 2-level constant voltage. Therefore, by selecting an appropriate value for the duty ratio of the clock signal,
It is possible to compensate for the non-linear characteristic part.

In the above embodiment, the duty ratio n: m
The clock signal T4 having a duty ratio of 1: 2 and the clock signal T5 having a duty ratio n: m of 2: 1 are used, but both duty ratios may be used.

Thirteenth Embodiment FIG. 59 shows still another embodiment. In this embodiment, the outputs S0 to S3 of the decoder DEC are AND circuits 59, respectively.
It is one of the inputs 01 to 5904. A clock signal T is input to the other inputs of the AND circuits 5901 to 5904.
6 to T9 are input respectively. AND circuit 590
The outputs of 1 to 5904 are input to the 4-input OR circuit 5905. The output of the OR circuit 5905 is the source line O
given to n.

In this embodiment, by appropriately setting the duty ratios of the signals T6 to T9, it is possible to apply a voltage of any value between the voltage VD and the ground level Vgnd to the picture element. That is, assuming that the average voltage values determined by the duty ratios of the signals T6 to T9 are V0 to V3, respectively, the relationship between the video signal data (D1, D0) and the voltage applied to the picture element is as shown in Table 15 below. Become.

[0225]

[Table 15]

As described above, according to this embodiment, four kinds of arbitrary voltages can be applied to the picture element.

Therefore, also in this embodiment, a 4-level voltage can be produced from a 2-level constant voltage. Therefore, by selecting an appropriate value for the duty ratio of the clock signal,
It is possible to compensate for the non-linear characteristic part.

In the present embodiment, a vibration signal is generated by appropriately combining two or more signals having different duty ratios according to the video signal data, and the vibration signal and a single or a plurality of DC voltage levels are generated. It is also possible to superimpose them or selectively output their DC voltage according to the vibration signal. In this case, it is possible to realize gradation display of more levels by using a small number of DC voltage levels.

Both the present embodiment and the conventional example of FIG. 17 have the same circuit when viewed from the picture element to which the voltage is supplied. However, comparing the two, the analog switch used in the conventional example and the voltage source V0 supplied from the outside are used.
~ V3 is not necessary in this embodiment. In the present embodiment, four AND circuits 5901 to 590 are used instead of them.
4 and an OR circuit 5905 are provided. All of these circuits are basically logic circuits. Further, in the present embodiment, a signal generating circuit (not shown) for generating the clock signals T6 to T9 is required, but such a circuit is LS.
It can be easily realized inside I, and its explanation is omitted.

By the way, in the above embodiments, the low-pass filter for suppressing the periodic component of the oscillating voltage is formed mainly on the basis of the resistance and capacitance of the signal line of the panel, but in the actual panel, As shown in FIG. 44, a pixel C1 and a capacitor CLC based on an auxiliary capacitor, which is one of the elements forming the pixel, and an on-resistance Rt of a switching element (TFT in this example) connecting the pixel to a signal line It is considered that the time constant based on also functions as a low-pass filter. In that sense, it is considered that the actual state has an effect as a second-order low-pass filter as shown in FIG. Further, it is considered that which of the contributions to the filter effect is greater depends on the characteristics of the panel and the position of the picture element on the panel (the distance from the output terminal of the drive circuit). In any case, what has been described as a first-order filter in the above embodiments is the most severe condition for a low-pass filter, and the actual state is more effective as a low-pass filter. You can think of it.

[0231]

According to the present invention, one or more interpolation voltages can be obtained from the voltage supplied from a given voltage source. As a result, it is possible to significantly reduce the number of voltage sources conventionally required in the configuration of the drive circuit. When the voltage source is provided outside the drive circuit, the number of input terminals of the drive circuit can be reduced, and when the drive circuit is composed of an LSI, the number of input terminals of this LSI can be reduced. Therefore, according to the conventional example, due to the increase in the number of terminals, the driving L for the multi-gradation display, which is practically impossible to realize.
It becomes possible to realize SI. Further, (1) the manufacturing cost of the display device and the drive circuit can be significantly reduced, (2)
It is possible to easily manufacture a driving circuit for multi-gradation, which could not be practically manufactured due to problems in the conventional chip size or LSI mounting. There are also merits. Thus, according to the present invention, not only the digital drive circuit of the multi-gradation display device, which has been impossible in the conventional example due to mounting problems, can be realized, but also at low cost. Therefore, the practical advantage is extremely large.

Furthermore, when the drive circuits of the first and second embodiments are used, (4) basically, only the logic level is used to apply an arbitrary voltage to the picture element. (5) Since there is no need to use the analog switch used conventionally, there is an advantage that the chip size can be significantly reduced.

When the drive circuits of the tenth to thirteenth embodiments are used, the characteristics of the picture elements are non-linear with respect to the applied voltage even when the oscillating voltage average value driving method is used. The characteristic part can be compensated, and accurate gradation display is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a display device according to the present invention.

FIG. 2 is a timing chart showing a relationship among input data, a sampling pulse, and an output pulse in one horizontal period.

FIG. 3 is a timing chart showing the relationship among input data, output pulse, output voltage, and gate pulse in one vertical period.

FIG. 4 is a timing chart showing a relationship among input data, an output pulse, an output voltage, a gate pulse, and a voltage applied to a pixel in one vertical period.

FIG. 5 is a waveform diagram showing an output voltage that oscillates during one output period.

FIG. 6 is a diagram showing a waveform example of a period 2π.

FIG. 7 is a diagram showing an equivalent circuit of a source line of a load to be driven according to the present invention.

FIG. 8 is a circuit diagram of an output portion for one source line according to the first embodiment.

FIG. 9 is a diagram showing waveforms of signals used in the first embodiment.

10 is an enlarged view of a part of the waveform of FIG.

FIG. 11 is a waveform chart showing the relationship between input data and output voltage in the first embodiment.

FIG. 12 is a circuit diagram of an output portion for one source line of a second embodiment.

FIG. 13 is a circuit diagram for explaining the operation of a conventional analog drive circuit.

FIG. 14 is a circuit diagram of an output portion for one source line of the circuit of FIG.

FIG. 15 is a signal timing diagram for explaining the operation of the circuit of FIG.

FIG. 16 is a circuit diagram for explaining the operation of a conventional digital drive circuit.

17 is a circuit diagram of an output portion for one source line of the circuit of FIG.

FIG. 18 is a diagram showing amplitude characteristics of a transfer function.

FIG. 19 is a circuit diagram of an output portion of a conventional example when 16-gradation display is performed.

FIG. 20 is a circuit diagram of an output portion for one source line in the third embodiment.

FIG. 21 is a diagram showing waveforms of signals used in the third embodiment.

FIG. 22 is an equivalent circuit diagram when the third embodiment is connected to a display panel.

23 is an equivalent circuit diagram in which the equivalent circuit of FIG. 22 is replaced with a lumped constant.

24 is an equivalent circuit diagram in which the equivalent circuit of FIG. 23 is simplified.

FIG. 25 is a diagram showing the waveform of the signal of FIG. 21 in another form.

FIG. 26 is a circuit diagram of a selection control circuit used in the third embodiment.

FIG. 27 is a circuit diagram of an output portion for one source line in the fourth embodiment.

FIG. 28 is a circuit diagram of a selection control circuit used in the fourth embodiment.

FIG. 29 is a circuit diagram of an output portion for one source line of the fifth embodiment.

FIG. 30 is a circuit diagram of an output portion for one source line of the sixth embodiment.

FIG. 31 is a diagram showing waveforms of signals used in the sixth embodiment.

FIG. 32 is a diagram showing the waveform of the output voltage of the sixth embodiment.

FIG. 33 is a circuit diagram of an output portion for one source line according to the seventh embodiment.

FIG. 34 is a diagram showing waveforms of signals used in the seventh embodiment.

FIG. 35 is a circuit diagram of an output portion for one source line of the eighth embodiment.

36 is a diagram showing a circuit example of the selection control circuit SCOL in FIG. 35.

37 is a view from the output terminal of the selection control circuit SCOL of FIG. 35 to the output terminal of the drive circuit.

FIG. 38 is a diagram showing an example of an oscillating voltage.

FIG. 39 is a diagram showing a circuit configuration in which a source line load is connected to FIG. 37.

FIG. 40 is a circuit diagram of an output portion for one source line of the ninth embodiment.

41 is a diagram showing a circuit example of the selection control circuit SCOL of FIG. 40. FIG.

FIG. 42 is a diagram showing waveforms of signals used in the ninth embodiment.

FIG. 43 is a diagram showing an example of an oscillating voltage.

FIG. 44 is a diagram for explaining another circuit configuration of the low pass filter.

FIG. 45 is a circuit diagram showing a second-order low-pass filter as a realistic low-pass filter.

FIG. 46 is a waveform diagram showing an output voltage in a conventional one output period.

FIG. 47 is a conceptual diagram showing changes in oscillating voltage according to the present invention.

48 is a diagram showing the relationship between the oscillating voltage and the gate signal in FIG. 47.

FIG. 49 is a circuit diagram of an output portion for one source line in the tenth embodiment.

50A shows a clock signal t2, and FIG. 50B is an output waveform diagram when the video signal data is 1. FIG.

51 is a specific circuit diagram of the decoder DEC of FIG. 49.

FIG. 52 is a circuit diagram of an output portion for one source line in the eleventh embodiment.

53A shows a clock signal t3, and FIG. 53B is an output waveform diagram when the video signal data is 1. FIG.

54 is a specific circuit diagram of the decoder DEC of FIG. 52.

FIG. 55 is a circuit diagram of an output portion for one source line in the twelfth embodiment.

FIG. 56 is a clock signal T used in the twelfth embodiment.
4 is a signal diagram showing T5.

FIG. 57 is an enlarged view showing the clock signal T4.

FIG. 58 is a waveform chart showing the relationship between input data and output voltage in the twelfth embodiment.

FIG. 59 is a circuit diagram of an output portion for one source line in the thirteenth embodiment.

FIG. 60 is a circuit diagram for explaining the operation of the conventional digital drive circuit.

FIG. 61 is a diagram showing a voltage example for realizing visually correct 8 gradations in a liquid crystal panel of the TFT system.

[Explanation of symbols]

D _{0 to} D ₃ digital image signal DEC decoder M _SMP sampling memory M _H hold memory On source line TM _{0 to} TM ₃ clock signal ASW _{0 to} ASW ₇ analog switch V _{0 to} V ₁₅ voltage signal SCOL selection control circuit T ₁ clock signal t _{1 to} t ₁₆ clock signal T _{4 to} T ₉ clock signal

 ─────────────────────────────────────────────────── ─── Continuation of front page (31) Priority claim number Japanese Patent Application No. 4-117778 (32) Priority Date 4 (1992) May 11 (33) Priority claim country Japan (JP) Application for accelerated examination ( 72) Inventor Kuniaki Tanaka, 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Prefecture, Sharp Corporation (72) Inventor Hirofumi Fukuoka 22-22, Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture (72) Inventor Yoshiharu Kanaya 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture (72) Inventor Toshihiro Yanagi 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture (56) References JP 62 -265696 (JP, A) JP-A-4-230789 (JP, A) JP-A-5-108034 (JP, A)

Claims (10)

[Claims] 1. Display pixels arranged in a matrix,
A display panel having a scanning line connected to the display picture element and a signal line connected to the display picture element, and a scanning voltage for selecting the display picture element that is different for each scanning period. A display device capable of multi-gradation display, including a driving circuit having means for sequentially supplying to the lines and means for supplying a drive voltage for driving the selected display pixel to the signal lines. A driving method, wherein an oscillating voltage output operation, in which an oscillating voltage having an oscillating component that oscillates during the one scanning period is output from the drive circuit to the signal line as the drive voltage, and the display pixel from the signal line. The averaged voltage applied to the selected display picture element is an averaged voltage that suppresses the vibration component of the drive voltage by passing through a circuit system that exists on the path leading to Applying operation and method of driving display device 2. The driving voltage has an oscillating component that periodically oscillates between a first voltage value and a second voltage value.
A method for driving the described display device. 3. Display picture elements arranged in a matrix,
A display panel having a scanning line connected to the display picture element and a signal line connected to the display picture element, and a scanning voltage for selecting the display picture element that is different for each scanning period. A display device capable of multi-gradation display, including a driving circuit having means for sequentially supplying to the lines and means for supplying a drive voltage for driving the selected display pixel to the signal lines. A driving method, wherein one of a plurality of voltages supplied from a power source and each having a substantially constant value during the one scanning period is output as the driving voltage from the driving circuit to the signal line,
An operation of applying the drive voltage to the selected display pixel,
An oscillating voltage having an oscillating component that oscillates during the one scanning period, which is obtained by alternately switching and outputting two selected voltages selected from the plurality of voltages, is output from the drive circuit to the signal line as the drive voltage. Then, the averaging voltage in which the oscillating component of the drive voltage is suppressed is selected by passing through a circuit system that exists on the path from the signal line to the display pixel and operates as a low-pass filter. And a method of driving a display device for selectively performing the operation of applying to the display pixel. 4. The method for driving a display device according to claim 3, wherein the oscillating voltage is formed by alternately switching and outputting the two selected voltages at a specific duty ratio. 5. Display picture elements arranged in a matrix,
A display panel having a scanning line connected to the display picture element and a signal line connected to the display picture element, and a scanning voltage for selecting the display picture element that is different for each scanning period. A display device capable of multi-gradation display, including a driving circuit having means for sequentially supplying to the lines and means for supplying a drive voltage for driving the selected display pixel to the signal lines. A driving method, wherein one of a plurality of voltages supplied from a power source and each having a substantially constant value during the one scanning period is output as the driving voltage from the driving circuit to the signal line,
An operation of applying the drive voltage to the selected display pixel,
An oscillating voltage having an oscillating component that oscillates during the one scanning period, which is obtained by alternately switching between an output state in which one of two selected voltages selected from the plurality of voltages is output and an output state in which both of them are simultaneously output. Is output as the drive voltage from the drive circuit to the signal line, and is passed through a circuit system that exists on the path from the signal line to the display pixel and that operates as a low-pass filter. And a step of applying an averaged voltage in which the vibration component is suppressed to the selected display picture element, the driving method of the display device. 6. The method of driving a display device according to claim 1, wherein the circuit system is provided in the display panel. 7. The driving voltage has a voltage value determined corresponding to a digital signal value indicating a gradation input to the driving circuit, claim 2, claim 3, claim 4, and claim 4.
Alternatively, the method of driving the display device according to claim 5. 8. Display picture elements arranged in a matrix,
A switching element provided in each of the display picture elements, a scanning line connected to the display picture element via the switching element, and a signal line connected to the display picture element via the switching element. A liquid crystal display panel, a means for sequentially supplying a scanning voltage for selecting the display picture element to different scanning lines for each scanning period, and a driving voltage for driving the selected display picture element. A driving method of a display device capable of multi-gradation display, comprising: a driving circuit having a means for supplying to the signal line, wherein the driving voltage is a digital signal indicating a gradation input to the driving circuit. An oscillating voltage output that outputs a oscillating voltage having a voltage value determined according to a signal value and having an oscillating component that oscillates while the switching element is in an ON state to the signal line from the drive circuit as the drive voltage. Operation and the signal line An averaged voltage that suppresses the vibration component of the driving voltage is applied to the selected display pixel by passing through a circuit system that exists on the path to the display pixel and that operates as a low-pass filter. A method for driving a display device, which performs an averaging voltage applying operation. 9. The method of driving a display device according to claim 8, wherein the switching element is a thin film transistor, the scanning line is connected to a gate electrode of the thin film transistor, and the signal line is connected to a source electrode of the thin film transistor. . 10. The method for driving a display device according to claim 8, wherein the circuit system is provided in the liquid crystal display panel.