JPH0769359B2 - Frequency measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention counts the number of input pulses that have become burst waves for each sampling cycle, and arranges the input pulses that have become burst waves uniformly over the sampling cycle. The present invention relates to improvement in accuracy of a frequency measuring device that calculates a pulse frequency at the time.

[Prior Art] As a conventional frequency measuring device, for example, FIG.
As shown in the time chart of No. 2, there is a method in which the number N of burst-wave-shaped input pulses is counted at every constant sampling period T, and the frequency f of the input pulse is calculated from f = N / T. The calculated frequency is as shown in FIG.

[Problems to be Solved by the Invention] However, in this device, as shown in the figure (b), the measured frequency is 1 / T as shown by the solid line, even though the actual frequency becomes as shown by the broken line. Since the resolution varies, the measurement error increases. This is because the sampling period and the input pulse are not synchronized, and thus a fractional time as shown by e occurs.

As a device for reducing the measurement error, there is a device that inserts a filter to smooth the measurement signal.

However, in this device, the phase of the measurement signal is delayed by the filter, which is a problem when used in a servo system or the like.

The present invention has been made in order to solve such a problem, and realizes a frequency measuring device capable of measuring an input pulse in a burst wave with high accuracy and without causing a phase delay in a measurement signal. With the goal.

[Means for Solving the Problems] The present invention counts the number of burst-wave input pulses for each sampling cycle, and the pulse frequency when the burst-wave input pulses are evenly arranged over the sampling cycle. In the frequency measurement device that calculates, the input pulse counter that counts the number of input pulses for each sampling cycle, and the fractional time from the last burst wave occurrence to the end of the sampling cycle in this sampling cycle Fractional time output section for measuring and outputting, first holding means for retaining and outputting the fractional time of the previous sampling cycle, fraction for counting the number of input pulses generated during the fractional time of the current sampling cycle The clock counter and the fractional clock counter in the previous sampling cycle Second holding means for holding and outputting a unit, and using the following equation based on the outputs of the input pulse counter, the fractional clock counter, the fractional time output section, the first retaining means and the second retaining means. Calculation unit for obtaining the measurement frequency in the current sampling period, f = (N− _Nb + N _a ) / (T−τ _n + τ _n−1 ) f: Measurement frequency N: Number of pulses counted in the current sampling period T: sampling period tau _n-1: fractional time of the previous sampling period tau _n: fractional time n _a of the current sampling period: count n _b fractional clock counter of the last sampling period: count fractional clock counter in the current sampling cycle A frequency measuring device comprising:

[Examples] The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a frequency measuring device according to the present invention.

In the figure, 1 is a one-shot circuit that generates a one-shot output S ₂ according to an input pulse S ₁ by using a flip-flop, and 2 is a burst period by taking a logical product of the input pulse S ₁ and the one-shot output S _2. It is an AND gate that outputs the pulse S ₃ .

Reference numeral 3 denotes a synchronization circuit, which synchronizes the input pulse S ₁ and the sampling clock SC with the fractional time count clock EC to generate the synchronization input pulse S ₄ and the synchronization sampling clock. The synchronous sampling clock is generated inside the synchronous circuit. In addition, the synchronizing circuit 3 uses the burst cycle pulse S ₃
And the fractional time count clock EC is given, and the latch signal
It outputs S ₅ , an input pulse clear signal S ₆ , a fractional clock counter clear signal S ₇ , a latch signal S ₈ , and a fractional time counter clear signal S ₉ .

Reference numeral 4 is an input pulse counter, which counts the number of synchronous input pulses S ₄ and is cleared at every sampling cycle by an input pulse clear signal S ₆ .

Reference numeral 5 denotes a latch, which latches and outputs the count of the input pulse counter 4 at each sampling cycle at the timing of the launch signal S ₅ .

Reference numeral 6 is a fractional clock counter, which counts the number of input pulses generated in a fractional time and is cleared by a fractional clock counter clear signal S ₇ .

Reference numeral 7 is a latch for latching and outputting the count of the fractional clock counter 6 by the launch signal S ₅ , and 8 is a latch for launching and outputting the output of the latch 7 by the latch signal S ₅ . The value latched by the latches 7 and 8 becomes the count of the fractional clock counter 6 in the current sampling period and the previous sampling period.

The period of the fraction count clock EC is set sufficiently shorter than the sampling period.

Reference numeral 9 denotes an adder / subtractor, which obtains the corrected number of pulses by the following calculation.

N−N _b + N _a N: Number of pulses counted in the current sampling cycle = output of latch 5 N _a : Fraction in the previous sampling cycle Count of clock counter 6 = Output of latch 8 N _b : Fraction in the current sampling cycle The count of the clock counter 6 = the output 10 of the latch 7 is a fraction time counter, and counts the number of fraction time count clocks EC input during the fraction time from the last burst wave in the sampling period to the end of the sampling period. Then, it is cleared by the counter clear signal S ₉ .

Reference numeral 11 is a latch, which latches the count of the fractional time counter 10 by the latch signal S ₈ .

A multiplier 12 calculates a fractional time from the output of the latch 11.

That is, the fractional time is calculated from (cycle of fractional time count clock) × (number of counted fractional time count clocks).

Reference numeral 13 is a latch, which latches the multiplication value of the multiplier 12 by the latch signal S ₈ and outputs it.

Reference numeral 14 is an adder / subtractor, which is corrected by the following calculation to obtain a calculation time.

T- [tau] _n + [tau] _n-1 T: Sampling cycle [tau] _n : Fraction time in current sampling cycle = Output of multiplier 12 [tau] _n-1 : Fraction time in previous sampling cycle =
The output 15 of the latch 13 is a divider, which uses the outputs of the adders / subtractors 9 and 14 to calculate the measured frequency f in the current sampling period by the division shown in the following equation.

_{f = (N-N b +} N a) / (T-τ n + τ n-1) , where the fraction time output unit referred to in the claims, the components 1
The first holding means and the second holding means correspond to the latches 13 and 8, respectively.

Next, the operation of such a device will be described.

FIG. 2 is a time chart of a signal of a portion that generates a burst period pulse.

When the input pulse S ₁ is given to the one-shot circuit 1, a one-shot output S ₂ corresponding to this pulse is generated. This one-shot output S ₂ is logically ANDed with the input pulse S ₁ to generate a burst cycle pulse S ₃ .

Shot width T _W, relative to the period T ₁ and the interval T ₂ of the burst wave pulse input, the relation of T ₁ «T _W «T _2.

FIG. 3 is a time chart of each signal of a portion for counting the number of input pulses in a fractional time.

Input pulse S ₁ , burst period pulse by the synchronization circuit 3
S ₃ and the sampling clock SC are synchronized with the fractional time count clock EC and synchronized input pulses S ₄ and S ₄ , respectively.
Synchronous burst pulse P ₁ and synchronous sampling clock P ₂ . Of these, the synchronous burst pulse P ₁ and the synchronous sampling clock P ₂ are generated inside the synchronous circuit, and these are ANDed with the fractional time count clock EC,
It becomes the fractional clock counter clear signal S ₇ and the latch signal S ₅ . The number of input pulses in a fractional time is measured using these signals.

Fractional clock counter 6 and latch 7 count C ₁ and C ₂
become that way.

FIG. 4 is a time chart of each signal of the part for counting the number of input pulses.

The synchronous input pulse S ₄ is input to the input pulse counter 4. An input pulse counter clear signal S ₆ and a latch signal S ₅ are generated from the synchronous sampling clock P _2, and the number of input pulses during the sampling period is counted and latched based on these signals.

The input pulse counter clear signal S ₆ and the latch signal S ₅ are shifted by a half cycle of the fractional time count clock EC to prevent competition between latch and clear.

FIG. 5 shows a time chart of the signal of the part for counting the fractional time.

Sync burst pulse P ₁ to fractional time counter clear signal
It generates S _9, making the latch signal S ₈ from the synchronous sampling clock P _2. The clear signal S ₉ is generated every synchronous burst pulse P ₁ , and the latch signal S ₈ is the synchronous sampling clock P ₂
Since it is generated every time, the output of the fraction time counter 10 is always the number of clocks of the fraction time count clock counted from the time when the last sync burst pulse occurs to the time when the sync sampling clock occurs.

From the signals of these time charts, N _b , N _a , τ _n , τ
The value of _n-1 is obtained, and the measured frequency is calculated using the formula.

FIG. 6 is a diagram showing the relationship between the sampling time corrected using the equation and the number of clocks.

In the apparatus according to the present invention, as shown in FIG. 6, the sampling time T-τ _n + τ _n-1 corrected by using the previous fractional time τ _n-1 and the current fractional time τ _n (N−N _{Since b} + N _a ) pulses are input, the measurement frequency is calculated from (N−N _b + N _a ) / (T−τ _n + τ _n−1 ).

[Effect] According to the present invention, the sampling frequency and the number of counted pulses are corrected to obtain the measurement frequency according to the phase relationship between the input pulse of the burst wave and the sampling period. Therefore, the input pulse and the sampling period are asynchronous. It is possible to prevent a decrease in measurement accuracy due to Further, since the measurement signal does not need to be averaged through the filter, the phase delay of the measurement signal does not occur.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a frequency measuring device according to the present invention, FIGS. 2 to 6 are operation explanatory diagrams of the device of FIG. 1, and FIG. 7 is an operation of an example of a conventional frequency measuring device. It is an explanatory time chart. 4 ... Input pulse counter, 6 ... Fractional clock counter,
8,11,13 ... Latch, 10 ... Fractional time counter, 12 ... Multiplier.

Claims (1)

[Claims] 1. A frequency measuring device for counting the pulse number of a burst wave input pulse for each sampling period and calculating a pulse frequency when the burst wave input pulses are evenly arranged over the sampling period. An input pulse counter that counts the number of pulses for each sampling cycle, and a fractional time output section that measures and outputs the fractional time from the time when the last burst wave occurred to the end of the sampling cycle in this sampling period. A first holding means for holding and outputting the fractional time of the previous sampling cycle, a fractional clock counter for counting the number of input pulses generated in the fractional time of the current sampling cycle, and The second that holds and outputs the count of the fractional clock counter A calculation for obtaining the measured frequency in the current sampling period using the following equation based on the outputs of the holding unit, the input pulse counter, the fractional clock counter, the fractional time output unit, the first holding unit and the second holding unit. Part, f = (N−N _b + N _a ) / (T−τ _n + τ _n−1 ) f: Measurement frequency N: Number of pulses counted in the current sampling period T: Sampling period τ _n−1 : Previous sampling Fractional time of cycle τ _n : Fractional time of current sampling cycle N _a : Count of fractional clock counter in previous sampling cycle N _b : Frequency measurement characterized by having count of fractional clock counter in current sampling cycle apparatus.