JPH0767048A - Display controller - Google Patents

Abstract

PURPOSE:To provide a display controller which can horizontally enlarge a display area without the increase of cost caused by enlarging the capacity of a memory. CONSTITUTION:The display controller is provided with a code memory 11 and a read address generating circuit 42 for generating read address data 33 corresponding to the code memory 11. It is discriminated by a decode circuit 43 whether character code data 52 read from the code memory 11 are a repeated control code or not. When the character code data 52 are correspondent to the repeated control code, an address corresponding to a transparent space is outputted as address data 53 and a count enable signal 54 and the number of times of repetition following the repeated control code are outputted to a delay counter 44 as delay data 55. When the count enable signal 54 is inputted, the delay counter 44 outputs a delay pulse 51 for temporarily stopping a horizontal position counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for performing display control for displaying characters such as characters and graphics on the screen of a video device such as a television receiver.

[0002]

2. Description of the Related Art Generally, a television receiver (hereinafter referred to as T
A video device such as V) has a function selection display function for performing setting for each function by displaying channel display, volume display, setting items related to functions of the video device main body, and setting amount related to the setting items. It is provided. As a method of displaying the characters that make up the setting items in this function selection display function, a character memory that stores the character data for the number of displayed characters (hereinafter referred to as a code memory) and a color for coloring the characters in character units There is a system in which a memory and a pattern memory in which the shape of a character is stored are used and a character is displayed based on the data from each memory.

For example, a microcontroller TM for TV
The P47C434 / 634 (manufactured by Toshiba Corp.) has a built-in display control device, and this display control device is a device capable of displaying two lines of 16 characters.

This display control device will be described with reference to the drawings. FIG. 7 is a block diagram showing an example of a conventional display control device.

As shown in FIG. 7, the display control device described above includes an oscillation circuit 1 provided with terminals 2 and 3 connected to an oscillator (not shown). A horizontal synchronizing signal is applied as a trigger to the oscillation circuit 1 via a terminal 4, and the oscillation circuit 1 oscillates a display clock 38 whose frequency is an integral multiple of the frequency of the horizontal synchronizing signal.

The display clock 38 from the oscillation circuit 1 is given to the horizontal display position detection circuit 6. The horizontal display position detection circuit 6 detects the horizontal synchronization signal, and at the same time as this detection, outputs the control signal 28 including the display clock 38 to the horizontal position counter 7. The horizontal position counter 7 counts the display clock 38 based on the control signal 28 and generates count data 30 indicating the count value.

The vertical synchronizing signal taken into the terminal 5 is given to the vertical display position detecting circuit 9 together with the horizontal synchronizing signal taken into the terminal 4. The vertical display position detection circuit 9 detects the start and end of the input of the vertical synchronization signal, detects the input start of the vertical synchronization signal, and at the same time outputs the control signal 29 including the horizontal synchronization signal to the vertical position counter 8 to output the vertical synchronization signal. The output of the control signal 29 is stopped at the same time when the input end is detected.

The vertical position counter 8 counts the horizontal scanning frequency in the vertical scanning period based on the control signal 29, and generates count data 31 indicating this count value.

The count data 30 generated by the horizontal position counter 7 and the count data 31 generated by the vertical position counter 8 are supplied to the read address generation circuit 10. The read address generation circuit 10 uses the count data 30, 31.
The read address data 32 and 33 are generated based on.

The read address data 33 is given to the code memory 11. Code data for each character is stored in the code memory 11. From the code memory 11, the code data stored at the address corresponding to the read address data 33 is the address data 3
It is output as 4. The address data 34 is given to the pattern memory 14, and the pattern data 37 stored at the address corresponding to the address data 34 is read from the pattern memory 14.

On the other hand, the read address data 32 is the foreground color memory 12 and the background color memory 13.
Given to. The color data 35 stored at the address corresponding to the read address data 32 is read from the foreground color memory 12, and the color data stored at the address corresponding to the read address data 32 is read from the background color memory 13. 36 is read.

The pattern data 37 read from the pattern memory 14 is a parallel-serial conversion circuit (hereinafter referred to as P
/ S conversion circuit 15), the P / S conversion circuit 15 performs parallel-serial conversion on the pattern data 37 in synchronization with the display clock 38, and outputs the conversion result to the switching circuit 16. The switching circuit 16 is P / S
Based on the conversion result from the conversion circuit 15, the color data 35 from the foreground color memory 12 and the color data 36 from the background color memory 13 are selectively selected.
Output to 7.

The RGB color table 17 is provided for each color signal 3
5, 36 are converted into R (red), G (green), and B (blue) color signals, and the R, G, and B color signals are input to terminals 19, 20, 21.
And output the luminance signal Y from the terminal 18
Output from.

In recent years, TVs have become multi-functional by incorporating many functions, and with this multi-functionalization, there has been a demand for a display function relating to functional operations for making the operability for the user easier to understand. In particular, the function selection display function of the TV requires a display design that does not block the broadcast video image displayed on the TV screen as much as possible. For example, the channel number is displayed at the upper right corner of the screen, and the volume level is displayed at the lower center of the screen.

However, when the above-mentioned display control device simultaneously displays at the left and right corners of the screen, the code information corresponding to the left corner and the right corner are displayed so that characters and figures are not displayed at the center of the screen. It is necessary to insert transparent space code information that represents a transparent space between the code information corresponding to the position and the code information, and a code memory having a capacity for the number of character strings that can be displayed in the horizontal direction of the screen is required. Therefore, the capacity of the code memory is increased and the cost is increased.

In addition to multi-functional TVs, so-called wide screen TVs have been developed in which the screen aspect ratio is expanded from 3: 4 to 9:16. This wide-screen TV requires a display control device capable of displaying a larger number of character strings. Therefore, the capacity of the code memory is further increased and the cost is further increased.

[0017]

As described above, when the conventional display control device simultaneously displays at the positions of the left and right corners of the screen, the left corner of the screen is displayed so that characters and figures are not displayed at the center of the screen. It is necessary to insert transparent space code information that represents a transparent space between the code information corresponding to the position and the code information corresponding to the position of the right corner, and the capacity for the number of character strings that can be displayed in the horizontal direction of the screen must be set. It requires a code memory to have. Therefore, the capacity of the code memory is increased and the cost is increased.

Further, in addition to the multi-functionality of the TV, a so-called wide screen TV whose screen aspect ratio is expanded from 3: 4 to 9:16 is required to display more character strings. The capacity of the code memory is further increased,
The cost increase will be even greater.

It is an object of the present invention to provide a display control device capable of enlarging the display area in the horizontal direction without incurring a cost increase due to an increase in the capacity of the memory.

[0020]

SUMMARY OF THE INVENTION The present invention is a display control device for performing display control for displaying characters such as characters and figures on the screen of a video device such as a television receiver. A code memory in which information and repetitive control information indicating the number of times this character is repeatedly displayed are stored as code information, and a display readout address in the row direction for the code memory is generated in synchronization with horizontal scanning and vertical scanning of the video device. Read address generating means for performing a row direction read address generating operation and a column direction read address generating operation for generating a column direction display read address for the code memory, and the row direction display read address and the column direction display read address Code read from the code memory based on Detecting means for detecting whether or not code information corresponding to the repetitive control information is included in the report, and the detected repetitive operation when the detecting means detects the code information corresponding to the repetitive control information. Display period signal generating means for generating a display period signal indicating the display period of the character corresponding to the number of times of repetition of the character obtained from the control information, and during the period indicated by the display period signal,
The column-direction read address generating operation of the read address generating means is temporarily stopped while holding the address for the character indicated by the repeat control information, and when the display period indicated by the display period signal ends, the read address is generated. Delay means for restarting the column direction read address generating operation of the means.

[0021]

[Operation] In the display control device of the present invention, when it is detected that the code information read from the code memory includes code information corresponding to the repeat control information, the detected repeat control is performed. A display period signal indicating a display period of the character corresponding to the number of times the character is repeated obtained from information is generated, and during the period indicated by the display period signal, the column-direction read address generation operation of the read address generation means is performed. The address for the character indicated by the repeat control information is temporarily stopped while being held, and when the display period indicated by the display period signal ends, the column-direction read address generating operation of the read address generating means is restarted.

When it is detected that the code information read from the code memory contains the code information corresponding to the repetition control information, the repetition of the character obtained from the detected repetition control information is detected. A display period signal indicating the display period of the character corresponding to the number of times is generated, and the column-direction read address generation operation is temporarily stopped during the period indicated by the display period signal.

During this display period, the column direction display read address holds the address of the character obtained from the detected repetitive control information, so that this character can be displayed for the number of repetitions of the repetitive control information. . Therefore, it is possible to expand the display area in the column direction, that is, the horizontal direction of the screen of the video display device, without using the memory capacity corresponding to the number of times the displayed character is repeated.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the display control device of the present invention.

As shown in FIG. 1, the display control device includes an oscillation circuit 1 provided with terminals 2 and 3 connected to an oscillator (not shown). The horizontal synchronizing signal is applied to the oscillator circuit 1 as a trigger through the terminal 4, and the oscillator circuit 1
Oscillates a display clock 38 whose frequency is an integral multiple of the frequency of the horizontal sync signal.

The display clock 38 from the oscillation circuit 1 is given to the horizontal display position detection circuit 6. The horizontal display position detection circuit 6 detects the horizontal synchronizing signal, and at the same time as this detection, the horizontal position counter 41 outputs the control signal 28 including the display clock 38.
Output to. The horizontal position counter 41 counts the display clock 38 based on the control signal 28 and generates count data 30 indicating the count value. The counting operation of the horizontal position counter 41 is temporarily stopped when the delay pulse 51 from the delay counter 42 described later is input, and is restarted after the input of the delay pulse 51 is stopped.

The vertical synchronizing signal taken into the terminal 5 is given to the vertical display position detecting circuit 9 together with the horizontal synchronizing signal taken into the terminal 4. The vertical display position detection circuit 9 detects the start and end of the input of the vertical synchronization signal, detects the input start of the vertical synchronization signal, and at the same time outputs the control signal 29 including the horizontal synchronization signal to the vertical position counter 8 to output the vertical synchronization signal. The output of the control signal 29 is stopped at the same time when the input end is detected.

The vertical position counter 8 counts the horizontal scanning frequency in the vertical scanning period based on the control signal 29, and generates the count data 31 indicating this count value.

The count data 30 generated by the horizontal position counter 41 and the count data 31 generated by the vertical position counter 8 are applied to the read address generation circuit 42.
The read address generation circuit 42 uses the count data 30, 3
Based on 1, read address data 32 and 33 are generated. In this embodiment, one character has a width corresponding to eight display clocks (hereinafter, referred to as one character width), and the horizontal address is updated with eight clocks of the count data 30 of the horizontal position counter 41 as one unit. .

The read address data 33 is given to the code memory 11, and the character code data 52 stored at the address corresponding to the read address data 33 is read from the code memory 11.

On the other hand, the read address data 32 is the foreground color memory 12 and the background color memory 13.
Given to. The color data 35 stored at the address corresponding to the read address data 32 is read from the foreground color memory 12, and the color data stored at the address corresponding to the read address data 32 is read from the background color memory 13. 36 is read.

The character code data 52 is given to the decoding circuit 43. The decoding circuit 43 determines whether or not the character code data 52 is a repetitive control code, and generates address data 53 for the pattern memory 14 based on the result of the determination.

When the determination result of the decoding circuit 43 indicates that it corresponds to a normal character code, the character code data 52 is output as it is as the address data 53.

On the other hand, when the determination result of the decoding circuit 43 indicates that it corresponds to the repetitive control code, the address for the pattern of the transparent space (the pattern is all 0) is output as the address data 53, and
The number of repetitions following the count enable signal 54 and the repetition control code is used as the delay data 55 to form the delay counter 44.
Is output to.

When the count enable signal 54 is input, the delay counter 44 counts the display clock based on the control signal 28 from the horizontal display position detection circuit 6, detects the one character width, and then outputs the delay pulse 51 to the horizontal position. Output to the counter 41. The delay pulse 51 is output during the display period of the number of repetitions indicated by the delay data 55.

Address data 5 from the decoding circuit 43
3 is provided to the pattern memory 14. The pattern memory 14 stores character dot pattern data. The font composition of one character is 16 x vertical
There are 8 dots horizontally, and the number of colors per pixel is 16 colors (4b
it).

The pattern data 37 corresponding to the address data 53 is read from the pattern memory 14. The read pattern data 37 is given to the P / S converter 15, the P / S conversion circuit 15 performs parallel-serial conversion on the pattern data 37 in synchronization with the display clock 38, and the conversion result is used as the switching circuit 16. Output to. The switching circuit 16 selectively outputs the color data 35 from the foreground color memory 12 and the color data 36 from the background color memory 13 to the RBG color table 17 based on the conversion result from the P / S conversion circuit 15.

The RGB color table 17 includes the switching circuit 1
The output from 6 is converted into R (red), G (green), and B (blue) color signals, and the R, G, and B color signals are input to terminals 19, 20, and
21 and the luminance signal Y is output from the terminal 18.

Next, the operation of the display control device will be described with reference to the drawings. FIG. 2 is a diagram showing an access timing to each memory for explaining the operation of the display control device of FIG.

First, the oscillation circuit 1 oscillates the display clock 38 as shown in FIG. The display clock 38 from the oscillation circuit 1 is given to the horizontal display position detection circuit 6. As shown in FIG. 2B, the horizontal display position detection circuit 6 detects the horizontal synchronization signal and outputs the control signal 28 including the display clock 38 to the horizontal position counter 41 at the same time as this detection. As shown in FIG. 2C, the horizontal position counter 41 counts the display clock 38 based on the control signal 28 and generates count data 30 indicating the count value.

The vertical display position detecting circuit 9 detects the start and end of the input of the vertical synchronizing signal, detects the input start of the vertical synchronizing signal, and at the same time, the control signal 29 including the horizontal synchronizing signal.
Is output to the vertical position counter 8 to detect the end of input of the vertical synchronizing signal, and at the same time, stop outputting the control signal 29.

The vertical position counter 8 counts the horizontal scanning frequency in the vertical scanning period based on the control signal 29, and generates the count data 31 indicating this count value.

The count data 30 generated by the horizontal position counter 41 and the count data 31 generated by the vertical position counter 8 are supplied to the read address generation circuit 42.
The read address generation circuit 42 uses the count data 30, 3
Based on 1, read address data 32 and 33 are generated. The read address data 33 is given to the code memory 11, and the character code data 52 stored at the address corresponding to the read address data 33 is read from the code memory 11.

The read address data 42 is given to the foreground color memory 12 and the background color memory 13. As shown in FIG. 2F, the color data 35 stored at the address corresponding to the read address data 32 is read from the foreground color memory 12, and the read address data 32 is read from the background color memory 13. The color data 36 stored at the address corresponding to is read.

The character code data 52 is supplied to the decoding circuit 43, and the decoding circuit 43 determines whether the character code data 52 is a normal character code or a repetitive control code, and based on the result of this determination, the pattern memory 14 is determined. To generate address data 53 for.

As shown in FIG. 2E, the pattern data 37 corresponding to the address data 53 is read from the pattern memory 14. Pattern data 37 is P / S
The P / S conversion circuit 15 is supplied to the converter 15 and performs parallel-serial conversion on the pattern data 37 in synchronization with the display clock 38, and outputs the conversion result to the switching circuit 16.

As shown in FIG. 2 (g), the switching circuit 16 uses the color data 35 from the foreground color memory 12 and the color data from the background color memory 13 based on the conversion result from the P / S conversion circuit 15. 36 and 36 are selectively output to the RGB color table 27. RGB color table 17
Represents the color signals 35, 36 as R (red), G (green), B
It is converted into each color signal of (blue), and each color signal of R, G, B is output via the terminals 19, 20 and 21, respectively, and the luminance signal Y is output via the terminal 18. Each color signal is supplied to the display means individually or after being superimposed on the video signal, and the character of each character is displayed on the screen of the display means.

Next, the read address and the access timing to the code memory 11 when the count value of the delay counter 44 reaches a predetermined number of repetitions after the detection of the repetition control code will be described with reference to the drawings. FIG. 3 is a diagram showing timings for explaining the operation at the start and end of the delay operation of the display control device of FIG.

The horizontal position counter 41 counts the display clock 38 from the oscillation circuit 1 and outputs count data 30. Since the width of one character is 8 clocks, as shown in FIG. 3B, the read address is updated every 8 clocks.

For example, when the repeat control code is stored in the address n of the code memory 11 and the repeat number is stored in the address (n + 1), the read address generating circuit 41 operates as shown in FIG. Is output, and the repetitive control code stored in the address of the code memory 11 corresponding to this address data 33 is read. The read repetitive control code is supplied to the decoding circuit 43. Decoding circuit 43
Outputs a count enable signal 54 as shown in FIG.

The delay counter 44, to which the count enable signal 54 is applied, starts the counting operation from the position of the read address n with the display clock 38 as a reference, as shown in FIG. 3 (e). After counting 8 units, which is the width of one character, the delay pulse 51 is output as shown in FIG. When the delay pulse 51 is input to the horizontal position counter 41, the horizontal position counter 41 temporarily stops the counting operation at (n + 1).

The read address generation circuit 42 is (n + 1)
When the address data 33 of the
From the delay counter 44 to delay data 55 indicating the number of repetitions.
Is output to. The delay counter 44 has delay data 55 and 8
The delay data 55 is compared with the count data in clock units.
The delay pulse is continuously output until the number of repetitions indicated by and the count data match.

When the number of repetitions indicated by the delay data 55 and the count data in units of 8 clocks match, the output of the delay pulse 51 is stopped, as shown in FIG. 3 (d). When the output of the delay pulse 51 is stopped, the counting operation of the horizontal position counter 41 is restarted, and the read address 33 is updated to (n + 2) after the lapse of 8 clocks.

Next, the code memory 11 stores the address (n
When the normal character code 53 corresponding to +2) is output,
As shown in FIG. 3D, the output of the count enable signal is stopped.

Therefore, the transparent space can be repeated without increasing the capacity of the code memory 11,
The display area can be expanded horizontally. For example,
When the time and channel are displayed in the blanking areas formed on the left and right portions of the screen having the aspect ratio of 9:16, on which the image having the aspect ratio of 3: 4 is displayed, FIG.
By setting the number of transparent spaces to be repeatedly displayed as shown in (a), the capacity of the code memory does not increase, and the horizontal direction is displayed on the television receiver screen as shown in FIG. 4 (b). A display enlarged in the direction is performed.

In the present embodiment, the number of times the transparent space is repeated based on the repeat control code is performed for each character width (8 clock units), but a method of setting it in arbitrary clock units may be used. . In this method, the delay counter counts one unit of an arbitrary clock unit, and then outputs a delay pulse, and compares the count data with the number of repetitions in an arbitrary clock unit.

Further, in this embodiment, the code memory capacity is prevented from increasing by defining the number of repetitions of the transparent space, but other characters different from the characters of the transparent space (for example, characters, figures, etc.). It is possible to prevent the code memory from increasing in capacity by setting the number of repetitions of. For example, by storing the repetitive control code and the number of repetitions in the code memory at an arbitrary address, and by storing the character code desired to be repeatedly displayed at the subsequent address, the desired character can be stored without increasing the memory capacity. It can be displayed repeatedly.

The read address and the timing of access to the code memory by this method will be described with reference to the drawings. FIG. 5 is a diagram showing timings for explaining operations at the start and end of the delay operation in another display control device.

For example, when the repeat control code is stored in the address n of the code memory, the repeat number is stored in the address (n + 1), and the character code is stored in the address (n + 2),
As shown in FIG. 5C, the read address generating circuit is n
Is output, and the repetitive control code stored in the address of the code memory corresponding to this address data is read. The read repetitive control code is supplied to the decoding circuit. The decoding circuit outputs a count enable signal, as shown in FIG.

The delay counter supplied with the count enable signal starts the counting operation from the position of the read address n based on the display clock from the oscillation circuit, as shown in FIG. 5 (e). After counting in units of 16 clocks, which is a width of two characters, a delay pulse is output as shown in FIG. When the delay pulse is input to the horizontal position counter, the horizontal position counter temporarily stops the counting operation at (n + 1).

When the read address generating circuit outputs (n + 1) address data, the number of repetitions is output from the code memory to the delay counter. The delay counter compares the number of repetitions with the count data in 8-clock units, and continuously outputs the delay pulse until the number of repetitions and the count data match.

When the number of repetitions and the count data in units of 8 clocks match, the output of the delay pulse is stopped as shown in FIG. 5 (d). When the output of the delay pulse is stopped, the counting operation of the horizontal position counter is restarted, and the read address is updated to (n + 3) after the lapse of 8 clocks.

Next, the code memory reads the address (n +
When the character code corresponding to 3) is output, the output of the count enable signal is stopped as shown in FIG.

Therefore, any character can be repeated without increasing the capacity of the code memory, and the display area can be enlarged in the horizontal direction. For example, when displaying a volume, as shown in FIG. 6 (a), by making the characters to be displayed repeatedly an elongated bar graph and a transparent space, the capacity of the code memory does not increase and the screen of the television receiver is not displayed. , As shown in FIG. 6 (b),
A horizontally enlarged display is performed.

[0066]

As described above, according to the display control device of the present invention, the display area can be expanded in the horizontal direction without increasing the cost due to the increase in the capacity of the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a display control device of the present invention.

2 is a diagram showing an access timing to each memory for explaining an operation of the display control device of FIG. 1. FIG.

FIG. 3 is a diagram showing timings for explaining an operation at the time of starting and ending a delay operation of the display control device of FIG.

FIG. 4 is a diagram showing an example of contents of a code memory of the display control device of FIG. 1 and a screen display corresponding thereto.

FIG. 5 is a diagram showing timings for explaining operations at the start and end of the delay operation of another embodiment of the display control device of the present invention.

FIG. 6 is a diagram showing an example of contents of a code memory of the display control device of FIG. 5 and screen display corresponding thereto.

FIG. 7 is a block diagram showing a conventional display control device.

[Explanation of symbols]

11 ... Code memory, 14 ... Pattern memory, 41 ... Horizontal position counter, 42 ... Read address generating circuit, 43
... decoding circuit, 44 ... delay counter.

Claims (2)

[Claims] 1. A display control device for performing display control for displaying a character such as a character or a figure on a screen of a video device such as a television receiver, the character information for the character and the number of times the character is repeatedly displayed. And a row-direction read-address generating operation for generating a row-direction display read address for the code memory in synchronization with horizontal scanning and vertical scanning of the video device. Read address generating means for performing a column direction read address generating operation for generating a column direction display read address for the code memory; and reading from the code memory based on the row direction display read address and the column direction display read address. In the code information that has been Detecting means for detecting whether or not code information corresponding to information is included, and when the detecting means detects code information corresponding to the repetitive control information, repetition of a character obtained from the detected repetitive control information Display period signal generating means for generating a display period signal indicating the display period of the character corresponding to the number of times, and repeating the column direction read address generating operation of the read address generating means during the period indicated by the display period signal. A delay unit for temporarily stopping while holding the address for the character indicated by the control information, and for restarting the column-direction read address generation operation of the read address generation unit when the display period indicated by the display period signal ends. A display control device characterized by the above. 2. The display control device according to claim 1, wherein the repetition control information is information indicating the number of repetitions for a character in a transparent space.