JPH02224586A - Screen display device - Google Patents

Abstract

PURPOSE:To vary the time of a burst period of a composite video signal and to prevent crosstalk of signals of the PAL system and the NTSC system by providing a burst period register and a burst period setting means. CONSTITUTION:A burst period register 61 storing a prescribed value is provided in a display control register 6, and a burst period setting means 131 varying the time of the color burst period is provided in a display control circuit 13 based on a value in the register 61. When an address representing the address of the register 61 from an externally mounted control circuit such as a microcomputer and a value to be stored in the register 61 are inputted to an input control circuit 3 in terms of serial signals sequentially, a prescribed value is stored in the register 61. Thus, the means 131 outputs a setting signal of the color burst period. That is, plural color burst signals are outputted in response to the value of the register 61 and crosstalk is prevented by adjusting the time of the color burst period switchingly in an area where crosstalk of signal of the PAL system and the NTSC system easily takes place.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a screen display device that displays characters and patterns such as channel numbers in broadcast images displayed on a display device such as a cathode ray tube. .

[Prior Art] FIG. 3 shows an example of the configuration of a conventional screen display device of this type. In FIG. 3, 1 is a display oscillation circuit to which the oscillation output of the π-type LC oscillation circuit 1a is supplied, 2 is a timing generator that generates various timings using the signal oscillated by the display oscillation circuit 1, and 3 is a timing generator for this. Each input terminal 38 to 3c is connected to an external control circuit such as a microcomputer (not shown) for controlling the output of the timing generator 2 and the screen display device.
4 is a data control circuit, 5 is an address control circuit, and 7 is a display data memory for storing control data. , RAM.

A display character memory 8 stores characters and patterns to be displayed in the font structure shown in FIG. 4, and is composed of a ROM. 6 is a display control register that latches commands such as display control among the outputs of the input control circuit 3; 9 is a terminal 9a, 9b;
11 is a synchronization signal switching circuit that selectively outputs either a horizontal or vertical synchronization signal of the image signal supplied to the image signal or a horizontal or vertical synchronization signal generated internally; 11 is a character or pattern in the display device; 13 is a display control circuit which controls the display of the output of the display character memory 8 in accordance with display commands from the display control register 6. This screen display device is composed of the above circuits, and the output of the display control circuit 13 is supplied to the video mixer 17, which outputs a composite video signal via the CVIDEO terminal 17a. Also, from the display control circuit 13.

R, G, H color signals, etc. are outputted via terminals 13a to 13f. 10 is an H counter, 14 is a shift register,
15 is an oscillation circuit for generating a synchronizing signal to which the oscillation output of the oscillation element circuit 15a is supplied; 16 is a timing generator for generating a synchronizing signal; and 21 is a blinking circuit.

Next, the operation will be explained.

The human control circuit 3 processes control data input from a microcomputer etc. through terminals 38 to 3c, causes the display control register 6 to latch commands such as display control, etc., and displays character codes etc. as display contents. It is stored in the data memory 7. During display, the character code stored in the display data memory 7 accesses the display character memory 8 as output data, and the display character font output from the display character memory 8 is input to the display control circuit 13. Here, in the display data memory 7, one word is (
a+b) bits, and if the number of characters displayed is C, it is composed of a total of (a+b)·C bits. On the other hand, it is assumed that one font of the display character memory 8 is composed of (JXm) bits, and there are n characters of such types. The display timing is determined by inputting a synchronization signal from the image signal to the synchronization signal switching circuit 9, counting this synchronization signal with the H counter 10, and using the display position detection circuit 11 based on this count value to display the characters displayed on the display device. determine the position of The display control circuit 13 synchronizes the display character output with an external video signal, controls the display according to the contents of the display control register 6, outputs it, and supplies it to the video mixer 17. Note that the oscillation circuit 1 for generating a synchronizing signal
5, the oscillation element circuit 15a can generate a synchronizing signal of the N'I'' SC method or the PAL method, and this switching is performed by the signal from the N/P terminal 15b, thereby generating 4 fsc or 2 fsc oscillation. The synchronization signal generation timing generator 16 generates a synchronization signal, so it is possible to display on the TV screen even when there is no signal.However, fsc is a color subcarrier, and in the NTSC system, 3
．． 58M)lz, 4.43M1l for PAL method
It is z.

In addition, the video mixer 17 outputs N '1' S C
It is possible to generate a composite video signal of both PAL and PAL formats and to superimpose it onto an external composite video signal. The composite video signal has character level (LEC; HA), external composite video input (CVIN), and blanking level (
CVI is synthesized by switching six signals: LEBK), background carrier color signal input (R8IN), color burst input (CBIN), and sync chip level.
It is output from the DEO terminal 17a.

[Problem to be solved by the invention] By the way, in the case of conventional screen display devices, PAL system and NT
In areas where both signals of the SC system are received, there is a problem that interference may occur because the frequencies of the carrier color signals are close.

This invention was made to solve the above problem, and aims to prevent interference between the PAL system and NTSC system signals by making the burst period time of the decoded video signal variable. .

[Means for Solving the Problems] A screen display device according to the present invention includes a burst period register that stores a predetermined value in a display control register, and displays a color burst based on the value in the burst period register. The present invention is characterized by providing a burst period setting means for varying the period time.

[Operation] When a predetermined value is held in the register for the burst period,
The burst period setting means outputs a color burst period setting signal according to the value held in the burst period register, and the synchronization signal generation timing generator outputs two types of color burst signals, long and short.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

In addition, the same numbers and numbers are used for components that are the same as those in the prior art.
, and the explanation thereof will be omitted.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. In the figure, 61 is a burst period register in the display control register 6 that stores a predetermined value, and 131 is set in the burst period register 61. The burst period setting means outputs a color burst period setting signal based on the determined value.

Next, the operation will be explained.

When the address indicating the address of the burst period register 61 and the value to be stored in the burst period register 61 are sequentially input to the input control circuit 3 as a serial signal from an external control circuit such as a microcomputer, the values are stored in the burst period register 61. A predetermined value is stored.

When a predetermined value is stored in the burst period register 61, the burst period setting means 131 in the display control circuit 13 outputs a color burst period setting signal.

FIG. 2 is a diagram showing details of a specific example of this burst period setting means. This is a selector that you can select depending on your preference.

In such a circuit configuration, if the value in the burst period register 61 is "1", a color burst setting signal with a long pulse width from signal line a is output, and the value in the burst period register 61 is 10'. If so, a color burst setting signal with a short pulse width is output along the signal line.

As a result, two types of color burst signals, long and short, are output. Therefore, in areas where PAL and NTSC signals are susceptible to interference (4), interference can be made less likely to occur by switching and adjusting the time of the color burst period.

[Effects of the Invention] As explained above, according to the present invention, a burst period register is provided for storing a predetermined value in a display control register, and a color burst period is determined based on the value in the burst period register. Since the burst period setting means for setting the time is provided, it is possible to prevent interference between signals of both the PAL system and the NTSC system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram of a specific example of the burst period setting means in FIG. 1, FIG. 3 is a block diagram of a conventional screen display device, and FIG. FIG. 4 is a diagram showing the configuration of fonts in a conventional display character memory. DESCRIPTION OF SYMBOLS 1... Display oscillation circuit, 2... Timing generator, 3... Input control circuit, 4... Data control circuit, 5... Address control circuit, 6... Display control register, 7... ... Display data memory, 8... Display character memory, 9... Synchronization signal switching circuit, 11... Display position detection circuit, 13... Display control circuit, 17...
Video mixer, 61... register for burst period,
131...Burst period setting means. In the drawings, the same reference numerals indicate the same or corresponding components. Figure 4

Claims (1)

[Scope of Claims] A screen display device that displays characters or patterns on a display device such as a cathode ray tube includes an oscillation circuit that generates signals that serve as reference for various timings, and various timings based on the oscillation signals of the oscillation circuit. A timing generator that generates a signal, an input control circuit that accepts and processes a control signal from an external control circuit such as a microcomputer, a synchronization signal switching circuit that inputs a synchronization signal for a video signal to be displayed on the display device, and A display position detection circuit that counts synchronization signals to detect the display position of the display device, and control data such as characters, pattern codes, blinking information, etc. that are processed by the input control circuit and are to be displayed on the display device. a display data memory for storing; a display character memory for storing fonts of characters displayed as the display contents;
A display control circuit that outputs a predetermined display signal to display display contents at a predetermined position of the display device based on the position detection signal from the display position detection circuit, and a synchronization signal generation circuit that generates various timings of the decoded video signal. a timing generator, a video mixer that mixes the display signal into the video signal, and a display control register that holds data input from the external control circuit to the input control circuit; A burst period register for storing a predetermined value is provided, and a burst period setting means is provided for setting the time of the color burst period based on the value stored in the burst period register,
A screen display device characterized in that the synchronization signal generation timing generator outputs a color burst signal corresponding to the output of the burst period setting means.