JPH0766920B2 - Wiring connection method and device for IC element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention exists under an insulating film by laying an additional wiring on the surface of a protective film (insulating film) of an IC device that has been prototyped and almost completed. The present invention relates to a wiring connection method and an apparatus thereof for an IC element, which enables connection between wirings to specify a defective portion or repair the defective portion to realize characteristic evaluation of an IC element and quick design change.

[Conventional technology]

With the aim of improving the performance and speed of semiconductor devices, semiconductor devices are being miniaturized and highly integrated. Along with this, it has become difficult to develop a semiconductor device, resulting in a longer development period. This situation shows that the LSI design also requires a cut-and-try circuit manufacturing technique. That is, the defective portion on the chip that does not work sufficiently with the conventional design is specified, the wiring existing in the portion is cut, the wiring is given at an arbitrary position, the defective wiring is repaired, and provisionally. If a semiconductor device that can achieve a complete operation is manufactured, subsequent characteristic evaluation and design change can be performed quickly.

On the other hand, as a conventional technique, for example, a journal of
Electrochemical Society, Volume 128, Issue 9 (1981)
2039 to 2041 (Journal of Electrochemical S
ociety vol, 128, No.9, (1981) pp.2039-1041), or Extended Abstracts of the Seventeens Conference on Solid State Devices and Materials (1985) No.
Pages 193 to 196 (Extended Abstracts of the 17th C
onference on Solid State Devices and Materials, Tok
yo, 1985, pp.193-196), etc.,
Mo on a Si substrate coated with SiO ₂ using laser CVD technology
Techniques for forming wiring are shown. However, in order to lay wiring on an actual semiconductor device, it is necessary to form a wiring material having sufficiently low resistance at high speed.
Even if it is based only on such a viewpoint, the conventional technique cannot be applied as it is.

Even if the wiring can be laid at a practical speed, it is required that the adhesion strength between the wiring and the base be sufficient and that the wiring shape having a sufficient cross-sectional area be obtained.

According to the above-mentioned conventional technique, it is possible to increase the film thickness of the wiring material to be formed by increasing the CVD source gas pressure, increasing the laser output, and decreasing the relative scanning speed of laser light irradiation. There is a description of.

However, according to the experiments conducted by the inventors of the present application, the laser
It was clarified that when the film thickness of the wiring formed by CVD is increased, the wiring is peeled off or cracked. Further, when the laser output is increased, not only the underlying layer, especially the diffusion layer and the junction, are overheated and the characteristics deteriorate, but also the partial thermal capacity varies depending on the underlying structure, for example, the presence of Al wiring and the thickness of the passivation film. Therefore, it was also clarified that the film thickness and the wiring width of the wiring material to be formed remarkably changed. Wiring laying on a semiconductor device cannot be realized unless such a problem is solved.

As still another conventional technique, for example, as disclosed in JP-A-60-236214 and JP-A-60-236215,
As a nucleus that absorbs laser light, there is a technique of forming a thin film of 100 Å or less and then irradiating laser light to perform CVD to form a wiring material. However, according to the experiments conducted by the inventors of the present application, the adhesion strength between the wiring material and the base is insufficient for a thin film of 100 Å or less, the absorption of laser light is insufficient, and the base is overheated to deteriorate the characteristics. It has become clear that it will cause.

[Problems to be solved by the invention]

In the prior art, the following specific problems have not been solved. That is, (1) The deposited and laid wiring may be separated from the surface of the semiconductor device or may be cracked.

(2) When laying wiring, laser light is radiated,
The laser light irradiation overheats the lower layer that is the base of the wiring.

(3) As a result of (2), the deposition process depends on the heat capacity of the underlying lower layer, and if there is an underlying structure made of a material with low heat capacity, the thickness and width of the wiring to be laid will be extremely large. Therefore, it is difficult to keep the wiring width uniform.

The object of the present invention is to solve the above-mentioned problems of the prior art by forming a protective film (insulating film) on the surface of an IC device that has been prototyped and almost completed.
The additional wiring is laid at high speed without damaging the lower layer, and the wiring existing under the insulating film is reliably connected, and the defective portion is specified by connecting with low resistance, or the defective portion is repaired,
It is an object of the present invention to provide a wiring connection method and an apparatus for an IC element, which enables quick evaluation of the characteristics of the IC element and quick design change.

[Means for solving problems]

The present invention, in order to achieve the above object, to the IC element having a fine hole formed so that each wiring surface is exposed in the insulating film of the upper layer in each of a plurality of locations requiring connection, At least on the inside of each hole and on the insulating film between each hole, it has conductivity and absorbs laser light 100Å ~ 1000Å
A thin film forming step of forming a thin film having a thickness of, along a desired path on the thin film formed on the thin film formed inside each hole in the thin film forming step and on the insulating film between each hole, An additional wiring forming step of forming an additional wiring for connecting the exposed wirings by irradiating a laser beam while supplying a metal carbonyl compound gas or a metal halogen compound gas to deposit a conductive metal, and the additional wiring forming step And a removing step of removing an unnecessary portion of the thin film by etching after forming the additional wiring by the method.

In addition, the present invention is an IC element having fine holes formed in the upper insulating film at each of a plurality of locations requiring connection so that each wiring surface is exposed so that the oxide and A cleaning step to remove contaminants,
ICs that have been cleaned by the cleaning process
For the element, at least on the inside of each hole and on the insulating film between each hole, has conductivity, and absorbs laser light 100Å ~ 1
A thin film forming step of forming a thin film with a thickness of 000 Å, along a desired path on the thin film formed on the thin film formed inside each hole in the thin film forming step and on the insulating film between each hole An additional wiring forming step of forming an additional wiring connecting the exposed wirings by irradiating a laser beam while supplying a metal carbonyl compound gas or a metal halogen compound gas to deposit a conductive metal, and forming the additional wiring A wiring connecting method in an IC element, which comprises a step of removing an unnecessary portion of the thin film by etching after forming an additional wiring in the step.

Further, the invention is characterized in that, in the thin film forming step in the wiring connection method for the IC element, a metal thin film containing a metal as a main component is formed as the thin film by sputtering.

In addition, the present invention is an IC element having fine holes formed in the upper insulating film at each of a plurality of locations requiring connection so that each wiring surface is exposed so that the oxide and Cleaning means for removing contaminants,
ICs that have been cleaned by the cleaning means
For the element, at least on the inside of each hole and on the insulating film between each hole, has conductivity, and absorbs laser light 100Å ~ 1
A thin film forming means for forming a thin film having a thickness of 000Å, along a desired path on the thin film formed on the thin film formed inside each hole by the thin film forming means and on the insulating film between each hole An additional wiring forming means for forming an additional wiring for connecting the exposed wirings by irradiating a laser beam while supplying a metal carbonyl compound gas or a metal halogen compound gas to deposit a conductive metal, and forming the additional wiring. And a removing means for removing an unnecessary portion of the thin film by etching after the additional wiring is formed by the means.

[Action]

With the above structure, the additional wiring is laid at high speed on the surface of the protective film (insulating film) of the IC element, which is almost completed as a prototype, without damaging the lower layer (especially the diffusion area). The wiring under the film) can be connected reliably and with low resistance to characterize the defective part, or repair the defective part to speed up the characteristic evaluation and design change of the IC element. .

〔Example〕

FIG. 1 shows the overall construction of a wiring laying apparatus which is an embodiment of the present invention.

The load lock chamber 1 is connected to the main chamber 3 via a gate valve 2 and can be evacuated by vacuum pumps 4 and 4'via pipes 5 and 5'and valves 6 and 6 ', respectively. The load lock chamber 1 is provided with a sample stage 8 and an upper electrode 9 for writing a wafer 7 (or a chip if necessary), and a valve 10 for adjusting the flow rate.
It is connected to an Ar gas cylinder 12 via a pipe 11. In addition, a wafer 7'is placed in the main chamber 3 and XY
A movable stage 13 is installed in −Z−θ and is connected to a CVD source gas cylinder 16 via a flow rate adjusting valve 14 and a pipe 15. Further, the main chamber 3 is provided with a window 17 for transmitting a laser beam, and a laser beam 19 emitted from an Ar ion laser oscillator 18 is condensed by an objective lens 21 via a laser optical system 20 and irradiated onto the wafer 7 '. It can be configured. A TV camera 22 is attached to the laser optical system 20 so that the surface of the wafer 7'can be observed by a monitor 23.

Next, the function of each part and the wiring forming procedure according to the present invention will be described.

In the wafer 7, windows are previously formed in the passivation film and the interlayer insulating film at the portions where wiring is to be laid and connected.
Place the wafer 7 on the sample table 8 in the load lock chamber 1,
After sealing, the valve 6'is opened and the inside of the load lock chamber 1 is evacuated to 1 x ^10-7 Torr or less by the vacuum pump 4 '. At this time, the degree of vacuum is 1 × 10 ⁻⁵ Torr, but it is acceptable depending on the case.

After that, the flow rate adjusting valve 10 is opened, Ar gas is introduced from the Ar gas cylinder 12 into the load lock chamber 1, and the Ar gas pressure becomes several.
Adjust valve 10 to achieve mTorr. In this state, high frequency power from a high frequency power source (not shown) is applied to the sample table 8. At this time, the upper electrode 9 is kept at the ground level.
As a result, the sample table 8 and the wafer 7 and the upper electrode 9
Ar plasma is generated and Ar ⁺ ions sputter the surface of the wafer 7. As a result, the pollution sources (moisture, dust, dirt) adhering to the surface of the wafer 7 are removed, and the oxide film formed on the wiring surface due to being exposed to the atmosphere is also removed.

Then, high frequency power is applied to the upper electrode 9 to switch the sample stage 8 to the ground level. A Cr target was installed on the upper electrode and was generated by applying high frequency power.
The Ar ⁺ ions in the Ar plasma sputter the Cr target, causing Cr atoms to fly out and adhere to the surface of the wafer 7. As a result, a Cr film having a thickness of several 100 to 1000 Å can be formed. This effect can be obtained when the film thickness of Cr as the buffer film is about 300 Å, and the adhesion to the base (semiconductor device surface) is good even if the film thickness is increased to about 1 μm. If it is necessary to remove the buffer film in the subsequent process, the passivation film (SiO ₂ ) on the underlying semiconductor device surface and the thickness of the repair wiring formed on the semiconductor device surface can be adjusted by the etching process in the subsequent process. The film thickness of the buffer film is determined depending on whether or not the film may be removed.

Incidentally, it is not necessary to provide a buffer film on the entire surface of the semiconductor device, and if a mask means is appropriately provided and the buffer film is formed only at a place where wiring needs to be laid and its vicinity, the subsequent etching process will be somewhat easier. Become.

In this embodiment, the passivation film has a thickness of 1 to 2 μm, the repair wiring such as Mo described later has a thickness of 0.2 to 2 μm, and Cr as the buffer film has a thickness of 500 Å. It does not affect the characteristics of the device.

If a Mo target is used for the upper electrode 9, Mo can be formed as a buffer film. In this case, the Mo film thickness also needs to be about several hundred to 1,000 Å depending on what kind of means is used in the subsequent etching process.

After forming the buffer film, the valve 10 is closed to evacuate the inside of the load lock chamber 1 to about 1 × 10 ⁻⁷ Torr, the gate valve 2 is opened, and the wafer 7 on which the Cr film is formed is transferred to the XY inside the main chamber 3. -Z-θ Move to above stage 13 and close gate valve 2. Objective lens for laser focusing via window 17
21 and the TV camera 22 and the monitor 23 move in the Z direction to adjust the focus and also adjust in the θ direction. After that, a certain position (for example, a target mark) on the semiconductor device where the wiring is to be laid and a marker (for example, an intersection of the electronic lines) on the monitor 23 are made to coincide with each other, and the XY stage 13 is driven according to the designed size. Then, the marker is matched with the portion requiring connection, that is, the passivation film and the portion where the window is formed in the interlayer insulating film to expose the wiring. This marker is the focus position when the laser light 19 is irradiated.

The laser CVD technique used in the present invention decomposes and deposits the CVD source gas floating in the vicinity of the heat generation position by the thermal energy generated at the laser light irradiation position. In this embodiment, since the semiconductor device is not heated (preheated), the film thickness of the wiring material provided by laser CVD is about 2 μm at most.

The valve 14 is opened, and the CVD gas is introduced from the CVD source gas cylinder 16 through the pipe 15 into the main chamber 3, and
The valve 6 is closed to confine the CVD gas at a constant pressure. Here, Mo (CO) ₆ (molybdenum carbonyl) is used as the CVD gas, and the pressure is adjusted to about 0.1 Torr.
If necessary, an inert gas such as Ar or He may be introduced to raise the pressure to near atmospheric pressure. Also, since Mo (CO) ₆ is a white solid at room temperature and has a low vapor pressure due to sublimation,
It is necessary to heat the cylinder 16, the valve 14, and the pipe 15 (not shown).

Here, an Ar laser 19 is oscillated by an Ar laser oscillator 18 and is focused by a laser optical system 20 and an objective lens 21, while a hole is formed on a wafer 7'through a window 17 and a wiring is exposed (hereinafter, referred to as a window. The inside is called) and the laser beam is irradiated. Depending on the laser output, Mo can be deposited inside the window within a few seconds to a few tens of seconds. After completely embedding it in the window, the laser light 19 is blocked by a shutter (not shown), and the stage 13 is moved by a design dimension or a preset dimension by a controller (not shown) to form a pair. Match the marker to the part to be connected (the part where the wiring is exposed).
After the alignment is completed, the shutter is opened, laser light 19 is irradiated, and Mo is embedded inside the window.

Although depending on the source gas used for laser CVD, carbon C may be mixed as an impurity in the wiring material after the laying, but this can be improved by annealing. The deposited wiring material has a surface state capable of sufficiently absorbing laser light, and annealing is performed after exhausting the raw material gas for CVD.

When connecting at a plurality of points, the above operation is repeated, and when filling of all the windows is completed, connection between the filled portion and the filled portion, that is, wiring formation is performed. First, after aligning one hole-filled portion, while irradiating the laser beam 19, the stage 13 is moved at a constant speed along a preset path to form a Mo wiring. Then, when the Mo wiring reaches the other filled portion while forming the Mo wiring, the irradiation of the laser beam 19 is stopped. When laying a plurality of wirings, the above operation is repeated. Note that these hole filling and wiring formation are achieved by turning on / off the laser light 19 and moving the stage 13, but by inputting points to be connected in advance as coordinates, normal sequence control, numerical control or The combination can be performed automatically.

In this embodiment, Mo (CO) ₆ is used as the CVD source gas,
Although an example of attaching wiring was shown, Cr (CO) ₆ , W as gas
(CO) ₆ , Ni (CO) ₄ and metal carbonyl compounds, Mo
Metal halide compounds such as F ₆ and WF ₆ can be used, and the process is not particularly changed.

After wiring is completed, open valve 6 and Mo (CO) ₆
Is discharged. After exhausting to about 10 ⁻⁷ Torr, the gate valve 2 is opened and the wafer 7 ′ is moved onto the sample stage 8 in the load lock chamber 1. After closing the gate valve 2, the valve 10 of the Ar gas cylinder 12 is opened to introduce Ar gas into the load lock chamber, and the Ar gas pressure is adjusted to be maintained at several mTorr. After that, the upper electrode is set to the ground level, high frequency power is applied to the sample stage 8 to generate Ar plasma, and the surface of the wafer 7 is sputtered with Ar ⁺ ions. As a result, the wafer 7
The Cr film as the buffer film formed on the surface can be removed. The surface of the Mo film formed by laser CVD is also affected by spattering, but since the Mo wiring is usually formed to have a film thickness of 0.2 to 2 μm, it is a problem if the Cr film of several 100 to 1000 Å is removed. do not become.

In addition, it has been empirically obtained that a film thickness of 100 Å or more is required as the buffer film in order to improve the adhesion.

By completing these processes, the required wiring could be laid on the wafer.

Here, the wiring laying direction of the present invention will be described in detail with reference to FIG. FIG. 2 (a) shows a cross section of a wafer on which a semiconductor device requiring wiring is mounted.

In the present invention, a wafer on which a large number of semiconductor devices are mounted may be directly subjected to wiring installation, or a chip on which one semiconductor device is mounted may be targeted.

A first layer of Al wiring 34 is formed on a Si substrate 30 (FIG. 2A) via a SiO ₂ film 31, and a passivation film 35 for protecting the wafer is further formed thereon. Further, in the portion to be connected, a part of the passivation film 35 and the interlayer insulating film 33 is removed so that the Al wiring is exposed, and a hole (window portion) 36,
36 'is formed. These holes 36, 36 'are formed by etching using a resist process or by sputtering by ion beam focusing and irradiation by an ion beam irradiation means (not shown). By exposing the surface of the exposed Al wiring to the atmosphere, oxide films 37, 37 'are generated, and reaction products generated during other processes, dirt, or a pollution source 3 such as moisture are generated.
8,38 'is attached to the surface. The oxide films 37, 37 'cause an increase in the connection resistance of the wiring, a connection failure, and a pollution source 38, 3'.
8'causes a decrease in the adhesion of the installed wiring.

Therefore, as shown in FIG. 2B, the oxide films 37, 37 'and the pollution sources 38, 38' are removed by sputter cleaning. Thereafter, as shown in FIG. 2 (c), the film 39 having good adhesion to the passivation film 35, good conductivity, and high absorption rate of laser light (specifically, chromium without exposure to the atmosphere). A film is formed on the entire surface by a sputter with a thickness of several 100 to 1000Å. Then, the holes 36 and 36 'are first filled with Mo by converging and irradiating an Ar laser in a Mo (CO) ₆ (molybdenum carbonyl) gas atmosphere. Then, the wafer is moved while irradiating the Ar laser beam between the holes 36 and 37 'to form the Mo wiring 40 as shown in FIG. 2 (d). Then, by removing the unnecessary Cr film, the laying is completed as shown in FIG.

Here, Ar laser light is used as a laser high source, but any laser plateau having a wavelength that can be absorbed by the buffer film and converted into heat can be used. However, continuous oscillation is preferable. For example, krypton Kr laser, YAG laser (including harmonic oscillation), and CO ₂ laser if the size of the processed part allows.

Further, the Cr film 39 has a transmittance of about 14% for Ar laser light when the film thickness is 300 Å, and about 2% when the film thickness is 600 Å, and the transmittance does not change extremely to other laser light sources. It is possible to prevent thermal influence due to laser irradiation on the base.
Further, the Cr film 39 absorbs laser light and generates heat, and a decomposition reaction occurs there to deposit the Mo film, so that the influence of the lower layer such as the passivation film thickness and the presence or absence of Al wiring is small, and the film thickness of the Mo wiring 40 is small. ， The change of wiring width is also small. Furthermore, the Cr film itself is Al
Since the reflectance is lower than that of the wiring and the thermal conductivity is also small, the Mo wiring 40 can be formed with a lower laser output than when the Cr film 39 is not formed, and can be formed at a higher speed with the same output. . Further, since a series of steps can be processed in the same apparatus, an oxide on the surface of the Al wiring 32 or an oxide on the surface of the Cr film 39 is not newly generated, and a good wiring having a small connection resistance can be laid.

In this embodiment, spats / etching was performed to remove unnecessary portions of the Cr film previously formed on the entire surface.
Even if it is taken out into the atmosphere in the state shown in FIG. 2 (d), there is no particular inconvenience. Therefore, the unnecessary Cr film can be removed by the wet etching method. That is, for example, as an etching liquid, water 1 is added to cerium nitrate and ammonium nitrate Ce.
It is possible to remove a 500Å Cr film by using 200g of (NO ₃ ) ₄ 2NH ₄ NO ₃ dissolved and immersing it for about 30 seconds at room temperature.

Next, another embodiment of the wiring installation device of the present invention is shown in FIG. The same parts as those in FIG. 1 are indicated by the same numbers.

The road lock chamber 45 is connected to the main chamber 46 by the gate valve 2. Vacuum pumps 4, 4'for piping 5,
The structure is such that exhaust can be performed through 5'and valves 6,6 '. The load lock chamber 45 is provided with a sample table 47 for mounting the wafer 7 and an upper electrode 48, and is further connected to the Ar gas cylinder 12 via a valve 10 and a pipe 11 for adjusting the flow rate. Further, a wafer 7'is placed in the main chamber 46, and a stage 49 which is movable in X-Y-Z-.theta. Is installed, and is placed in an Ar gas cylinder 12 'through a flow rate adjusting valve 10' and a pipe 11 '. Further, it is connected to a CVD source gas cylinder 16 via a valve 14 and a pipe 15. Further, the main chamber 46 is provided with a window 17 for transmitting a laser beam, and a laser beam 19 oscillated from an Ar ion laser oscillator 18 can be condensed by an objective lens 21 via a laser optical system and irradiated onto the wafer 7 '. It is composed. Further, the main chamber 46 is provided with an upper electrode 50 having a target for sputtering.
The Ar gas cylinder 12 ′ may be shared with the Ar gas cylinder 12.

In the above-mentioned structure, the wafer 7 is placed on the sample table 47 in the load lock chamber 45, and after sealing and exhausting, Ar gas is caused to flow so as to have a pressure of several mTorr, the upper electrode 48 is set to the ground level, and the sample table 47 is placed. A high frequency power is applied to the surface of the wafer 7 to clean the surface of the wafer 7 by sputtering Ar ⁺ ions.
At the same time, the oxide film on the surface of the Al wiring exposed for connection is also removed. Then, the valve 10 is closed, the valve 6'is opened, and the vacuum pump 4'is sufficiently evacuated. After that, the gate valve 2 is opened, and the wafer 7 is moved onto the stage 49 in the main chamber 46 by a transfer means (not shown).
At this time, the stage 49 is located below the upper electrode 50 provided with the target for sputtering.

Here, the gate valve 2 is closed, the valve 11 'is opened, Ar gas is introduced from the Ar gas cylinder 12', and high frequency power is applied to the upper electrode 50 while adjusting the pressure to several mTorr. Stage 49 is at earth level. This causes Ar ⁺ ions to sputter the target, which in turn causes the target to
Cr atoms adhere to the wafer 7'to form a Cr film.

Then, after forming a film with a predetermined thickness (several hundred to 1000Å), the valve 11 'is closed, the Ar gas is exhausted, and then the valve 14 is opened to introduce the Mo (CO) ₆ gas from the CVD source gas cylinder 16 into the main chamber. Then, the valve 14 is closed at a constant gas pressure. The stage 49 moves under the window 17, and the objective lens 21, TV
The surface of the wafer 7'can be observed with the camera 22 and the monitor 23.
Here, after adjusting the Z direction and the θ direction by the stage 49, the focus position of the laser and the target mark in the chip for laying the wiring are moved to XY so as to coincide with each other. According to the above dimension, the stage 49 is moved to match the laser irradiation position with the portion requiring connection, that is, the passivation film and the portion where the window (hole) is formed in the interlayer insulating film and the wiring is exposed.

Here, the laser light 19 is oscillated from the Ar laser oscillator 18, and while being condensed by the laser optical system 20 and the objective lens 21, the laser 19 is applied to the inside of the hole through the window 17. As a result, Mo is deposited inside the hole and embedded. After burying all the holes that require connection as necessary, irradiate the laser beam 19 while moving by the stage 49 between the embedded portions according to the design dimensions or preset dimensions. Connection, that is, the Mo wiring is laid.

After laying all the wiring, open the valve ₆ to discharge Mo (CO) ₆ and move the stage 49 to the gate valve 2 side.
Open gate valve 2 and load wafer 7'to load lock chamber 45
It is moved to the sample table 47 inside. After closing the gate valve 2, while introducing Ar gas from the Ar gas cylinder 12 into the load lock chamber 45, the Ar gas pressure is adjusted so as to be maintained at several mTorr.

After that, high-frequency power is applied to the sample table 47, and the Cr formed on the surface of the wafer 7 is sputtered by Ar ⁺ ions.
Remove the membrane. Naturally, the surface of the Mo wiring is also sputtered, but since the Mo wiring is usually formed to have a film thickness of 0.2 to 2 μm, it does not matter if it is a condition of removing the Cr film of about several 100 to 1000 Å.

The sectional shape in each step by the apparatus shown in FIG. 3 is exactly the same as that described in FIG. 2, and not only the same effect can be obtained but also the wet etching step is unnecessary.

Next, FIG. 4 shows the overall construction of a wiring laying apparatus which is a third embodiment of the present invention. In FIG. 4, the optical system including the main chamber 3 and the laser oscillator 18 is the same as that in FIG.

A sample table 47 and an upper electrode 48 are installed in the load lock chamber 55, and an Ar gas introduction system 12, 56, 57 and a vacuum exhaust system 4 ',
It is equipped with 5'and 6 ', so that cleaning by Ar sputtering and etching in the final process can be performed. The load lock chamber 55 is connected to the spatter chamber 62 via the gate valve 2 '. The spatula chamber 62 is a sample table 60 fixed to the earth level, an upper electrode 61 for applying a high frequency power to perform a sputtering operation, and a pipe 58 and a valve 59 for supplying an upper electrode Ar gas equipped with a target for spattering. , The vacuum pump 4 ″ is used for exhausting.

After cleaning the surface of the wafer 7 using the sputtering with Ar ⁺ ions in the load lock chamber 55 and removing the oxide on the wiring surface, the wafer 7 is moved into the sputtering chamber 62 using the gate valve 2'and the upper electrode is used as a buffer film. A film is formed according to the target material added to. After that, the wafer 7'is moved onto the stage 13 connected through the gate valve 2 "and wiring is laid by laser CVD. This procedure is the same as the procedure described in the explanation of FIG. 1 and FIG. After the wiring is formed, the wafer 7 ″ moves to the sample stage 47 of the load lock chamber 55 through the gate valves 2 ″ and 2 ′, and the unnecessary film is removed by the spattering process. Wiring installation is complete.

In this embodiment, since the sputtering film forming mechanism and the cleaning mechanism are respectively performed in the dedicated vacuum chambers, there is an effect that mutual contamination is unlikely to occur. Further, since each mechanism is divided, there is an effect that flexibility is increased in providing each mechanism depending on whether the semiconductor device is handled as one chip or is handled for each wafer.

Next, FIG. 5 shows another embodiment of the mechanism portion for forming the buffer film. This is a mechanical portion corresponding to the load lock chamber 1 in FIG. 1, the upper electrode 50 in FIG. 3, and the sputtering chamber 62 in FIG. 4, respectively.
65 is used.

That is, the electron beam 67 emitted from the electron gun 66 causes the crucible.
The sample table by heating and evaporating the evaporation material 69 installed in 68
A metal or semiconductor film is formed on the surface of the wafer fixed to 70. The sample table 70 has a structure in which it can be rotated by a rotary shaft 71, and a wafer that has been sputter-cleaned in the load lock chamber 55 can be rotated through the gate valve 2 ″.
It is moved and fixed on 70. After that, the sample table 70 is rotated by 180 ° and the shutter 72 is opened with the wafer surface facing downwards.
Perform vapor deposition.

As a matter of course, the vacuum pump 73 in the deposition chamber 65
A sufficient degree of vacuum is maintained through the valve 74 and the pipe 75. When the vapor deposition on the wafer surface is completed, the shutter 72 is closed, the sample table 65 is rotated to direct the wafer upward, and the wafer is moved into the main chamber via the gate valve 2 ″.

FIG. 6 shows another embodiment of the mechanism part for forming the buffer film.
Shown as a CVD chamber 80. It can be used instead of the sputter chamber 62 shown in FIG. That is, a sample stage 81 having a heater, a CVD source gas cylinder 82, a valve 83, a pipe 84, and a nozzle 85.
Equipped with a vacuum pump 86, valve 87, piping as an exhaust system
Equipped with 88.

The wafer 7 that has been sputter cleaned in the load lock chamber 55 is moved onto the sample table 81 via the gate valve 2 '. After the wafer 7 is heated to a required temperature by the heater of the sample stage 81, a metal or semiconductor film is formed while flowing the gas from the CVD source gas cylinder 82 through the adjusting valve 83 and the pipe 84 and the nozzle 85 onto the wafer 7. To do. When the required film thickness is formed, close the valve 83 and exhaust sufficiently,
The wafer 7 is moved to the main chamber via the gate valve 2 ″. The subsequent wiring forming process and unnecessary film removing process are the same as those shown in FIGS.
As a result, the same effects as those of the wiring laying apparatus shown in FIGS. 1 and 3 can be obtained.

In the embodiments of the present invention, the configuration and function of each device have been described. For example, the valve is an electromagnetic valve or an electrically operated valve, and the flow control valve is the electromagnetic valve or the air operated valve and a flow control device (mass control device). By using a flow controller, the process from the insertion of the wafer into the load lock chamber to the completion of wiring installation can be performed completely automatically by sequence control or numerical control.

In addition, although the surface cleaning has been described by sputtering with Ar plasma, the focused ion is used to remove the pollution source by ultraviolet light irradiation, reactive ion etching using etching gas, and oxide removal on the exposed wiring surface. Beam removal processing can also be applied.

In addition, film formation for improving adhesion and reducing thermal influence can be realized by CVD using ultraviolet light or infrared light irradiation in addition to sputtering film formation, thermal CVD, vacuum deposition.

Further, although the wiring was laid by laser CVD by moving the stage, the same wiring can be laid by moving the optical system. As the buffer film 39, specifically, a metal such as Mo, Cr, W, or Ni, or a semiconductor such as Si, Ge, GaAs, or polysilicon containing active impurities, or a silicide that is an alloy of metal and silicon is used. is there. These substances are SiO ₂ that covers the surface of the semiconductor device.
Excellent adhesion to passivation film and additional wiring laid by laser CVD. Therefore, the additional wiring is not peeled off from the surface of the semiconductor device, and the additional wiring after laying is not cracked. The buffer film is a laser
Since the absorption rate of the laser light that causes the CVD phenomenon is high, the additional wiring can be deposited without increasing the laser output, and the laser CVD with good controllability can be performed. In other words, additional wiring having a desired width and film thickness can be laid even if the laser beam is scanned at high speed. In addition, since the buffer film has a high absorptivity for laser light, the influence of the material structure of the underlying layer can be mitigated, the width and film thickness of the additional wiring to be laid can be easily kept constant, and the thermal effect on the underlying layer can be greatly reduced. Can be reduced to

〔The invention's effect〕

According to the present invention, an additional wiring is laid at a high speed on the surface of a protective film (insulating film) of an IC element that is almost completed as a prototype, without damaging the lower layer, and wiring between wirings existing under the insulating film is Is connected securely and with low resistance to identify the defective part,
Alternatively, there is an effect that a defective portion can be repaired and characteristic evaluation and design change of the IC element can be quickly realized.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a wiring laying apparatus which is an embodiment of the present invention, FIG. 2 is a diagram for explaining each step of the wiring laying method of the present invention, and FIG. 3 is another embodiment of the present invention. FIG. 4 is an overall configuration diagram of a wiring laying apparatus as an example, FIG. 4 is an overall configuration diagram of a wiring laying apparatus as a third embodiment of the present invention, and FIG. 5 is a diagram showing an embodiment of a buffer film forming mechanism. FIG. 6 is a view showing another embodiment of the buffer film forming mechanism. 1 ... Road lock chamber, 2 ... Gate valve, 3,46 ... Main chamber, 4,4 '... Vacuum pump, 7,7' ... Wafer, 12,12 '... Ar gas cylinder, 16 ... CVD material Gas cylinder, 18 …… laser oscillator, 9,48,50 …… upper electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junzo Higashi, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Inside the Hitachi, Ltd. Institute of Industrial Science (72) Inventor Susumu Aiuchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Company, Hitachi, Ltd., Institute of Industrial Science (56) Reference JP 60-211860 (JP, A) JP 61-147549 (JP, A) JP 60-216555 (JP, A)

Claims (5)

[Claims] 1. An IC device having a fine hole formed in an upper insulating film at each of a plurality of places where connection is required so that each wiring surface is exposed, at least inside and inside each hole. On the insulating film between the holes, a thin film forming step of forming a thin film having conductivity and absorbing laser light and having a thickness of 100Å to 1000Å, and a thin film formed inside each hole in the thin film forming step. And along a desired path on the thin film formed on the insulating film between each hole, while supplying a metal carbonyl compound gas or a metal halogen compound gas, irradiating a laser beam to deposit a conductive metal An additional wiring forming step of forming an additional wiring connecting the exposed wirings; and a removing step of removing an unnecessary portion of the thin film by etching after forming the additional wiring by the additional wiring forming step. I Wiring connection method for C element. 2. The wiring connection method in an IC element according to claim 1, wherein in the thin film forming step, a metal thin film containing a metal as a main component is formed as the thin film by sputtering. 3. An IC device having a fine hole formed in an upper insulating film at each of a plurality of locations requiring connection so as to expose the surface of each wiring is cleaned to remove an oxide and an oxide. For the cleaning process for removing contaminants and for the IC element that has been cleaned by the cleaning process, at least the inside of each hole and the insulating film between the holes have conductivity and absorb laser light. Yes 100Å ~ 100
A thin film forming step of forming a thin film having a thickness of 0Å and along a desired path on the thin film formed on the thin film formed inside each hole and on the insulating film between each hole in the thin film forming step An additional wiring forming step of forming an additional wiring connecting the exposed wirings by irradiating a laser beam while supplying a metal carbonyl compound gas or a metal halogen compound gas to deposit a conductive metal, and forming the additional wiring And removing the unnecessary portion of the thin film by etching after forming the additional wiring by the process.
Wiring connection method for IC elements. 4. In the thin film step, as the thin film,
The wiring connection method for an IC element according to claim 3, wherein a metal thin film containing a metal as a main component is formed by sputtering. 5. An IC element having fine holes formed in an upper insulating film at each of a plurality of locations requiring connection so as to expose each wiring surface is cleaned to remove an oxide and an oxide. With respect to the cleaning means for removing contaminants and the IC element cleaned by the cleaning means, at least the inside of each hole and the insulating film between the holes have conductivity and absorb the laser beam. Yes 100Å ~ 100
A thin film forming means for forming a thin film having a thickness of 0Å, along a desired path on the thin film formed on the thin film formed inside each hole by the thin film forming means and on the insulating film between the holes An additional wiring forming means for forming an additional wiring for connecting the exposed wirings by irradiating a laser beam while supplying a metal carbonyl compound gas or a metal halogen compound gas to deposit a conductive metal, and forming the additional wiring. And removing means for removing an unnecessary portion of the thin film by etching after forming the additional wiring by the means.
Wiring connection device for IC elements.