JPH02312237A - Semiconductor device, correction of wiring thereof and wiring correcting device - Google Patents

Abstract

PURPOSE:To prevent the cutting part of an Al wiring from being short-circuited by a migration and the like by a method wherein after the wiring of a semiconductor device is corrected, the corrected part is covered with an insulating film. CONSTITUTION:An LSI chip, in which a cutting or the formation of a wiring is finished, is put in an atmosphere 73 containing tetra ethyl ortho silicate and ozone and the interior of a cut hole can be filled with an SiO2 film 74 by irradiating the hole with a laser beam 70 or an FIB (a focusing ion beam). Moreover, by scanning the laser beam 70 from the starting point of a wiring route to the end point of the wiring route, an SiO2 film 75 can be formed only on a wiring 72. This cutting, the formation of the wiring and the local film formation of the SiO2 film are repeated according to the need. Thereby, as the end part of the cutting part of the Al wiring is not exposed, there is no possibility that the wiring is short-circuited due to an electro- migration of Al and the like and moreover, as a connecting wiring formed by an FIBCVD method and a laser CVD method is not exposed, a possibility that the wiring is disconnected by a mechanical force at the time of assembly or a heating and the like in the air is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring forming method and apparatus for forming wiring on the surface of a semiconductor device, and a semiconductor device in which wiring is formed by the wiring forming method and apparatus. In particular, the present invention relates to a wiring repair method and apparatus suitable for identifying the location and cause of a defect that partially exists in a prototype semiconductor device and repairing the defect, as well as a semiconductor device.

[Conventional technology]

2. Description of the Related Art In order to improve the performance and speed of semiconductor devices, semiconductor devices are becoming smaller and more highly integrated. Along with this,
Developing semiconductor devices is becoming more difficult, leading to longer development periods. This situation indicates that a cut-and-try circuit fabrication technique is necessary for LSI design as well. In other words, you can identify a defective part on a chip that does not work satisfactorily with conventional designs, cut the wiring existing in that part, route the wiring to an arbitrary location, or repair the defective wiring to create a temporary solution. If a semiconductor device that can operate perfectly is manufactured, subsequent characteristic evaluations and design changes can be quickly performed, and it is also possible to ship the device as a technical sample to users as is.

On the other hand, as a conventional technology, for example, Semiconductor World 19
As described in the September 1987 issue, pages 27 to 32, after drilling holes in the passivation and interlayer insulation film on the LSI chip surface using FIB (focused ion beam) and exposing the wiring, CVD Same <FI after introducing gas
A method of forming metal wiring using H is introduced.

Also, the Extended Abstracts on the Seventeenth Conference on Solid State Devices and Materials Tokyo (
1985) pp. 193-196 (Extend
ed Abstracts of the 17th
Conference 5solid 5tate
1) avicea and Materials, '
pokyo.

1985 pp. 193-196), a method is introduced in which Mo wiring is formed on a Si-81 substrate coated with Sin using the CVD technique.

In addition, as prior art, Japanese Patent Application Laid-Open No. 62-229956, Japanese Patent Application Laid-open No. 62-229957, 1988 Autumn Proceedings of the Society of Applied Physics 1988.10. p534 is known.

[Problem that the invention seeks to solve]

The above first prior art or the first prior art and #I2
This combination of conventional techniques makes it possible to cut unnecessary wiring and form additional wiring, thereby making it possible to repair an LSI chip that does not function due to design or process defects and obtain a fully operational LSI. However, the LSI chip obtained in this manner has a problem in that sufficient reliability cannot be obtained.

The purpose of the present invention is to cut any wiring on a semiconductor device, form a wiring with a constant thickness and width with excellent adhesion, and connect with low connection resistance at the connection part, and to eliminate defective parts of the semiconductor device. It is an object of the present invention to provide a highly reliable wiring repair method and apparatus, and a semiconductor device, which enable identification of faulty parts, characteristic evaluation by repairing defective parts, speeding up of design changes, and shipping of repaired LSIs.

[Means for solving problems]

The above object is achieved by forming an insulating film on the cut portion and the formed wiring.

That is, regarding the first problem, for example, SiO! By embedding the second and third problems, for example, S
By forming iO,M, the fourth problem can be solved, for example, in S10! after forming a through hole in the upper layer wiring. All of these problems can be solved by re-forming a connection hole to the lower layer wiring and then connecting it.

[Effect]

Tet the LSI chip after cutting or wiring formation.
ra Ethyl 0rtho 5ilicata
and placed in an ozone atmosphere. Laser (or F
By irradiating with IB), the inside of the hole can be filled with Sin. Furthermore, by scanning the laser beam from the start point to the end point of the wiring path, the 5ifl film can be formed only on the wiring. Cutting/wiring formation/Sin.

By repeating the local film formation (including filling in holes) as necessary, the above problem can be solved, and the reliability of the modified LSI can be ensured.

That is, according to the present invention, since the M wiring holding portion of the cut portion is not exposed, there is no risk of short circuiting due to M electromigration or the like. Furthermore, since the connection wiring formed by FIBCVD or laser CVD is not exposed, there is no risk of disconnection due to mechanical force during assembly or heating in the atmosphere. Furthermore, even if connection wirings cross each other, it can be corrected. Further, even when connecting the lower layer wiring in a portion where the upper layer wiring and the lower layer wiring overlap with another wiring, it is possible to prevent the upper layer wiring and the lower layer wiring from being short-circuited.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a wiring installation device that is an embodiment of the present invention.

The load lock chamber 1 is connected to the main chamber 3 via a gate valve 2, and is configured to be evacuated by a vacuum pump 4.4' via piping 5, 5' and a valve 6.6'. There is. The wafer 7 is in the load lock chamber l.
Sample stage 8 and upper part 1 for placing the (or chip as required)! An E electrode 9 is provided, and an Ar gas cylinder 12 is provided via a valve 10I piping 11 for flow rate adjustment.
It is connected to the.

In addition, a wafer 7' is placed in the main chamber 3 and
A movable stage 13 is installed in Y-Z-σ, valves 14, 15, 30, 3i, and piping 1 are installed for adjusting the flow rate.
6.1? , 32.CVD1 for tesoresole wiring through 33
Material gas cylinder 1g, Ar gas cylinder 19, Cv for insulation film
The D material gas cylinder pair is connected to the false gas cylinder 35. Further, an ozone generator 36 is installed in the middle of the piping. Furthermore, an ion beam optical system 20 is installed in the main chamber 3, and is configured to perform sputtering processing by finely focusing metal ions emitted from a liquid metal ion source and scanning a certain area, for example. Further, the main chamber 3 is provided with a sputtering upper electrode 21 having a sputtering target. Furthermore, a window 22 for transmitting laser light is provided, so that the laser light 24 oscillated from okara from the Ar ion laser oscillator can be focused on the objective lens via the laser optical system 5 and irradiated onto the wafer 7'. There is. The laser optical system 25 has a T
A V-camera 27 is attached so that the surface of the wafer 7' can be observed through a monitor 4.

Next, the functions of each part and the procedure for forming wiring according to the present invention will be explained.

The wafer 7 on which wiring is to be formed, including cutting unnecessary wiring, is placed on the sample stage 8 in the load-lock chamber 1 and sealed, and then the valve 6 is opened and the vacuum pump 4 is used to move the wafer 7 into the load-lock chamber 1. is evacuated to below lXIF'Torr. At this time, even a degree of vacuum of 10-' Torr is permissible in some cases.

Thereafter, the flow rate vI4JI valve 10 is opened, and Ar gas is introduced into the load lock chamber 1 from the Ar gas cylinder 12.

The valve 10 is adjusted so that the Ar gas pressure is several m1 orr. In this state, high frequency power from a high frequency source (not shown) is applied to the sample stage 8. At this time, the upper electrode 9 is kept at ground level. As a result, Ar plasma is generated between the sample stage 8, the wafer 7, and the upper electrode 9, and the r+ ions sputter the surface of the wafer 7. This removes contamination sources (moisture, dust, dirt) adhering to the surface of the wafer 7.

Thereafter, the application of high frequency power is stopped, the valve 10 is closed, and the valve 6 is opened to exhaust the Ar gas in the load lock chamber 1. Thereafter, the gate valve 2 is opened and the wafer 7 is transferred to the main chamber 3 by a transfer mechanism (not shown).
-z-〇 Place it on the stage 13. At this time, the inside of the main chamber 3 is maintained at a high vacuum of about I x 10-'Torr.

The wafer 7' is provided with a window 22 for laser transmission by the stage 13.
2. While being moved directly below and observing with the objective lens 26, TV camera n, and monitor 4. Adjust in the θ direction. After that, align the base position (target mark or specific part of the chip) of the chip where wiring is to be formed,
The stage 13 is driven to move directly below the ion beam optical system 20. Here, preliminary alignment was performed using the laser optical system 5, objective lens 26, TV camera 27, and monitor path, but it is not necessary. You can go while doing it.

As shown in Figure 2, the ion beam optical system is attached to the ion beam @(
For example, a liquid metal ion source (such as Ga) 41, an extraction electrode 42 provided at the bottom thereof, an electrostatic lens 43, a blanking electrode material, a deflector electrode 45, a secondary electron detector 46,
It consists of an electronic shower 47.

By applying a high voltage to the extraction electrode, the ion source 4
A metal ion beam 48 (Ga ions in the case of a Ga ion source) is emitted from 1 and is 0.1 to 0 by electrostatic lensing.
．． It is focused to 5 μmφ and irradiated onto Ueno 7'.

At this time, by scanning the ion beam using the deflector electrode 45, sputtering processing is performed in a certain area. Additionally, a monitor 49 monitors the signal obtained from the secondary electron detector 46 in synchronization with the signal applied to the deflector electrode 45.
As shown above, the surface of the sea urchin haf' can be observed as a scanning ion microscope image. Here, the electron shower 47 is such that the surface of the chip (wafer) is exposed to the ion beam 4.
This is to prevent the band 8 from forming a straight band '1'. In addition, the heating power source of the ion source 41, each electrode 42, 4
4, 45, electrostatic lens 43, K for electronic shower 47
A is not shown. Scanning ion microscope % on monitor 49!
The reference position of the chip is aligned, for example, with the center of the optical axis of the ion optical system 20 while looking at the L mirror image. Thereafter, the stage device 3 is driven according to the design data to move to the wiring position to be cut or to the wiring position to be connected. At this time, the ion beam is bent by the blanking 1 and others 44 and does not reach the chip.

When the movement is finished, the optical axis when not deflected is the center.
In the case of cutting, the scanning area is set wider than the wiring width (but within the range where adjacent wiring is not irradiated), and in the case of connecting, the scanning area is set to be about the same as the wiring width. irradiate for the required time. The irradiation time can be set by measuring the processing speed in advance,
A means for monitoring the machining depth may also be used. By repeating the ion beam processing and the movement of the stage 13, the necessary cutting of the wiring and the opening of the window to the wiring to be connected are completed. Note that although this embodiment has described observation using secondary electrons by ion beam irradiation, observation using secondary ions can also be used in combination. In particular, a method using secondary ions is effective as a means of monitoring the machining depth, but it will not be discussed further here.

Next, as shown in FIG. 1, the stage 13 is driven to move the wafer 7' directly below the sputtering electrode 21. A gate valve is provided at the opening portion through which the main chamber 3 is irradiated with the ion beam, and is closed when the ion beam irradiation is completed to keep the ion beam optical system 20 in a vacuum. Inside the main chamber 3 is a flow rate adjustment valve 15
(FIG. 1), Ar gas is introduced from a cylinder 19 through a pipe 17 and adjusted by a valve 15 so that the Ar gas pressure is several m'forr. A Cr target is installed on the sputtering electrode 21, and high frequency power is applied to this, and the stage 13 is maintained at the ground level. Ar + ions in the Ar plasma generated by the application of high-frequency power sputter the Cr target, causing Cr atoms to fly out and adhere to the surface of the sea urchin huff. This results in the number 10
A Cr film of about 0 to 1000 layers can be formed. The film thickness of Cr as this buffer film can exhibit the effect of about 300 layers, and even if it is as thick as about 1Aw, the adhesion to the underlying layer (the surface of the semiconductor device) is good. If the buffer film needs to be removed in a later process, the thickness of the buffer film will depend on how much the wiring film formed on the surface of the semiconductor device can be removed in the later etching process. will be decided.

Note that it is not necessary to apply the buffer film to the entire surface of the semiconductor device, and a masking means may be provided as appropriate to form the buffer film only in and around the locations where wiring is required.

In this example, the passivation film (5il1 etc.) is 1
~2 μm, since Cr as a buffer film is 500,
Even if the etching is applied a little more strongly, the characteristics of the semiconductor device will not be affected.

If MO metal or TL metal is used for the upper electrode 9, MO or T1 can be formed as a buffer film.

In this case, the film thickness of Mo or T1 needs to be determined as appropriate, depending on what means is used for the subsequent etching step, and can range from several hundred to a thousand.

After forming the buffer film, the valve 15 is closed and the main chamber 3
The inside of the chamber is evacuated to about l x 10-' Torr, and the stage 13 is driven to move the wafer 7' directly below the window 4. Through the window n, the laser condensing objective lens 26, the TV left camera 7, and the monitor 4 are connected. A certain position (for example, a target mark) on the semiconductor device where wiring is to be laid is made to coincide with a marker (for example, the intersection of electronic lines) on the monitor. Then, drive the X-Y stage 13 according to the designed dimensions,
The marker is aligned with a portion that requires connection, that is, a portion where a window is formed in the badge-base film and, if necessary, an interlayer insulating film to expose wiring. This marker uses laser light 19
This is the condensing position when irradiating.

The laser CVD technology used in the present invention decomposes the CVD raw material gas adsorbed on the chip (wafer) surface and the CVD raw material gas floating near the heat generating position using thermal energy generated at the laser beam irradiation position. It is then deposited.

The valve 14 is opened to introduce CVD gas into the main chamber 3 via the CvDIIK source gas bomber gas cylinder 186, and the valve 6' is closed to confine the CVD gas at a constant pressure. Here, Mo(Co) is used as CVD gas.
)s (molybdenum carbonyl), 0.1 Tor
Adjust so that the pressure is around r. Note that, if necessary, an inert gas such as Ar or He may be introduced to raise the pressure to near atmospheric pressure. Also, Mo(CO).

Since it is a white solid at room temperature and has a low vapor pressure due to sublimation, it is necessary to heat the cylinder 18, valve 14, and piping 16. (Not shown) Here, the Ar laser beam is oscillated by the Ar laser oscillator 4, and while being focused by the laser optical system 4 and the objective lens 26, a hole is drilled on the wafer 7' through the window 4 to expose the wiring. (hereinafter referred to as the inside of the window) is irradiated with the laser light. Although it depends on the laser output, Mo can be deposited inside the window in several seconds to several tens of seconds. After completely filling the inside of the window, the laser beam a is blocked by a shutter (not shown), and the stage 13 is moved by a design dimension or a preset dimension by a control device (not shown) to form a pair. Match the marker with the part to be connected (the part where the wiring is exposed). After the alignment is completed, the shutter is opened and a laser beam is irradiated to fill the inside of the window with MO.

When connecting multiple locations, the above operation is repeated, and once the holes inside all the windows have been filled, the next step is to connect the filled portions to the filled portions, that is, to form wiring. First, after aligning one of the filled holes, the stage 13 is moved at a constant speed along a preset path while irradiating laser light to form Mo wiring. Then, when the Mo wiring reaches the other hole filling part while forming it, the laser beam irradiation is stopped. If multiple wirings are to be laid, repeat the above operation. On the right, these hole filling and wiring formation are achieved by turning on and off the laser beam 19 and moving the stage 13, but by inputting the points to be connected as coordinates in advance, normal sequence control and numerical control can be performed. Alternatively, it can be performed automatically by a combination thereof.

In this example, an example was shown in which Mo(Co)s was used as the CVDm material gas and Mo wiring was laid, but Cr was used as the gas.
(CO)s = W(CO)s, metal carbonyls such as Ni(CO)4, halogen compounds such as MOF@, WF'@, ht(CB)s, Cd(CH
Alkyl compounds such as s)t can be used and the process remains unchanged.

After all wiring installation is completed, open valve 6'M.

(Exhaust cods. Evacuate to about 1ff'Torr, open gate valve 2, and move wafer 7' onto sample stage 8 in load rotator chamber 1. After closing gate valve 2, open the valve of Ar gas cylinder 12. Open 10 and Ar
Gas is introduced into the load lock chamber l, and the Ar gas pressure is several meters.
Adjust so that Torr is maintained. After that, the upper electrode 9 is set to the ground level, high frequency power is applied to the sample stage 8 to generate Ar plasma, and the wafer 7 is exposed to Ar+ ions.
Sputter the surface. Thereby, the Cr film as a buffer film formed on the surface of the wafer 7 can be removed. Note that the surface of the Mo film formed by laser CVD is also scratched by sputtering, but normally Mo
The wiring is formed to a thickness of 0.2 to 2 μm, so it is several hundred
There is no problem if the conditions are such that about 1,000 Cr films are removed.

In addition, in order to improve the adhesion, 1001
It has been empirically determined that a film thickness greater than or equal to the above is required.

After these processes are completed, the wafer 7' is moved to the main chamber 3 again. Inside main chamber 3 is 1 x 10
°'Torr Exhaust to 4 degrees. Here again,
The ion beam is moved directly below the ion beam optical system, and the ion beam is irradiated to the part that requires cutting to sequentially process and cut the passivation film, interlayer insulating film, and wiring from the upper layer. When all necessary cutting has been completed, the wafer 7' is again moved directly below the fourth laser optic.

After forming this 9Q1 connection wiring, cutting was performed again using a focused ion beam.If cutting was performed when forming the connection hole, Cr would also adhere to the inside of the cut hole when a Cr buffer film was formed on the entire surface in the next step. However, this is because it may not be removed by sputter etching. However, this is not the case if isotropic etching can be achieved using assist gas or the like. Furthermore, changes in these procedures do not change the gist of the present invention.

When these processes are completed, the valve 30 of the CVD gas cylinder for insulating film, the valve 31 of the oxygen cylinder 35,
using Tetra Ethoxy 5ilane,
'I'etraEthyl 0rtho 5ilica
te and ozone are introduced into the main chamber 3. Although this mixed gas is not shown, it is effective to supply it to the vicinity of the laser irradiation part through a nozzle. It may be introduced into the chamber 3 until a constant pressure is reached. In addition, since the vapor pressure of TE01 is low, the pipe 32 after the cylinder is heated to 30 to 70° C. if necessary. In the same way as Mo was embedded in the connection hole, the chip (wafer ) The Ar laser beam oscillated by the Ar laser oscillator is focused and irradiated onto the cut portion of the upper M-line through the window 22 using the laser focusing objective lens 26. This allows a few seconds to
Si can be deposited inside the cut portion (hole) in several tens of seconds. After covering the cut portion with Sl, the laser light is shut off by a shutter (not shown), and the stage 13 is sequentially moved by a designed dimension or a preset dimension.
All the cut parts are covered with Si in the same way.

Next, in the same manner as when forming and connecting the Mo wiring, move the stage 13 at a constant speed on the Mo wiring from the starting point (connection hole) to the end point (paired connection hole) while irradiating the laser beam. . As a result, the Mo wiring is covered with SLO, and the Mo wiring is irradiated with laser light again, thereby reducing the specific resistance of the Mo wiring. If multiple wirings are installed, repeat the above operation. After completing these processes, the wafer 7 is taken out through the load lock chamber 1.

Thereby, the necessary wiring can be formed on the wafer, and the wiring is covered with an insulating film. When forming a wiring that intersects with these wirings, the above-described process may be performed once again.

Here, the wiring forming method of the present invention will be further explained in detail with reference to FIG. Figure 3(a) shows that in the load lock chamber 1, contaminants such as moisture adhering to the surface are removed by sputter etching, etc., and the wiring is cut and connection holes are formed by focused ion beam processing using an ion beam optical system. The cross-sectional structure of the completed semiconductor integrated circuit chip is shown. That is, the Sin! formed on the Si substrate 61! Through the film 62, there is a lower layer M wiring ω, a layer insulation film pierced, an upper layer M wiring 65,
A passivation field is formed, and a cut hole 67 and connection holes 68 and 68' are formed by focused ion beam processing. As described above, cutting can also be performed after the wiring is formed.

After that, passivation [
A Cr film that has good adhesion to 66, is conductive, and has a higher absorption rate of laser light than the surface of the M wiring is formed on the entire surface with a thickness of several hundred to a thousand layers using incense and ivy. After that, the connection hole 68.6g was filled with Mo(CO)a (molybdenum carbonyl) as shown in Figure 3 (bl).
The connection holes 68 and 68' are filled with Mo 71 by condensing and irradiating Ar laser beam 70 in an atmosphere of gas 69. Next, as wiring formation, as shown in FIG. 3 (cl), Mo wiring 72 is formed by moving the chip while irradiating Ar laser beam 70 between the large connection side and 6&'. After exhausting the +, the Ar laser beam 70 is again scanned over the Mo wiring 72 in a vacuum 78 as shown in FIG. 3 (di) to improve the resistance value of the Mo wiring 72. It is necessary to increase the laser output by 2 to 5 times when the wiring is formed.

Thereafter, the Cr film formed on the chip surface is removed by sputter etching in the load rotor chamber 1, and cutting is performed as necessary. Next, Sin! to the cutting hole! Figure 3 (
As shown in e), the cut portion is first irradiated with Ar laser beam 70 in TE01 and ozone atmosphere 73 to embed 5int 74. Next, as shown in Fig. 3 (fl), the Mo wiring 7 was formed in an ozone atmosphere 73 with %TEO8 to form a protective film on the wiring.
By scanning the laser beam 70 over 2, only the Mo wiring 72 can be covered with 5t (1175).

Here, it is possible to combine the step shown in FIG. 3(d) (improving film quality) with the step shown in FIG. By omitting the process of T
SiO by irradiating laser light in an EO8 atmosphere! Catch 758
During the formation, the film quality of Mo 1172 can be improved.

Here, the improvement of film quality and the formation of an insulating film will be further explained. For example, the Ar laser beam is φ3μ with an objective lens.
When moving the chip while focusing it around m and irradiating it to the chip in the Mo(CO)s atmosphere, the laser output, Mo (
Although it depends on the CO)s gas pressure, moving speed, and cross-sectional structure of the chip, as shown in Figure 4(a), the heating area expands due to heat conduction, so a laser output of 100 rrW will spread the heating area to a width of 5 to 10 μm.
Mo wiring 72 with a width of 10 to 15 am with a laser output of 200 m
can be formed. Here, if the film quality is improved while moving the laser beam 81 focused at around φ3 μrs on the Mo wiring 72 with a width of about 10 μm in the wiring direction, the film quality cannot be improved over the entire width, but only on the 5 to 7 μm width. It is known that this can be improved. Also, when forming an insulating film on the wiring, if a focused laser beam with a diameter of around 3 μm is irradiated to the center of the wiring while moving in the direction of the wiring, the insulating film The film thickness is small.

Therefore, either the condensing diameter of the laser beam 81' is expanded to the same extent as the wiring width as shown in FIG. 4 (bl), or the laser beam 81# is directed in the width direction of the wiring 82 as shown in FIG. This can be solved by moving in the wiring direction while also scanning.When increasing the condensing diameter, the laser output is increased as necessary.

To scan the laser beam 81'' in the width direction, for example, a laser optical system shown in FIGS. 5 and 6 is used.
As shown in the figure, the laser beam U is transmitted through two galvanometers 92.
, 93 around orthogonal axes, it is possible to scan in the X-Y direction, or scan in a direction perpendicular to the direction of movement of the stage, or synchronize and vibrate both axes to perform circular motion. You can achieve the objective by moving it around the stage while doing so. Also, as shown in Figure 6,
- Deflector 94 that utilizes the electro-optic effect of laser light;
95 (arranged so that the deflection directions are orthogonal), X
- can be scanned in the Y direction and achieve the objective as well.

In addition, in order to expand the spot diameter of the laser beam 81'', a seventh
This purpose can be achieved by moving one of the lenses 96' forming the beam expander in the direction of light rotation as shown in the figure. In other words, when the laser beam is bent by (A) degrees by the mirror 97, focused by the objective lens 98, and irradiated onto the wafer 7', the focal position of the objective lens and the positional relationship for outputting it as parallel light by the beam expander are determined. If the sample surfaces match, conduct wiring formation and hole filling.
Move the lens % position to move the focal position in the optical axis direction (
(out of focus), and as a result, the spot diameter is expanded,
M.

The film quality of the wiring 72 is improved and 5iOti 75 is formed.

In addition to moving the position of the lenses constituting the beam expander, the same effect can also be obtained by inserting and removing a long focal length lens, inserting and removing a transparent flat plate between the objective lens and the sample, and the like.

In the above-described embodiments, the case where the wiring correction device shown in FIG. 1 is used has been described. This allows cutting of wiring, formation of connection holes, filling of holes with conductive material, formation of wiring, and formation of an insulating film in one device, but the present invention is not limited to this. It is clear that even if the respective steps are carried out using separate apparatuses, it is sufficient as long as the wiring is repaired by cutting the wire or forming an additional wire, and then a step of covering the repaired portion with an insulating film is performed.

Also, in the process shown in Fig. 3, even if the process order is changed, such as forming only the connection hole and filling it with Mo, forming the MO wiring, and then cutting the wiring, etc.
It is included as long as it does not depart from the gist of the present invention.

Next, another application of the present invention will be explained according to the @S diagram. This is the part where the upper layer wiring 65 and the lower layer wiring ω overlap,
This is a case where connection is made to the lower layer wiring portion without shorting with the upper layer wiring 65. As shown in FIG. 8(a), the semiconductor integrated circuit is fabricated on a Si substrate 61. Lower layer M wiring ω via the film 62
, an interlayer insulating film B1, an upper layer M wiring 65, and a passivation film are formed. First, a connection hole 107 is formed in the passivation m66 and the upper layer M wiring 65 so that the glabella insulating film □□□ is exposed, and the inside of the hole 107 is filled with 5i01108 as shown in FIG. 8(c).

After that, as shown in FIG. 8(d), a connection hole 107' is formed so that the upper layer M wiring 65 is not exposed, and the lower layer M wiring 63 is formed.
expose. Next, as shown in Fig. 8(e), connect hole 1
07', Mo is buried to form Mo interconnections 71 and 72, and connected to the portions requiring connection. After that, if necessary, a 5in2 film 75 is formed on the Mo wiring 72 to
Protects and insulates the wiring 72. Each of these steps is exactly the same in principle and means as shown in FIG. 3, and it goes without saying that adhesion can be improved by forming a Cr film before filling Mo and forming Mo wiring. Also,
The unnecessary Cr film is appropriately removed by means such as sputter etching.

Furthermore, another application of the present invention is shown in FIG. Figure 9 (a
) shows a cross section of the semiconductor device shown in FIG. 3 after cutting and formation of the connecting MO wiring 72 have been completed. Mo distribution 4
A St film 75 is formed on #72 as a protection film, but this is used here as an insulating film between the eyebrows.

That is, as shown in FIG. 9(b), a Mo wiring 76 is formed on the Mo wiring 72 to intersect therewith. 9th if necessary
As shown in the figure (cl), on this Mo wiring 76, there is a
7 can be formed. A buffer film (Cr film) may be formed to improve adhesion before forming the intersecting MO interconnects 76; in that case, a step of removing the buffer film is required after forming the MO interconnects. .

Further, in the embodiment shown in FIG. 9, an insulating film between the eyebrows was formed to prevent wiring formed by laser CVD from shortening, but the same applies to the case where the insulating film is applied to a chip before forming a passivation film. That is, as shown in FIG.
', 105'' are formed. These M wirings are exposed, and if, for example, a connecting wiring 1IIillO7 is formed between M layouts i 105 and 105' by laser CVD, it will naturally short-circuit with 105'. Wiring 10
M wiring 105' is formed by 1ζ laser CVD before forming 7.
By forming the upper interlayer insulating film 106, short circuits can be prevented.

In addition, although the film 106 is formed locally on Sl in FIG. 1O, it is also possible to form SiO and M over a wider area. In that case, similarly to the chip on which the passivation film is formed, it is necessary to form connection holes using a focused ion beam or the like.

Needless to say, high reliability is ensured by covering the connection wiring 107 formed in this manner with SiO2.

Next, another embodiment is shown in FIG. In the above-mentioned embodiment, the cut portion and the modified wiring are sequentially coated with Si.
However, in this example, a SiO film is formed over the entire repaired area at once.

That is, as shown in FIG.
1 (formed so that the laser beam 120 passes through only the necessary portions), and placed in a positional relationship such that the image of the mask 121 is projected onto the semiconductor chip 7' by the objective lens 122 to form the laser irradiation area. 125 for projection irradiation.

Usually, pads 124, which are electrodes for power supply and signal input/output, are formed on the semiconductor chip 7', and it is necessary to avoid forming an Sl film on these pads. Although not shown in FIG. 11, the chip 7' is placed in a mixed gas atmosphere of TE01 and ozone in a chamber, and is irradiated with laser light 120 through a transmission window. As the laser beam 120, continuous wave and pulse wave Ar lasers, YA lasers, etc.
Any device that can heat the chip surface, such as the fundamental wave of a G laser and its harmonics, or a C02 laser, can be used, and the output is adjusted so that the M wiring formed within the chip will not be damaged.

Note that in this method, a film is formed on the passibasitan film and on the Sl film except in the repaired portion, but this does not cause any problem in terms of the characteristics of the chip 7'.

In the above-mentioned embodiments, the case where only laser CVD is applied to form the connection wiring has been described, but it is also possible to irradiate a focused ion beam or electron beam onto a chip placed in a CVD gas atmosphere. By this,
Similarly, a wiring can be formed, and this wiring can be covered with an insulating film by irradiating the wiring with an electron beam in a CVD gas field for insulation and expansion formation. Furthermore, the film quality of the wiring film can be improved by irradiating at the same time or before forming the insulating film.

〔Effect of the invention〕

As described above, according to the present invention, after the wiring of a semiconductor device is repaired, the repaired portion can be covered with an insulating film, so that the cut portion of the 0M wire will not be short-circuited due to migration or the like. ■Can prevent connection wiring from breaking due to mechanical force, ■Can prevent short circuits when connection wiring crosses, ■Can prevent short circuits with wiring inside semiconductor devices, etc. This is effective, and the reliability of the modified semiconductor device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a wiring correction device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of an ion beam optical system in FIG. 1, and FIG. 3 is a configuration diagram of a wiring correction device according to an embodiment of the present invention. Explanatory diagram of the correct method, 4th
The figure is an explanatory diagram for improving wiring film quality and forming an insulating film, Figures 5 and 6 are explanatory diagrams for laser beam scanning, respectively, Figure 7 is an explanatory diagram for changing the laser spot diameter, and Figures 8 to 10 are diagrams for explaining laser beam scanning. FIG. 11 is an explanatory diagram of a wiring correction method according to another embodiment of the present invention, respectively. 1... Load lock 2... Gate valve 3.
・Main chamber 18...CVD material gas cylinder 34...CVD gas cylinder for insulating film 35...Oxygen cylinder n...Laser oscillator de1
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Claims (1)

[Claims] 1. A semiconductor device characterized in that at least the end face of the internal wiring exposed by cutting is covered with an insulating film to prevent short circuits due to migration of the wiring. 2. A semiconductor device characterized in that additional wiring is formed to connect internal wiring, and at least the additional wiring is covered with an insulating film. 3. Form a conductive buffer film at least on the path where the connection wiring is to be formed, selectively form the connection wiring on it by energy beam CVD, then remove the unnecessary buffer film, and then A method for repairing wiring in a semiconductor device, characterized in that annealing is performed by energy beam irradiation. 4. Forming a connection hole at a desired location on the semiconductor device using an energy beam; Forming a conductive buffer film on the semiconductor device at least on a path where a connection wiring is to be formed;
A process of forming connection wiring on a semiconductor device by energy beam CVD, a process of removing unnecessary buffer films, a process of irradiating the wiring with an energy beam in a vacuum, an inert gas or a reducing gas atmosphere, and an energy beam CVD process. A method for repairing wiring in a semiconductor device, comprising the step of forming an insulating film on the connection wiring by beam CVD, and cutting and connecting the wiring in the semiconductor device. 5. A stage on which a semiconductor device is placed, a chamber for maintaining the semiconductor device in a specific atmosphere, a means for evacuating the inside of the chamber, and a means for supplying a material gas for forming a conductive substance. , means for supplying a material gas for forming an insulating material, means for generating an energy beam for decomposing the material gas for forming the conductive material and the insulating material, and supplying the energy beam into the chamber. A wiring repair device for a semiconductor device, comprising: an optical system for condensing and irradiating light onto the surface of the semiconductor device; and an optical system for observing the chip surface.