JPH0766799A - Clock monitoring circuit - Google Patents

Abstract

PURPOSE:To provide a clock monitoring circuit capable of easily and accurately monitoring excess/omission due to the detection of disconnection of a supplied reference clock and its waveform distortion. CONSTITUTION:A receiving circuit 101 generates a receiving clock S2 from a reference clock S1. A monitoring period signal generating circuit 103 generates a monitoring period signal S4 with a period (t) and a judging period signal S5 with a period T from a sampling signal S3. Counting circuits 104, 106, 107 respectively count the occupation time rates and leading edges of the logic levels '1', '0' of a receiving clock S2, and when these count values satisfy an abnormality judging condition, output respective counted result signals S7 to S9. When the signals S7 to S9 are generated continuously or plural times in the judging period T time, a judging circuit 108 outputs a judged result signal S10 judging the existence of abnormality in the receiving clock S2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock monitoring circuit for monitoring whether or not a clock is normal, and more particularly to a clock monitoring circuit suitable for monitoring a reference clock for synchronization received for establishing network synchronization.

[0002]

2. Description of the Related Art A conventional monitoring circuit of this type is shown in FIG.
The description will be given with reference to the circuit diagram of the clock monitoring circuit shown in FIG. 4 and the timing chart for explaining the operation of the clock monitoring circuit shown in FIG.

This clock monitoring circuit is a 74LS12.
Has a model number such as 2,74LS123, Retriggl
e Monostable Multivibrato
An integrated circuit (IC) 201 with the name r is used. This clock monitoring circuit includes a capacitor C1 having a capacitance value C between the R / C terminal of the IC 201 and a Cext terminal at the ground potential, and a resistor R1 having a resistance value R between the R / C terminal and the + 5V power source. Are connected. In addition, IC201
The A input terminal is grounded and the Clear terminal is supplied with + 5V power. The reference clock S21 to be monitored is
The output signal S22 of the monitoring result, which is supplied to the B input terminal of the IC 201, is output to the Q terminal.

This clock monitoring circuit is used for alarm conditions,
For example, the capacitance value C and the resistance value R are determined based on the condition that it is determined that the reference clock S21 is abnormal when the reference clock S21 is disconnected for 10 consecutive clock cycles. In this condition, I
The C201 generates an output signal S22 having a pulse width tw (= k × C × R: k is a coefficient) with respect to one clock input of the reference clock S21.

Now, when the reference clock S21 is supplied to the B terminal of the IC201, the IC201 newly adds a pulse width tw to the Q terminal each time the reference clock S21 rises.
Only hold the logic level "1". Reference clock S2
When 1 is continuously input to the IC 201, the Q terminal keeps the logic level "1". On the contrary, the reference clock S21 is not input to the IC 201, and as shown in FIG.
When the time tw has passed after the last input of the reference clock S21, the output signal S22 generated at the Q terminal becomes the logic level "0", which means that the disconnection of the reference clock S21 is detected.

[0006]

In this conventional clock monitoring circuit, even if the reference clock surplus or loss occurs due to input abnormality of the reference clock, waveform deterioration, etc., within the fixed period indicated by the pulse width tw. If the normal reference clock is input to, the clock break is not detected. That is,
If at least one rising edge of the reference clock exists at the input end of the clock monitoring circuit within the fixed period indicated by the pulse width tw, the reference clock disconnection is not detected. Therefore, this clock monitoring circuit has a drawback in that it is not possible to detect surplus or loss of the reference clock due to input abnormality or waveform deterioration.

[0007]

A clock monitoring circuit of the present invention is a clock monitoring circuit for monitoring whether or not a supplied clock is normal, and the repetition frequency is at least twice the repetition frequency of the clock. A sampling signal generating circuit that generates a sampling signal, a monitoring period signal of a period t, and a determination period signal having a period T that is n (n is an integer of 1 or more) times the period t are generated in synchronization with the sampling signal. A monitoring cycle signal generating circuit and the cycle t
A first counting circuit which counts the time occupied by the first logic level of the clock in time by sampling with the sampling signal and produces a first count result signal when the count result exceeds a predetermined first value. And the time occupied by the second logic level of the clock in the period t is counted by sampling with the sampling signal, and a second count result signal is generated when the count result exceeds a predetermined second value. A second counting circuit and a rising point at which the second logic level of the clock changes from the second logic level to the first logic level during the period t, and when the counting result exceeds a predetermined third value, A rising frequency counting circuit that outputs a counting result signal of 3,
And a determination circuit that generates a determination result signal that determines that the clock is abnormal when any of the first counting result signal, the second counting result signal, and the third counting result signal occurs.

In the clock monitoring circuit, the determination circuit determines that the abnormality occurs continuously or a plurality of times during the period T in which the period t is a count unit and n is 2 or more. A configuration that produces a result signal can be employed.

Further, the clock monitoring circuit of the present invention is a clock monitoring circuit for monitoring whether or not the supplied clock is normal, and generates a sampling signal whose repetition frequency is at least twice the repetition frequency of the clock. A sampling signal generating circuit for generating a monitoring cycle signal having a cycle t and a determination cycle signal having a cycle T that is n times (n is an integer of 1 or more) times the cycle t in synchronization with the sampling signal. The circuit and the time occupied by the logic level "1" of the clock during the period t are counted by sampling with the sampling signal, and the first counting result signal is output when the counting result exceeds a predetermined first value. A first counting circuit that occurs, an inverting circuit that inverts the polarity of the clock to produce an inverted clock, and And a second counting circuit which counts the time occupied by the logic level "1" of the inversion clock by sampling with the sampling signal and produces a second counting result signal when the counting result exceeds a predetermined second value. , During the time period t, counting the rising points at which the logic level "0" of the clock changes to the logic level "1", and when the counting result exceeds a predetermined third value, a third counting result signal is output. A rising number counting circuit that occurs, an OR circuit that ORs the first counting result signal, the second counting result signal, and the third counting result signal; n is 2
And a determination circuit for generating a determination result signal for determining the clock as abnormal when the logical sum level "1" of the logical sum continuously occurs or occurs a plurality of times during the period T.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The receiving circuit 101 of this clock monitoring circuit
Receives a reference clock S1 supplied from a reference clock generator (not shown) for establishing network synchronization, and outputs a reception clock S2 obtained by waveform-shaping the reference clock S1. The reception clock S2 has two logic levels of "1" and "0". Further, the sampling signal generation circuit 102 generates a sampling signal S3 having a repetition frequency that is at least twice the reception clock S2. The sampling signal S3 is supplied to the monitoring cycle signal generating circuit 103, and the monitoring cycle signal generating circuit 103 generates a monitoring cycle signal S4 having a cycle t and a determination cycle signal S5 having a cycle T that is n (n) times the cycle t. Cause In the clock monitoring circuit of this embodiment, n is 2 or more.

Receive clock S2 and sampling signal S3
And the monitoring cycle signal S4 are supplied to the first counting circuit 104. The counting circuit 104 counts the time (ratio) occupied by the logic level "1" in the reception clock S2 by sampling the sampling signal S3 every t times of the monitoring cycle signal S4, and the counting result is predetermined. When it exceeds the first value, the first counting result signal S7 is output at the logic level "1".

Further, the reception clock S2 is supplied to the inverting circuit 10
The polarity is inverted at 5 to become the inversion clock S6. Inversion clock S6, sampling signal S3, monitoring period signal S4
Are supplied to the second counting circuit 106. Counting circuit 10
6 uses the sampling signal S3 for the time (ratio) occupied by the logic level "1" of the inversion clock S6, that is, the time occupied by the logic level "0" of the reception clock S2 for each cycle t time indicated by the monitoring cycle signal S4. When the counting result exceeds a predetermined second value, the second counting result signal S8 is output at the logic level "1".

The reception clock S2, the sampling signal S3, and the monitoring period signal S4 are also supplied to the rise counter circuit 107. Rising frequency counting circuit 107
Counts the number of rising points at which the reception clock S2 changes from the logic level "0" to the logic level "1" at every cycle t, and when the count result exceeds a predetermined third value, The third counting result signal S9 is output at the logic level "1".

The counting result signals S7, S8 and S9 are supplied to the judging circuit 108. The determination circuit 108 performs a logical sum operation on the count result signal S7, the count result signal S8, and the count result signal S9 with one cycle t as a time unit of the operation. Here, each of the counting circuits 104 and 106 and each of the rising number counting circuits 107 produces at least one of the counting result signals S7, S8 and S9 (determination circuit 108).
Is at least one logic level "1"), it indicates an abnormal state of the reception clock S2 as described later. The determination circuit 108 further determines the determination cycle signal S5.
When the abnormality of the reception clock S2 recognized by the logical OR operation occurs continuously or a plurality of times during the period T obtained from the above, it is determined that the reception clock S2 is abnormal and the determination result signal S10 is output. It should be noted that the reason why the determination circuit 108 does not immediately output the determination result signal S10 even if the abnormality of the reception clock S2 occurs once is to be careful in determining the abnormality of the reception clock S2, and, of course, once the reception clock S2 has occurred. The determination result signal S10 may be generated for the abnormality. In this case, the cycle T of the determination cycle signal S5 supplied by the monitoring cycle signal generation circuit 102 may be equal to the cycle n of the monitoring cycle signal S4.

Needless to say, the clock monitoring circuit of this embodiment is suitable for use as an LSI because all signal processing is digitally processed.

FIG. 2 shows the reception clock S2 in this embodiment.
3A and 3B are timing charts of the sampling signal S3, in which (a) is a normal reception clock S2 and (b) is (a).
FIG. 7C is a diagram in which the sampling signal S3 is superimposed, FIG. 7C is a diagram in which the sampling signal S3 is superimposed on the reception clock S2 in the missing state of the logic level “0”, and FIG.

Referring to FIGS. 1 and 2, in the clock monitoring circuit of this embodiment, the cycle t of the monitoring signal S4 is made substantially equal to one clock cycle of the reception clock S2. The cycle T of the determination cycle signal S5 is set to be twice the cycle t or more.

Further, the first counting circuit 104 receives the reception clock S during the monitoring time t indicated by the monitoring cycle signal S4.
When the occupation time ratio of the logic level "1" of 2 exceeds 95%, the counting result signal S7 is output. Similarly, the second counting circuit 105 outputs the counting result signal S8 when the occupation time ratio of the logic level "0" of the reception clock S2 in the period t exceeds 95%, and the rising number counting circuit 107 similarly outputs the period t. When the number of rises during the time is two or more, the counting result signal S9 is output.

Reception clock S shown in (a) and (b)
2 is in a normal state, and the occupied time of the logic level "1" and the logic level "0" during the period t does not satisfy the output conditions of the count result signal S7 and the count result signal S8, respectively. However, since the occupation time of the logic level "1" of the reception clock S2 shown in (c) exceeds 95%, the counting circuit 104 which has received the reception clock S2 of (c) makes this reception clock S2 in an abnormal state. A count result signal S7 indicating that there is is output.

The rising number counting circuit 107 has a function of counting rising points (points indicated by ∇) where the reception clock S2 changes from the logic level "0" to the logic level "1". The counting circuits 104 and 106 described above
Even if the reception clock S2 shown in (d) is received, since the reception clock S2 does not satisfy the conditions for outputting the count result signal S7 and the count result signal S8, it is determined that the reception clock S2 is abnormal. It is not possible.
However, when the rise counter circuit 107 receives the reception clock S2 shown in (d), the reception clock S2
It is counted that the number of rises of is two or more times within the period t, and since the count result satisfies the determination condition,
A count result signal S9 indicating that the reception clock S2 in (d) is in an abnormal state is output.

The determination circuit 108 outputs a logical sum (O) of the count result signal S7, the count result signal S8, and the count result signal S9 for each cycle t in the cycle T indicated by the judgment cycle signal S5.
R). The logical sum level “1” of this logical sum is the cycle T
If it occurs consecutively or multiple times during the time,
The determination circuit 108 determines that the reception clock S2 is abnormal and outputs the determination result signal S10. The determination circuit 1
08 can reproduce the signal of the cycle t by utilizing the property that the count result signal S7, the count result signal S8 and the count result signal S9 are reset every cycle t, but the monitor cycle signal generating circuit 103 outputs the monitor cycle signal S4. You may receive. Further, the determination circuit 108 may have a protection (activation / cancellation) function against the transmission of the determination result signal S10.

In the present embodiment, an example (FIG. 2 (c)) in which the logic level "0" part of the reception clock S2 is missing is explained. However, the logic level "1" is missing in the reception clock S2. Obviously, the present embodiment can similarly detect an abnormality in the disconnection of the reception clock S2.
Further, it goes without saying that the accuracy of abnormality detection is improved by increasing the repetition frequency of the sampling signal S3. Further, this clock monitoring circuit can change the transmission conditions of the cycle t, the cycle T, and the count result signals S7, S8, and S9, and has great freedom in determining the reception clock abnormality including the determination speed and the determination sensitivity. You can have a degree.

[0025]

As described above, according to the present invention, the logical level "1" and the logical level "0" of the reception clock during the monitoring period t are used by using the sampling signal whose repetition frequency is twice or more of the reception clock. The occupied time of "" and the number of rises of the reception clock are counted, and the abnormality of the reception clock (reception state of the reception clock, missing state, surplus state) is detected by logical processing of these counting results. It has the feature that it can be monitored easily and accurately.

Further, according to the present invention, since the monitoring period t, the abnormality determination period T of the reception clock, and the counting result can be varied, there is a large degree of freedom in the determination condition of the reception clock abnormality including the determination speed and the determination sensitivity. This has the effect of providing a monitoring circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of a reception clock S2 and a sampling signal S3 in the present embodiment, (a)
Shows a normal reception clock S2, (b) shows a sampling signal S3 superimposed on (a), and (c) shows a logic level "0".
The sampling signal S3 is superimposed on the reception clock S2 in the missing state, and (d) shows the reception clock S2 in the surplus state.

FIG. 3 is a block diagram of a conventional monitoring circuit.

FIG. 4 is a timing chart explaining the operation of a conventional monitoring circuit.

[Explanation of symbols]

 101 Reception Circuit 102 Sampling Signal Generation Circuit 103 Monitoring Period Signal Generation Circuit 104 First Counting Circuit 105 Inversion Circuit 106 Second Counting Circuit 107 Rising Time Counting Circuit 108 Judgment Circuit

Claims (3)

[Claims] 1. A clock monitoring circuit for monitoring whether or not a supplied clock is normal, the sampling signal generating circuit generating a sampling signal having a repetition frequency of at least twice the repetition frequency of the clock, and a cycle. t monitoring period signal and n (n
Is a whole number greater than or equal to 1) and a determination period signal having a period T that is a multiple of the period, and a monitoring period signal generating circuit that generates the period signal in synchronization with the sampling signal, A first counting circuit which counts by sampling with the sampling signal and produces a first counting result signal when the counting result exceeds a predetermined first value; and a second logic of the clock during the period t. A second counting circuit that counts the time occupied by the level by sampling with the sampling signal and generates a second counting result signal when the counting result exceeds a predetermined second value; and the clock during the period t. When the rising point at which the second logic level of changes to the first logic level is counted and the counting result exceeds a predetermined third value, A rising frequency counting circuit that outputs a third counting result signal, and if any of the first counting result signal, the second counting result signal, and the third counting result signal occurs, the clock is determined to be abnormal. A clock monitoring device, comprising: a determination circuit that generates a determination result signal. 2. The determination circuit generates the determination result signal when the abnormality occurs continuously or a plurality of times during the period T time in which the period t is a count unit and n is 2 or more. The clock monitoring circuit according to claim 1, wherein: 3. A clock monitoring circuit for monitoring whether or not a supplied clock is normal, the sampling signal generating circuit generating a sampling signal having a repetition frequency of at least twice the repetition frequency of the clock, and a cycle. t monitoring period signal and n (n
Is a whole number greater than or equal to 1) and a monitoring period signal generating circuit that generates a determination period signal having a period T that is a multiple of the period T, and a period occupied by the logic level "1" of the clock during the period t. A first counting circuit that counts by sampling with the sampling signal and that generates a first count result signal when the count result exceeds a predetermined first value; and an inversion that inverts the polarity of the clock to generate an inverted clock. The circuit and the time occupied by the logic level "1" of the inversion clock during the period t are counted by sampling by the sampling signal, and when the counting result exceeds a predetermined second value, the second counting result signal Generating a second counting circuit, and changing the logic level "0" of the clock from the logic level "1" during the period t. A rising number counting circuit that counts the number of rising points and generates a third counting result signal when this counting result exceeds a predetermined third value, the first counting result signal, the second counting result signal, and A logical sum circuit for calculating the logical sum of the third count result signal, and a logical sum level "1" of the logical sum during the cycle T time in which the cycle t is a counting unit and n is 2 or more. A clock monitoring device, comprising: a determination circuit that generates a determination result signal for determining that the clock is abnormal when the clock is continuously generated or a plurality of times.