KR100754707B1 - Clock monitoring apparatus and method in a communication system - Google Patents

Abstract

Disclosed are a clock monitoring apparatus and method for monitoring whether a system clock of a communication system is operating normally. According to an embodiment of the present invention, a board for inputting a preset reference clock, clock synthesizing and outputting a synthesized clock, a plurality of boards having a plurality of output ports, and performing a unique function of a plurality of system clocks An apparatus for monitoring a clock of a communication system, comprising: a clock driver that buffers the synthesized clock and outputs a plurality of system clocks through the plurality of output ports, and inputs all of the plurality of system clocks; And a clock monitoring unit which sequentially determines whether the clocks are normal or abnormal.

Clock Monitoring, System Clock, Monitoring Cycle, Register

Description

Clock monitoring device and method of communication system {CLOCK MONITORING APPARATUS AND METHOD IN A COMMUNICATION SYSTEM}             

1 is a view showing the configuration of a clock monitoring apparatus according to the prior art.

2 is a view showing the configuration of a clock monitoring apparatus according to an embodiment of the present invention.

3 is a diagram illustrating a detailed configuration of a clock monitoring unit shown in FIG. 2.

FIG. 4A is a diagram illustrating an operation timing of clocks output through n output ports of the clock driver illustrated in FIG. 2.

4B is a view illustrating an operation timing of the monitoring cycle clock generator shown in FIG. 3.

5 is a diagram illustrating a processing flow of a clock monitoring operation according to an embodiment of the present invention.

The present invention relates to a clock monitoring apparatus and method for monitoring whether a system clock of a communication system is operating normally.

Code division multiple access (CDMA) mobile communication systems such as the Universal Mobile Telecommunication System (UMTS), all communication systems such as satellite systems, optical transmission systems, switching systems, etc. perform various functions that perform unique functions. Is made of. Since each board of such a communication system is operated by a system clock, a clock monitoring device for monitoring whether the system clock is operating normally is provided in each system.

1 is a view showing the configuration of a clock monitoring apparatus of a communication system according to the prior art. This clock-monitoring device shows an example implemented in a synchronizer board.

Referring to FIG. 1, a conventional clock monitoring apparatus includes a timing module 10, clock drivers 21 to 23, and a clock monitoring unit 30. The timing module 10 inputs a reference clock from a digital office timing supply (DOTS) and synthesizes the reference clock to generate a desired clock. The clock generated by the timing module 10 is inputted to clock driver chips 21 to 23 to generate as many clocks as necessary. The clock driver 21 inputs a clock generated by the timing module 10 and outputs a plurality of clocks. The clocks output from the clock driver 21 are input to the clock driver 22 and the clock driver 23. The clock drivers 22 and 23 output clocks of a predetermined number (eg, 4). That is, the clock driver 22 inputs the clock from the clock driver 21 and outputs the clocks through four output ports (port 1 to port 4), and the clock driver 23 inputs the clock from the clock driver 21. And outputs clocks through the four output ports. The last output port of the output ports of the clock driver 23 is a monitoring port. The clock through the monitoring port of the clock driver 23 is output to the clock monitoring unit 30. The clock monitoring unit 30 inputs a clock through the monitoring port, determines whether the clock is normal or abnormal, and outputs a state determination signal accordingly. The clock normal / abnormal state determination signal by the clock monitoring unit 30 is provided to a CPU (Central Processing Unit) (not shown).

As shown in FIG. 1, the clock monitoring apparatus according to the related art checks whether a clock is normally operated by inputting only one of several outputs of a clock driver to a CPLD, which is a clock monitoring unit, and whether the CPLD is operating normally. Determine and report to the CPU. As it does not monitor the normal operation of all the output clocks as described above, even if the clock input to the clock monitoring device according to the prior art is normal, the normal operation of the other output clocks depending on the assembly state of the printed board assembly (PBA) or component breakage. There is a problem that can not be 100% guaranteed.

Accordingly, an object of the present invention is to provide an apparatus and method for monitoring the normal operation of all clocks used in a communication system.

The present invention for achieving this purpose is to solve the problem that it was not possible to reliably monitor the normal operation of all the output clocks by monitoring only one output clock in the prior art, the normal operation of all output clocks used in the communication system We propose an apparatus and method for reliably monitoring whether or not.

A timing module for inputting a preset reference clock according to the present invention, clock synthesizing and outputting a synthesized clock, and a plurality of output ports, and providing a plurality of system clocks to various boards that perform unique functions. The communication system buffers the synthesized clock and outputs a plurality of system clocks through the plurality of output ports, inputs the plurality of system clocks, and checks whether each of the system clocks is normal or abnormal. And a clock monitoring unit configured to sequentially determine the result, and a register for storing a result of determining whether the system clocks are normal or abnormal by the clock monitoring unit.
In addition, a timing module for inputting a preset reference clock according to the present invention, clock synthesizing and outputting a synthesized clock, and a plurality of output ports, and buffering the synthesized clock to provide a plurality of output ports. A method of monitoring a clock in a communication system including a clock driver for outputting system clocks and providing the plurality of system clocks to various boards that perform unique functions may include inputting all of the plurality of system clocks; And determining whether the system clocks are normal / abnormal and sequentially determining them, and storing a result of determining whether the system clocks are normal / abnormal in a register.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.                     

2 is a diagram illustrating a configuration of a clock monitoring apparatus according to an exemplary embodiment of the present invention. This clock monitoring device shows an example implemented in a synchronizer board.

Referring to FIG. 2, the clock monitoring apparatus includes a timing module 10, clock drivers 21 to 23, a clock monitoring unit 300, and a central processing unit (CPU) 400. The timing module 10 inputs a preset reference clock and outputs a synthesized clock by synthesizing a clock. The clock output from the timing module 10 is a clock of a desired frequency. The clock driver 21 of the clock drivers inputs the clock from the timing module 10 and outputs the clocks to the clock drivers 22 and 23.

The clock driver 22 inputs a clock from the clock driver 21 and outputs a predetermined number of clocks (eg, 4). The clock driver 23 inputs a clock from the clock driver 21 and outputs a predetermined number of clocks (eg, 4). That is, the clock drivers 21 to 23 have a plurality of output ports, and buffer the synthesized clock to output a plurality of system clocks through the plurality of output ports. A plurality of system clocks output from the clock drivers 21 to 23 are provided to various boards (not shown) that perform unique functions in the communication system. The clock monitoring unit 300 inputs clocks output from the clock drivers 22 and 23 to determine whether each clock is normal or abnormal, and outputs a signal according to the determination result. The central processing unit (CPU) 400 inputs a clock normal / abnormal determination signal from the clock monitoring unit 300 and outputs a control signal for displaying a normal / abnormal state. The clock monitoring unit 300 does not determine whether one clock is normally operated among a plurality of clocks as in the prior art as illustrated in FIG. 1, but sequentially checks whether all clocks are normally operated. It features.

3 is a diagram illustrating a detailed configuration of the clock monitoring unit 300 shown in FIG. 2.

Referring to FIG. 3, the clock monitoring unit 300 includes a comparison clock oscillator 310, a monitoring period clock generation unit 320, an output clock port normal / abnormal determination unit 330, and a register 340. The comparison clock oscillator 310 oscillates the comparison clock. The monitoring period clock generator 320 inputs a comparison clock oscillated by the comparison clock oscillator 310 and generates a clock for determining a preset monitoring period. The output clock port normal / abnormal determination unit 330 checks the output ports of the clock drivers 22 and 23 according to the monitoring period clock generated by the monitoring period clock generator 320 to determine whether the corresponding system clocks are normal or abnormal. Determine. The output clock port normal / abnormal determination unit 330 outputs a normal / abnormal determination signal based on a decision result. The register 340 is for storing a result of determining whether the system clocks are normal or abnormal by the output clock port normal / abnormal determination unit 330. This register 340 is implemented as n bits when the system clocks are n, and each bit corresponds to each of the system clocks.

The operation in which the normal / abnormal determination signal is stored (written) and the stored normal / abnormal determination signal is read in the register 340 is controlled by the CPU 400. The CPU 400 may determine whether a clock corresponding to a specific port is normal or abnormal by reading information of a region indicated by a specific address, and clocks corresponding to all ports by reading information of all regions. It can be determined whether it is normal / abnormal. The CPU 400 inputs a normal / abnormal determination signal from the clock monitoring unit 300 and outputs a control signal for displaying a normal / abnormal state of a specific port correspondingly.

2 and 3, the clock monitoring apparatus according to the embodiment of the present invention uses an oscillator having the same frequency as the clock synthesized in the timing module 10 as a comparison clock, and uses a clock monitoring unit CPLD. 300 generates a clock that determines the monitoring period from the comparison clock. Block 330, which determines whether the clocks output from the clock drivers 22 and 23 are normal or abnormal, sequentially checks the output ports in a monitoring period and stores the normal / abnormal in the n-bit register 340. The CPU 400 reads which bit of the n bits stores the abnormal signal and generates a signal indicating that a problem has occurred in the output clock of the port corresponding to the bit. For example, the CPU 400 may generate a control signal for blinking a light emitting diode (LED).

For reference, the clock monitoring apparatus according to the related art shown in FIG. 2 does not reliably monitor the operation of the other clocks by inputting only one of a plurality of buffered clocks to the CPLD which determines whether the clock operates normally. I couldn't. Therefore, in order to solve this problem, the present invention inputs all buffered clocks to the CPLD and monitors the clocks in a predetermined order in a predetermined period. If the signal indicating abnormality is called "High", the CPU (or microprocessor) reads which bit in the n-bit register is "High" to indicate a problem with the output clock port corresponding to that port.

4A is a diagram illustrating an operation timing of clocks output through n output ports of the clock driver illustrated in FIG. 2. 4B is a diagram illustrating an operation timing of the monitoring cycle clock generator illustrated in FIG. 3.

Referring to FIG. 4A, clocks corresponding to buffered output clock ports are shown. Referring to FIG. 4B, a comparison clock for monitoring clocks corresponding to each output clock port is illustrated. . For example, if the frequency of the clock synthesized in the timing module 10 of FIG. 2 is 19.44 MHz, the n buffered clocks should have the same frequency of 19.44 MHz. Therefore, the clock monitoring unit 300 sequentially monitors clocks output from the n ports at 8 kHz (125 μs) cycles.

5 is a flowchart illustrating a processing flow of a clock monitoring operation according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the timing module 10 of FIG. 2 receives a reference clock from DOTS in step 501, and synthesizes clocks in step 502 to output a clock of a desired frequency. Clock drivers 21-23 buffer the synthesized clock. The clock monitoring unit 300 monitors the clocks output after being buffered by the clock drivers 21 to 23 in step 504 and stores a normal / abnormal determination signal according to the monitoring result in the register 340. The CPU 400 reads signals stored in each area of the register 340 of the clock monitoring unit 300 to determine whether each clock is normal or abnormal, and displays the determination result externally. For example, if it is determined in step 505 that the first port is abnormal, the CPU 400 outputs a control signal for indicating an abnormal state of the first port in step 506, and thus displays the abnormal state of the first port. Be sure to For example, if it is determined in step 507 that the n-th port is abnormal, the CPU 400 outputs a control signal for indicating an abnormal state of the n-th port in step 508, and thus the abnormal state of the n-th port is determined. To be displayed.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the clock monitoring apparatus according to the related art synthesizes a desired clock through a timing module, generates as many numbers as necessary through a driver, and then monitors only one of them, thereby inferring the operation of the other clocks. In addition, the device proposed in the present invention has the advantage that it is possible to immediately cope with a problem when it is possible to know whether all clocks operate normally by monitoring all the clocks copied through the driver. Accordingly, there is an advantage that can improve the reliability of the entire system.

Claims (6)

A timing module for inputting a preset reference clock, synthesizing a clock, and outputting a synthesized clock, and a communication system including a plurality of output ports and providing a plurality of system clocks to various boards performing unique functions. , A clock driver that buffers the synthesized clock and outputs a plurality of system clocks through the plurality of output ports; A clock monitoring unit which inputs all of the plurality of system clocks and checks whether the system clocks are normal or abnormal and sequentially determines the system clocks; And a register for storing a result of discriminating whether the system clocks are normal or abnormal by the clock monitoring unit. According to claim 1, wherein the clock monitoring unit, A monitoring cycle clock generator for generating a clock for determining a preset monitoring cycle; And a discriminating unit which determines whether the corresponding system clocks are normal / abnormal by inspecting the output ports according to the monitoring period clock. delete The clock monitoring apparatus of claim 1, wherein the register is implemented with n bits when the system clocks are n, and each bit corresponds to the system clocks. A timing module for inputting a preset reference clock, synthesizing a clock, and outputting a synthesized clock; and a plurality of output ports; buffering the synthesized clock to output a plurality of system clocks through the plurality of output ports Claims [1] A method for monitoring a clock in a communication system including a clock driver and providing the plurality of system clocks to various boards performing unique functions, the method comprising: Inputting all of the plurality of system clocks; Determining whether the system clocks are normal or abnormal and sequentially determining the system clocks; And storing the result of the determination on whether the system clocks are normal or abnormal in a register. The method of claim 5, The storing process, And when each of the system clocks is n, stores them in the register implemented with n bits, and each bit corresponds to each of the system clocks.

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