JPH0766792A - Ds3 frame transmitter/receiver - Google Patents

Abstract

PURPOSE:To make it possible to store a DS2 signal in an optional channel in a DS3C bit parity M frame system. CONSTITUTION:Nine bits (3X3) to be control bits C1 in 2ch, 6ch and 7ch out of control bits in 7 channels constituting a DS3C bit parity M frame are unused bits. Thereby these unused C1 bits consisting of 9 bits are used for two kinds of control bits (staff information or information indicating a storing channel position) or the like of a DS2 signal to be stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DS3 frame transmitting / receiving apparatus, and more particularly to a transmitting / receiving apparatus used in a DS3 level DS3C bit parity frame transmission system in a PCM communication system.

[0002]

2. Description of the Related Art As for the DS3C bit parity frame transmission system, American National Standard T1.
107-1990 (American National Standard T
1.107-1990) and Proposed Contribution to
CCITT (T1X1.4 AT & T. Jan. 27'9
2), and the format (structure) of the specified DS3C bit parity M frame is shown in FIG.
Is shown in.

This frame format is P shown in FIG.
The DS3 level (44.736 MHz) multiplexed signal is obtained by the CM multiplexing method, and is obtained by multiplexing the DS2 level signal (6.312 MHz) for 7 channels by the multiplexer A. To be In addition, each channel of this DS2 level signal outputs a DS1 level signal (1.544 MHz) in the multiplexer B.
It is obtained by multiplexing bits for channels.

FIG. 5 shows a DS3 level C-bit parity M (Multi) frame format obtained in this way,
It consists of 7 channels from 1ch to 7ch, and each channel has 85 slots (bits) × 8 =
It consists of 680 slots (bits). The head bit of each 85-slot group has various types of information defined in advance (overhead information, X, F1, AIC, FO, N
a, FEA, P, CP, FEBE, DLt, etc.) are superimposed, and DS is added to each of the other 84 slots.
Two-level signal bits are multiplexed respectively.

In particular, the bit portion indicated by the control bit in the frame of FIG. 5 is so-called C bit, and 7 × 3 = 21 bits are present in 1M frame. The 21 C bits are used to send and receive various alarms and control information.

[0006]

In the PCM communication system having such a frame format, as shown in FIG. 7, the signal of the DS2 level which is the input of the multiplexer A for multiplexing to the DS3 level is set at the previous level. A DS
In place of the 1-level multiplexed signal, there is a demand for switching the switch S to directly supply the DS2 level signal from the outside to the multiplexer A to multiplex the DS3 level signal.

For example, when it is desired to accommodate a DS2 level signal from the outside via the switch S1 in the first channel of the DS2 level, it is necessary to add control information to the DS2 signal from the outside and superimpose it. The control bits of the first channel (three C bits of AIC, Na, and FEA in FIG. 5) are used for other purposes as described above, and therefore cannot eventually accommodate the DS2 signal from the outside.

The same applies to the other channels, and as a result, in the conventional PCM communication system having the DS3 level C-bit parity M frame structure, the DS2 level signal is not supplied from the outside and accommodated.

Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, and its object is to provide a desired channel of the M frame of the DS3 level signal from the external DS2 level. It is to provide a DS3 frame transmitting / receiving apparatus capable of accommodating a signal.

[0010]

Principle of the Invention In the DS3 level C bit parity M frame format (FIG. 5), of the 21 control bits, the 3 control bits C of the second channel
3rd control bit C1,7ch
The three control bits C1 of the eye are all defined as unused bits fixed to "1".

Therefore, in the present invention, these 3 × 3 unused C1 bits are used as control information of the DS2 level signal from the outside to be accommodated, and at least two DS2 level signals are externally supplied. It is made possible to receive the DS3 level signal by inputting from.

More specifically, among the C1 bits of the 2nd, 6th and 7th channels having the unused control bit (C1), for example, the DS2 which accommodates the 3rd C1 bit of the 7th channel in the 7th channel. As the control information bit (stuff information bit) of the level signal, and as the control information bit (stuff information bit) of the DS2 level signal accommodated in another arbitrary channel, for example, three C1 bits of the sixth channel are used. Then, the three C1 bits of the second channel are used as the channel designation information for designating the accommodating channel of the DS2 level signal accommodated in an arbitrary channel.

By doing so, it becomes possible to accommodate two DS2 level signals from the outside in the two channels of 7ch and another arbitrary channel.

[0014]

In the DS3 frame transmitter according to the present invention, each frame is composed of a plurality of channels, and among these three channels, the first to third channels each have 3 unused C1 bits. And a first stuffing circuit for accommodating a DS2 level signal in the first channel, and stuffing information of the first stuffing circuit in the first channel. Means for superimposing on the used C1 bit, a second stuff circuit for accommodating another DS2 level signal in a designated channel other than the first channel designated from the outside, and stuff information of the second stuff circuit Means for superimposing the unused C1 bit of the second channel, and a channel indicator indicating which channel is the designated channel. Means for superimposing the information on unused C1 bit of the third channel, characterized in that it comprises a.

In the DS3 frame transmitting / receiving apparatus according to the present invention, each frame is composed of a plurality of channels, and among these channels, three first to third channels each include three unused C1 bits. A frame transmitting / receiving device, wherein D is used for the first channel
A first stuff circuit for accommodating an S2 level signal, and stuff information of the first stuff circuit are stored in the first stuff circuit.
Means for superimposing on unused C1 bits of a channel, a second stuffing circuit for accommodating another DS2 level signal in a designated channel other than the first channel designated from the outside, and a second stuffing circuit of this second stuffing circuit A transmitter comprising: means for superimposing stuff information on an unused C1 bit of the second channel; and means for superimposing channel specifying information indicating which channel the specified channel is on an unused C1 bit of the third channel. , Means for receiving the DS3 frame to extract the channel designation information, means for extracting the stuff information, and destaff of the channel designated by the extracted channel designation information. Using the destuffing circuit and the extracted staff information
And a receiver including a destuff circuit for destuffing the channel.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are block diagrams of a transmitting apparatus according to an embodiment of the present invention. In the present embodiment, there are three channels having unused C1 bits: 2ch, 6ch, 7c.
Among h, one external DS2 level signal is accommodated in 7ch, and another external DS2 level signal is accommodated in another arbitrary channel. The unused C1 bit (3 bits) of 7ch is used as the stuff information (3 bits) of the external DS2 level signal accommodated in 7ch.

The channel designation information (3 bits is sufficient) for designating the other accommodating channel of the external DS2 level signal is the unused C1 bit (3 bits) of 2ch.
The stuff information (3 bits) of this external DS2 level signal uses the unused C1 bit (3 bits) of 6ch.

1 to 6 channels among 1 to 7 channels forming the DS3 level C bit parity M frame shown in FIG.
Is input to the selection circuit 1. This selection circuit 1 is for each channel
It is composed of corresponding 2: 1 selectors, and the output of each selector is input to the multiplexing circuit 2.

7ch is directly input to the stuff circuit 3,
It is input to the multiplexing circuit 2 after undergoing the stuffing process. The stuff circuit 3 outputs 3-bit stuff information.

A 6: 1 selector 4 for inputting 1ch to 6ch is provided, and only the channels (1ch to 6ch) designated by external channel designation information are selectively derived to generate the stuff circuit 5. Supply to. In this stuffing circuit 5 as well, the signal of the selected channel is subjected to the stuffing process and becomes the other input of each selector of the selecting circuit 1. The stuffing circuit 5 also outputs 3-bit stuffing information.

In the selection circuit 1, only the selector corresponding to the channel designated by the channel designation information is switched and controlled, and the signal of the designated channel subjected to the stuffing process of the stuffing circuit 5 is derived. The other selector derives the input signal of each channel.

Thus, the multiplexer 2 outputs the DS3 level signal accommodating the DS2 level signal from the outside to a total of two channels of the designated one channel of the channels 1 to 6 in addition to the 7ch. Become.

This multiplexed output becomes an input to the control bit adding circuit shown in FIG. This control bit adding circuit is cascaded with a timing generation circuit that counts a clock (44.736 MHz: the same as the clock speed of a DS3 level signal) and generates a timing indicating the position of each control bit on the frame. And 9 2: 1 selectors 7 to 15.

The selectors 7 to 12 are selectors for adding the control bits AIC, Na, FEA, CP, FEBE, and DLt, respectively. The selectors 13 to 15 are channel designation information and DS2 accommodated in channels other than 7ch. It is a selector for adding the stuff information of the level signal and the stuff information of the DS2 level signal accommodated in 7ch, respectively.

By doing so, the two DS2 level signals that have been subjected to the stuffing process can be accommodated in 7ch and another arbitrary channel and sent out as a DS3 level signal.

FIG. 3 and FIG. 4 show an embodiment of a receiving device for receiving the multiplexed output (DS3 level signal) from the above transmitting device and converting it to a DS2 level signal.

The received DS3 level signal is input to the timing generation circuit 21, the timing extraction circuit 22 and the DS3 frame synchronization circuit 23, and each control bit in the DS3 level signal is extracted. The timing generation circuit 21 generates various control bit extraction timings based on the clock signal CLK and the frame signal FRM obtained by the timing extraction circuit 22 and the DS3 frame synchronization circuit 23.

The latch circuits 24-28 respectively extract and latch each control bit from the received DS3 level signal in synchronization with the control bit extraction timing.

The 2ch C1 decoder takes in and decodes the C1 bit (3 bits) of the 2nd channel, and the decoded output becomes the channel designation information. 6chC
1 majority circuit 30 and 7ch C1 majority circuit 31 is 6c
The C1 bits (3 bits each) of h and 7 ch are respectively taken in, the majority decision values of these 3 bits are respectively taken, and they are respectively output as destuff information.

The stuff information added to each C1 bit of 6ch and 7ch is, for example, all 3 bits of the C1 bit are "1" when there is a staff, and all "0" when there is no staff. It is assumed that the information is redundant information in order to improve reliability against bit errors. Therefore, the destuff information can be obtained with high reliability by making a majority decision on these three C1 bits.

The received DS3 level signal is input to the separation circuit 32, separated and derived for each of the seven channels, and becomes one input of the corresponding 2: 1 selector in the selection circuit 33.
It should be noted that only the 7th channel signal is directly input to the destuffing circuit 34 and is destuffed according to the 7th channel destuffing information.

The signals of channels 1 to 6 are 6: 1 selector 3
Only one channel input to channel 5 and designated by the channel designation information is input to the destuff circuit 36 and destuffed according to the destuff information.

The output of the destuffing circuit 36 is 2: 1 each.
The selector has other inputs, and among the selectors of the selection circuit 33, only the selector corresponding to the channel designated by the channel designation information selects and derives the output of the destuff circuit 36.

By doing so, the DS2 level signals are separated and output.

In the above embodiment, the C1 of 7ch is used.
The stuff information of the external DS2 level signal accommodated in the channel is superimposed on the bit, but the stuff information of the DS2 level signal accommodated in the channel is superimposed on the C1 bit of 2ch, and the stuff information of the C1 bit of 6ch and 7ch is 2
The stuff information and the channel designation information of signals accommodated in channels other than ch may be superimposed.

Further, the stuff information of the DS2 level signal accommodated in the channel is superimposed on the C1 bit of 6ch,
The stuff information and the channel designation information of signals accommodated in channels other than 6ch may be superimposed on each C1 bit of 2ch and 7ch.

[0038]

According to the present invention, 3 × 3 unused C1s
Since the bit is used as control information of the DS2 level signal from the outside to be accommodated, there is an effect that at least two DS2 level signals can be input from the outside and accommodated in the DS3 level signal.

[Brief description of drawings]

FIG. 1 is a partial block diagram of a transmission device according to an embodiment of the present invention.

FIG. 2 is a partial block diagram of a transmission device according to an embodiment of the present invention.

FIG. 3 is a partial block diagram of a receiving device according to an embodiment of the present invention.

FIG. 4 is a partial block diagram of a receiving apparatus according to an embodiment of the present invention.

[Figure 5] American National Standard T1.107
It is a figure which shows the format of DS3C bit parity M frame prescribed | regulated in -1990.

FIG. 6 is a diagram showing an example of a PCM multiplexing system.

FIG. 7 is a diagram showing another example of the PCM multiplexing system.

[Explanation of symbols]

 1, 33 selection circuit 2 multiplexing device 3, 5 stuff circuit 4, 35 selector 6, 21 timing generation circuit 7 to 15 2: 1 selector 22 timing extraction circuit 23 frame synchronization circuit 24 to 28 latch circuit 29 2ch C1 bit decoder 30, 31 majority circuit 34,36 destuff circuit

Claims (2)

[Claims] 1. A transmission device for a DS3 frame, wherein each frame comprises a plurality of channels, and three first to third channels of these channels each include three unused C1 bits. A first stuffing circuit for accommodating a DS2 level signal in the first channel; a means for superimposing the stuffing information of the first stuffing circuit on an unused C1 bit of the first channel; A second stuffing circuit for accommodating another DS2 level signal in a designated channel other than the first channel, and means for superimposing the stuffing information of the second stuffing circuit on an unused C1 bit of the second channel And superimposing channel designation information indicating which channel is the designated channel on the unused C1 bit of the third channel. Transmitting device DS3 frame, characterized in that it includes means that, a. 2. A transmission / reception device for a DS3 frame, wherein each frame comprises a plurality of channels, and three first to third channels of these channels each include three unused C1 bits. A first stuffing circuit for accommodating a DS2 level signal in the first channel, a means for superposing the stuffing information of the first stuffing circuit on an unused C1 bit of the first channel, A second stuffing circuit for accommodating another DS2 level signal in a designated channel other than the first channel, and stuffing information of the second stuffing circuit is used for the unused C1 of the second channel.
A transmitter including means for superimposing on the bit, means for superimposing channel designation information indicating which channel the designated channel is on the unused C1 bit of the third channel, and the channel designation by receiving the DS3 frame Means for extracting information, means for extracting the staff information, a destuff circuit for performing destuffing of a channel designated by the extracted channel designation information using the extracted staff information, and the extracted staff A receiver including a destuff circuit for destuffing the first channel using information, and a DS3 frame transceiver.