JPH0766255A - Manufacture of semiconductor and line of manufacture - Google Patents

Abstract

PURPOSE:To provide the pattern manufacturing method of a semiconductor and the like with which good or bad of process and the harmfulness of foreign matters can be judged. CONSTITUTION:The image of pattern being formed is detected, the detected image signal and the reference image signal are compared, the positional deviation of pattern is detected as configurational discordance after process treatment, and the defective or nondefective of process is judged based on the above- mentioned discordance. Also, the configurational discordance is detected before and after process treatment, and the harmfulness of foreign matters is judged based on the configurational discordance. As a result, the false report, where a normal part is detected as defective part, can be lessened and the detection sensitivity of a microscopic defect can be improved. Accordingly, the defect of 0.1 to 0.2mum can be detected in a highly reliable manner. Also, the forming method of pattern such as a semiconductor and the like, with which the defective and non-defective of process and the harmfulness of foreign matters is judged, can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a pattern of a semiconductor or the like and a manufacturing line thereof, and more particularly to a method of manufacturing a high yield pattern of a semiconductor wafer or a liquid crystal display and a manufacturing line thereof.

[0002]

2. Description of the Related Art Conventionally, in order to manufacture semiconductors such as memory devices with a high yield, it is considered appropriate to detect defects in appearance and foreign matters on a pattern of semiconductors in the process of manufacture rapidly by an automatic appearance inspection device. Countermeasures such as cleaning of manufacturing equipment and review of process conditions are being implemented. As a method for detecting the appearance defect, for example, Japanese Patent Laid-Open No. 60-73310,
JP-A-1-143938 and the like are available. Through these efforts, efforts are being made to detect defects and minimize yield loss.

[0003]

However, when the semiconductor to be manufactured becomes a super LSI such as 16 MDRAM or 64 MDRAM, the appearance defect to be detected becomes finer, for example, 0.25 μm or less. It cannot be detected by automatic visual inspection method / device. As shown in FIG. 32, although the detection method has advanced to binary comparison and density comparison, as the device becomes finer, the difference in the normal portion density due to the difference in the film thickness becomes larger with respect to the defect signal, resulting in a fine defect. Cannot be detected. That is, if an attempt is made to detect a desired microdefect that affects the electrical characteristics and reliability of the semiconductor, many false alarms will occur that detect a normal part, and if the false alarm is below an allowable value, the desired defect cannot be detected. It will be.

Even if a false defect is allowed to occur and a minute defect is detected, erroneous information called a false report is mixed in addition to the true useful information, and the defect countermeasure to be taken is not appropriate. Therefore, such a method does not improve the product yield.

The object of the present invention is to achieve 0.1 to 0.2 μm in the future.
An object of the present invention is to provide a method for reliably detecting m defects and accurately determining the quality of a process such as a cleaning process, an etching process, and a lithography process. Another object is to provide a method for judging the harmfulness of foreign matter. Another object of the present invention is to provide a method for manufacturing a pattern of a semiconductor or the like, which can judge the quality of the process and the harmfulness of foreign matter.

[0006]

Therefore, the present invention has achieved the above object by realizing the following idea. An image of a pattern in the middle of manufacturing is detected, and the detected image signal is compared with a reference image signal to detect a positional deviation of the pattern as a shape mismatch or a pattern quality.

[0007] The shape inconsistency and the quality of the process are detected after the process processing, and the quality of the process is judged based on the shape inconsistency and the quality of the process.

The shape mismatch is detected before and after the process processing, and the harmfulness of the foreign matter is judged based on the shape mismatch. The positional deviation of the pattern is detected by differentiating the image signals and comparing the polarities thereof.

The quality of the process and the harmfulness of the foreign matter are judged by using the detected number of mismatched shapes or the distribution of the quality.

[0010]

According to the above-mentioned means, there is little false alarm for detecting a normal portion as a defect, and the detection sensitivity for fine defects can be improved. That is, as shown in FIG. 33, in the conventional defect detection based on the density difference plus the threshold value, the difference between the normal portion and the defect due to the difference in film thickness or the like could not be discriminated. Defects can be detected with high accuracy. In particular, when the comparison is made depending on whether the image signal is rising to the right or falling to the right, the positional deviation of the pattern can be accurately detected for the first time. Therefore, future 0.1
0.2 μm defects can be detected with high reliability. Further, according to the above, it is possible to provide a method for accurately determining the quality of the process. Moreover, according to this, the method of judging the harmfulness of a foreign material can be provided. Furthermore, it is possible to provide a method for manufacturing a pattern of a semiconductor or the like that can judge the quality of the process and the harmfulness of foreign matter.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 show an example of the embodiment of the present invention. In the wafer manufacturing line, it has shown improvement in yield by detecting defects. In particular, here, in the semiconductor manufacturing line, to improve the yield,
Two management items for obtaining a non-defective device are shown. The first is foreign matter management. The second is process management.

First of all, foreign matter management means that when a wafer in the process of being manufactured is put on a certain process apparatus, the foreign matter that has already adhered to the process apparatus is defective in pattern shape (defect) by the process apparatus.
There are some types that do not have a defective shape, and some types that do not have a defective shape are identified as harmful foreign substances. Whether it becomes a harmful foreign matter depends on the composition and size of the foreign matter.
A foreign substance that is not a harmful foreign substance may be treated as a false alarm from the viewpoint of yield improvement measures. Therefore,
This is not beneficial for countermeasures. Therefore, it is necessary to correctly identify only the harmful foreign matter in order to improve the yield.

Process control means that when a wafer in the process of being manufactured is put on a certain process device, a defective shape occurs in a pattern due to a defective process condition or the like. Therefore, if the defective shape is detected, the condition setting and evaluation of the process can be performed. In addition, the quality of the pattern (including those that are not necessarily defective) can also be evaluated.

In order to realize the above-mentioned foreign matter management and process management, pattern shape defects are detected. Next, detection of pattern shape defects will be described.

FIG. 3 shows an example of a pattern shape defect detecting apparatus according to an embodiment of the present invention. In the figure, the scanning of the one-dimensional image sensor 4 is made to coincide with the scanning in the Y direction, so that the LSI wafer 1 which is the pattern to be inspected can be detected one-dimensionally through the objective lens 3.
By moving the LSI wafer 1 in the direction orthogonal to the main scanning of the image sensor 4, that is, the X direction by the XY table 1A, the pattern to be inspected can be detected as a two-dimensional image. The LSI wafer 1 is illuminated by the illumination lamp 2. The output signal of the image sensor 4 is delayed by the delay memory 6 by the time for moving the wafer 1 by one chip. As a result, the output signal of the image sensor 4 and the output signal of the delay memory 6 correspond to the image signals of the adjacent chips 1a and 1b. These image signals are compared by the image processing device 7, and the mismatch is detected as a defect.

This embodiment corresponds to a comparative inspection of optical images, but SEM (scanning electron microscope) is used as an image detecting means.
Is used for comparison inspection of SEM images. In addition, anything that can be detected as an image can be used.

The image stored in the delay memory 6 may be an image obtained by separately capturing a non-defective pattern. In this case, the detection of a mismatch (defect) described below is a deviation from the non-defective pattern. If the coordinates of the non-defective pattern are known, the deviation from the coordinates can be detected. That is, although the shape defect is detected and the above is described, the coordinate check of the pattern (either the long dimension or the short dimension) can be performed.

Next, the structure of the image processing apparatus 7 will be described.

First, in FIG. 4, for example, the detected image signal f of 8 bits and the stored image signal g are sequentially differentiated for each pixel by the primary differential circuits 10a, 10b and secondary differential circuits 11a, 11b. Differentiate.

As shown in FIG. 5, the first-order differentiating circuits 10a and 10b sequentially cut out 3 × 3 pixels from the image to obtain first-order differentiators o, p, ... V and o ', p'in eight directions. ...
..V is obtained, and 16-bit signals 100a and 100b, for example, each of which has a polarity (1,0) and a value (1,0) obtained by binarizing the absolute value of the first derivative are output. Here, the polarity "1" represents positive and "0" represents negative.

As shown in FIG. 6, the second-order differentiating circuits 11a and 11b apply the operators 1, 2, 1 to the pixels and binarize them by the threshold value Dth to remove the dark area of the edge of the pattern. For example, 1-bit signals 101a and 101b are output by setting them to "1" and others to "0".

Next, the cutout circuits 12a, 12b, 13
The outputs of the primary differentiating circuits 10a and 10b and the outputs of the secondary differentiating circuits 11a and 11b are cut out by a and 13b. The cutout circuits 12a and 13a cut out an area of, for example, 5 × 5 pixels and create a state in which ± 2 pixels are shifted. The cutout circuits 12b and 13b are synchronized with the central position of the 5 × 5 pixels.

Next, the polarity comparison circuits 14a to 14y use the outputs of the cutout circuits 12a, 12b, 13a, and 13b to perform the first-order and second-order differentiation results of the detected image signal and the stored image signal that are shifted by ± 2 pixels. Compare each. That is, in the dark area of the pattern edge extracted by the second derivative, the polarities of the first derivative of the detected image signal and the stored image signal in eight directions (pieces) and the magnitudes of their absolute values are compared for each direction. , A pixel having a non-matching polarity in a region having a large absolute value is regarded as a mismatch and a value “1” is output. The cutout circuits 12a and 12b are, for example, 5 × 5.
Since it has 25 pixel outputs, in that case, there are also 25 polarity comparison circuits 14a to 14y.

Next, the counter circuits 15a to 15y count the number of mismatched pixels obtained by the polarity comparison circuits 14a to 14y, for example, for each 1024 pixels × 256 pixels. The misregistration amount detection circuit 16 includes counter circuits 15a to 15a.
The number of mismatched pixels obtained by 15y is analyzed, and the number of mismatched pixels becomes smaller than the set value, for example, the amount of displacement (ΔX
₁ , ΔY ₁ ), ... (ΔXm, ΔYm) is output. This displacement amount is as shown in FIG. 7, for example.

Next, the outputs of the polarity comparison circuits 14a to 14y are delayed by the delay circuits 17a to 17y until the amount of positional deviation is obtained. Then, the area selection circuit 18a
To 18y, the above positional deviation amount (ΔX ₁ , ΔY ₁ ) ...
... Only the output of the polarity comparison circuit 16 at a position corresponding to (.DELTA.Xm, .DELTA.Ym) is used (activated), and the others are masked. Then, the AND gate circuit 19 takes the logical sum of the outputs of the area selection circuits 18a to 18y and outputs the value "1" as a defect.

Next, the components of each section will be described in more detail. FIG. 8 is a diagram showing a configuration example of the primary differentiating circuits 10a and 10b. From 8-bit digital signal 8,
Shift registers 20a, 20b and latches 21a-21
A region of 3 × 3 pixels is cut out in the latches 21a to 221i using i. From these 3 × 3 pixels, the primary differentials in the eight directions shown in FIG. 5 are calculated using the subtractors 22a to 22h. Here, the subtractor 22a calculates the first derivative o of FIG.
h corresponds to the first-order differential u, and the outputs of the subtractors 22a to 22h are 1-bit signs, that is, positive and negative polarities (1,
0) and the absolute value of the remaining first derivative (| f '| or | g'
It is 8 bits indicating |).

The binarization circuits 23a to 23h should set "1" to a value smaller than the threshold value Eth if the absolute value (| f '| or | g' |) of the first-order differential is equal to or larger than the threshold value Eth. For example, "0", that is, a 1-bit value (1, 0) obtained by binarizing the absolute value of the first derivative is output. That is, the subtractor 22
a to 22h and eight adjacent signals (directions) indicating the polarity from the binarization circuits 23a to 23h and eight adjacent signals (directions).
And a signal indicating the magnitude of the absolute value of are combined and output as signals 100a and 100b in a 16-bit configuration.

FIG. 9 is a diagram showing a configuration example of the secondary differentiating circuits 11a and 11b. 8 bit digital signal 8
From the shift registers 24a, 24b and the latch 25
A region of 3 × 3 pixels is cut out in the latches 25a to 25i using a to 25i. A binary edge pattern is extracted from these 3 × 3 pixels by using the edge operator shown in FIG. That is, the adder 26, the multiplier 27, and the adder 28 realize an edge operator of 1, -2, 1. The other three types of edge operators shown in FIG. 6 can be realized by the adder 26, the multiplier 27, and the adder 28 in the same manner. (In FIG. 9, the adder 26, the multiplier 27, and the adder 28 that perform the other three types of edge operators are omitted.) This is binarized by the threshold value Dth set by the binarization circuit 29, The dark area of the edge of the pattern is set to "1" and the other areas are set to "0", and the signals 101a and 101b having the 1-bit configuration are output.

FIG. 10 is a diagram showing a configuration example of the cutout circuits 12a and 12b. 16-bit digital signal (eight polarities (1,
0) and the magnitude of the absolute value of the eight first-order derivatives (1,0)) 100a, and the shift registers 30a to 30
d and the latches 31a to 31y
An area of 5 × 5 pixels is cut out at 31y. In addition, a shift is made from a 16-bit digital signal 100b (a composite signal of eight polarities (1,0) and eight primary differential magnitudes (1,0)) output from the primary differentiating circuit 10b. Registers 30e, 30f and latches 32a, 32b, 32c
Is used to output the pixel corresponding to the central pixel of the 5 × 5 pixels to the latch 32c.

The cutout circuits 13a and 13b shown in FIG. 4 can also be realized with a similar configuration. Figure 1
Here is an example: 1 bit output from the secondary differentiating circuit 11a
Shift register 33a-3 from the binary signal (signal (1, 0) indicating the edge region and the other region) 101a.
3d, and the latch 34a using the latches 34a to 34y
A region of 5 × 5 pixels is cut out to ˜34y. In addition, the 1-bit binary signal 101 output from the secondary differentiating circuit 11b
b (edge region, signal indicating other region (1,
0)), the shift register 33e, 33f and the latch 35a, 35b, 35c are used to make the latch 35c 5
A pixel corresponding to the central pixel of × 5 pixels is output.

FIG. 12 is a diagram showing a configuration example of the polarity comparison circuits 14a to 14y. In the figure, the comparison circuit 37a that validates the mismatch by the polarity comparison only in the region where the absolute value of the primary differential signal is large is the 16-bit signal 102, 10
EXOR that outputs a signal of "1" when the polarities (positive: 1, negative: 0) included in 4 and the polarities (positive: 1, negative: 0) do not match and when they do not match, and "0" when they match
Outputs a "0" signal when both of the signals representing the magnitude of the absolute value of the primary differential signal included in the signals 102 and 104 of the circuits 36a and 16 bits are small (both), and outputs a "1" signal otherwise. NAND circuit 36b and NAND circuit 3
When the output of 6b is "0", it is composed of an AND circuit 36c which does not output the mismatch of polarities which is output as a signal of "1" from the EXOR circuit 36a.

The OR circuit 38 takes the logical sum of the outputs of the eight (direction) comparison circuits 37a to 37h to obtain at least one comparison circuit 37 among the eight comparison circuits 37a to 37h.
When a mismatch due to polarity comparison is detected only in a region where the absolute value of the primary differential signal is large from a to 37h, this polarity mismatch signal is output. The OR circuit 39 takes the logical sum of the binarized edge pattern signals 103 and 105 output from the cutout circuits 13a and 13b, and outputs either the detected image signal f or the stored image signal g, that is, the cutout circuit 13
The signal "1" indicating that the edge pattern "1" signal has been detected is output to either a or 13b.
The AND circuit 40 calculates the logical product of the outputs of the OR circuit 38 and 39, and outputs a polarity mismatch signal obtained in a region where the absolute value of the primary differential signal is large as a signal "1" in the edge pattern. It is a thing.

Next, a description will be given of how comparison is made with the above configuration.

Detected image signal f is obtained for two circuit patterns having different shades as shown in FIGS. 13 (a) (b) (c) (d).
_{For 1} and the stored image signal g ₁ , a region where the absolute value of the primary differential signal is small (first differential value | f ′ | and | g ′ | ≦ Eth,
Eth is a threshold value) and is set to "0", and other regions are converted into primary differential polarity (positive (1), negative (-1)) signals. ). Then, a region where the absolute value of the primary differential signal is large (first differential value |
f '| or | g'|> Eth, where Eth is a threshold value),
Comparing the polarity (positive (1), negative (-1)) signal of the first derivative (f ') and the polarity (positive (1), negative (-1)) signal of the first derivative (g') With respect to the non-coincidence (1 / -1) signals, the OR circuit 38 shown in FIG. 12 in the polarity comparison circuits 14a to 14y shown in FIG. 4 obtains a determination result as shown in FIG. 14 (f). That is, in the area where the absolute value of the primary differential signal is large, it is determined that the detected image signal f ₁ and the stored image signal g _{1 do not} have the same polarity, and the polarity comparison circuit 14a shown in FIG.
The defect 8b is detected from the OR circuit 38 of 14y.

The size of the detected defect exactly matches the size of the actual defect. From this, it is understood that according to the present invention, it is possible to accurately grasp the shape error of the pattern due to the process condition failure or the like.

Here, attention is paid to the magnitude of the absolute value of the primary differential signal, but this is not always necessary depending on what one wants to pay attention to in the circuit pattern. However, it is usually better to do so to prevent erroneous detection in the normal part. For example, in FIG.
As shown in 5, for the detection image signal f ₁ and the stored image signal g ₁ only detects a defect 8b only polarity mismatch, the detected image signal f ₁ and the stored image signal g ₁ as shown in FIG. 15 Due to the difference, inconsistency of polarities is detected in the normal portion, and it is erroneously detected as a defect. Therefore, if a mismatch of polarities between the detected image signal f ₁ and the stored image signal g ₁ is detected in a region where the absolute value of the primary differential signal is large, FIG.
As shown in FIG. 4, erroneous detection of the normal part is eliminated.

Further, as shown in FIG. 16, as the circuit pattern is miniaturized, a mismatch in polarity between the detected image signal f ₂ and the stored image signal g ₂ is detected, and the normal portion is erroneously detected as a defect. Will end up. Therefore, the detected image signal f ₃ and the stored image signal g ₃ shown in FIG. 17A are respectively subjected to secondary differential signals f ₃ ″ and g ₃ ″ by the secondary differential circuits 11 a and 11 b.
(Shown as a second derivative in FIG. 17B) and binarized the second derivative signals f ₃ ″ and g ₃ ″ with the threshold value Dth (in FIG. 17C). (Shown as binarization of the second derivative) is obtained, and the OR circuit 39 shown in FIG. 12 OR-detects whether there is an edge signal (FIG. 17).
An edge signal of the circuit pattern of "1" is obtained in (d), which is shown as binarization of the second derivative. Then, with the signal "1" OR-detected by the OR circuit 39 shown in FIG. 12, the defect signal due to the polarity mismatch detected from the OR circuit 38 of the polarity comparison circuits 14a to 14y is logically ANDed in the AND circuit 40. By filtering, it is possible to eliminate erroneous detection of a normal portion that occurs in a non-edge region as shown in FIG.

According to the above, even if the shapes of the signal waveforms are considerably different, the shape defect generated at the circuit pattern edge is
Not only the presence or absence of it, but also the size can be detected accurately and with high reliability. Further, there are few false alarms in which a normal portion is erroneously detected as a defect, and the detection sensitivity for fine defects can be improved. This makes it possible to correctly evaluate the process, which is the initial purpose, and improve the product yield.

Of course, when the film thickness of the circuit pattern differs by more than the allowable value, this is detected as a defect. Therefore, the difference signal detection circuit 41 detects the difference signal as shown in FIG.
This may be binarized by the threshold value Gth using the binarization circuit 42.

Next, an example in which the present invention is applied to a multilayer pattern will be described.

The detection multilayer pattern F ₂ is shown in FIG.
The reference multilayer pattern G ₂ is shown in FIG. And
The stored image signal g ₂ for detecting the detection of multi-layer pattern F ₂ image signals f ₂ and the reference multi-layer pattern G ₂ shows the signal waveforms in FIG. 18 (c). As can be seen from these signal waveforms, a portion without positional deviation and a portion with positional deviation occur between them. This misalignment, which is called an inter-layer misalignment, occurs in a normal pattern and usually needs to be allowed. This misalignment between layers is likely to be a false alarm, and it is necessary to prevent it from being detected.

From the first-order differentiating circuits 11a and 11b, as shown in FIG.
8 (d), the differential polarity waveform signals 100a, 100b
Is obtained. Only by comparing the polarity waveform signals 100a and 100b in the polarity comparison circuits 14a to 14y,
Judgment result I (Fig.
8 (e), a defect and a normal portion are erroneously detected). Therefore, as shown in FIG. 19A, the stored image signal g ₃ is cut out to the left with respect to the detected image signal f ₃
2b differential polarity waveform signal 100a, which is shifted by 2b,
Find 100b. Then, the polarity waveform signal 100
A determination result II obtained by comparing a and 100b in the polarity comparison circuits 14a to 14y (a defect and a normal portion are erroneously detected as a polarity mismatch in the edge region as shown in FIG. 19C) is obtained. By ANDing these judgment results I and II with the AND circuit 19, FIG.
The final determination result as shown in 0 (only polarity mismatch due to a defect can be detected) is obtained.

FIG. 22 shows area selection circuits 18a-18y,
9 is a diagram showing a configuration example of an AND circuit 19. FIG. Delay circuit 17
The polarity comparison results output from a to 17y are the detected image signal f and the stored image signal g at the positions shifted by ± 2 pixels by the clipping circuits 12a, 12b, 13a and 13b.
Is a disagreement binarization signal obtained as a result of comparing the polarities with and, and the positional shift amount (ΔX ₁ , ΔY ₁ ) obtained by this and the positional shift amount detection circuit 16 ... (ΔXm, ΔYm) Area selection circuits (AND circuits) 18a to 18y based on
The binarized signal input to is selected as a signal of "1", and in the area selection circuits (AND circuits) 18a to 18y, the discrepancy binarized signals output from the polarity comparison circuits 14a to 14y and the positional deviation amount. The logical product with the binarized signal selected from the detection circuit 16 is taken, and as shown in FIG. 21, the threshold value Fth (Sth) or more for which the amount of positional deviation is determined is masked, and the AND circuit 19 causes ± 2 pixels. It is possible to realize the determination shown in FIG. 20 by taking the logical product of them within the range. This makes it possible to prevent the layer shift from being detected. Therefore, as compared with the conventional method, there are few false alarms in which a normal portion is erroneously detected as a defect, and the detection sensitivity for micro defects can be improved.

By these techniques, as shown in FIG. 1, it is possible to provide a method of manufacturing a pattern of a semiconductor or the like which can judge the quality of the process and the harmfulness of foreign matter.

FIG. 24 shows some specific examples that can be executed by the above technique. The expression is different from that in Fig. 1, but the basic idea is the same. There are things such as checking the transition of the density (occurrence frequency) of defects and foreign particles, focusing on one wafer, tracking the process to check how it changes with each process, and checking the distribution of defects and foreign particles. . Both of these contribute greatly to improving the yield of the line.

Further, FIG. 25 shows a method and an effect of the process tracking shown in FIG. This is the same as that described by the present inventors in JP-A-63-323276. According to this, it is possible to correctly extract the defects peculiar to the device,
Defect phenomena can be revealed. In addition, it is possible to detect a problematic process early in synchronization with wafer processing. In any case, a greater effect can be expected only when the present invention enables accurate defect detection without false alarms.

FIG. 26 shows an example of judging the quality of the cleaning process. By detecting defects, the cleanliness of the cleaning process is checked and fed back to the cleaning conditions. Figure 2
FIG. 7 shows an example of the cleaning process.

FIG. 28 shows an example of resolution check in the lithography process. Take the stepper as an example. The pattern resolution is checked by detecting defects.

FIG. 29 shows an example in which the wafer processing process is branched by the defect detection. Either process A or B is performed depending on the degree, number, distribution, etc. of defects. The transfer of wafers has been changed accordingly. By selecting the process in this way, as shown in FIG.
The effect that the number of detected defects can be significantly reduced is obtained.

Next, a method of classifying the types of defects will be described.

Although the difference in the pattern shape can be detected with high accuracy by the above-described embodiment, it is necessary to specify what the difference is in order to feed back information to the process. As shown in FIG. 31, the classification of defects includes (a) automatically classifying all defects to the end after detection of defects, and (b) using visual confirmation in the middle.

Of these methods, the method (b) classifies the defects by visual observation at the first time, but automatically classifies from the second time, and the types of the defects are short circuit, disconnection, convex defect, concave defect, It does not necessarily have to be grain, false information, etc., and types such as A, B, C (this is unknown) may be used. Of course, it is also effective to classify the defects into different shapes and the defects with different shades, or to detect the three-dimensional shape and classify based on this.

As described above, the unclassified defects are visually checked to classify the types of defects into A, B, C, etc., and the next detected defect has the same type as that already classified. If the person is a person, it is automatically determined to be one of the categories A, B, C, ... Without visual confirmation. This is repeated to separate defects by type.

Also, a plurality of types of defects are prepared according to the size of the defect. That is, since large defects can be classified into various categories, many types are prepared, but small defects are generally small in categories to be classified, and therefore, few types are classified.

In this way, the defects are classified, and the process and the like are controlled based on the classified information. Also, by feeding back the design data of the photomask,
It can also be used when redesigning a photomask.

The types of defects targeted by the present invention are:
In addition to the above, even if there are gate defects, pinholes, interlayer insulation film defects, disconnection due to foreign matter, aluminum wiring corrosion, defects due to stress migration of aluminum wiring parts, corrosion of bonding pad parts, cracks, etc. Good.

As described above with reference to the embodiments, according to the present invention, it is possible to improve the detection sensitivity for fine defects, since there are few false alarms in which a normal portion is erroneously detected as a defect. Therefore, future defects of 0.1 to 0.2 μm can be detected with high reliability.
As a result, it is possible to provide a method and a line for manufacturing a pattern of a semiconductor or the like, which can judge the quality of a process such as a cleaning process or a lithography process and the harmfulness of a foreign substance generated due to the process. Therefore, the product yield can be greatly improved.

[0059]

As described above, it is possible to improve the detection sensitivity of a fine defect because there are few false alarms in which a normal portion is erroneously detected as a defect. Therefore, future defects of 0.1 to 0.2 μm can be detected with high reliability. As a result, it is possible to provide a pattern manufacturing method or line for a semiconductor or the like that can judge the quality of the process and the harmfulness of foreign matter.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a wafer manufacturing line according to the present invention.

FIG. 2 is a diagram showing the management of a foreign substance or process according to the present invention.

FIG. 3 is a perspective view showing an embodiment of a pattern inspection apparatus according to the present invention.

FIG. 4 is a block diagram showing the configuration of an image processing apparatus.

FIG. 5 is a diagram illustrating a first-order differentiation process.

FIG. 6 is a diagram for explaining a secondary differentiation process.

FIG. 7 is a diagram illustrating alignment.

FIG. 8 is a block diagram showing a configuration of a primary differentiation circuit.

FIG. 9 is a block diagram showing the configuration of a second order differential circuit.

FIG. 10 is a block diagram showing a configuration of a cutout circuit.

FIG. 11 is a block diagram showing a configuration of a cutout circuit.

FIG. 12 is a block diagram showing the configuration of a polarity comparison circuit.

FIG. 13 is a one-layer pattern and a pattern detection signal.

FIG. 14 is an explanatory diagram of polarity comparison in a one-layer pattern.

FIG. 15 is an explanatory diagram of polarity comparison.

FIG. 16 is an explanatory diagram of polarity comparison.

FIG. 17 is an explanatory diagram of polarity comparison.

FIG. 18: Multilayer pattern and detection signal of multilayer pattern

FIG. 19 is an explanatory diagram of polarity comparison in a multilayer pattern.

FIG. 20: Defect determination example

FIG. 21 is an explanatory diagram of the number of mismatched pixels.

FIG. 22 is a block diagram showing a configuration of a region selection circuit for allowing interlayer deviation.

FIG. 23 is a block diagram showing the configuration of a grayscale difference detection circuit.

FIG. 24 is an example of an inspection result according to the present invention.

FIG. 25 is a block diagram showing the configuration of a system for performing failure analysis according to the present invention.

FIG. 26 is a block diagram showing the configuration of a system for checking the cleaning process.

FIG. 27 is a block diagram showing an example of a cleaning process.

FIG. 28 is a block diagram showing the structure of a lithography process according to the present invention.

FIG. 29 is a block diagram showing an embodiment of wafer processing according to the present invention.

FIG. 30 is a block diagram comparing and explaining effects of the present invention and a conventional example.

FIG. 31 is a block diagram illustrating how to classify defects.

FIG. 32 is a diagram illustrating a conventional defect detection method.

FIG. 33 is a block diagram illustrating the principle of the present invention.

[Explanation of symbols]

1 ... Wafer, 2 ... Illumination light, 3 ... Objective lens, 4 ... Image sensor, 10a, 10b ... 1st-order differentiation circuit, 11a, 1
1b ... Second-order differentiation circuit, 12a, 12b, 13a, 13b
... Cutout circuit, 14a to 14y ... Polarity comparison circuit, 15
15y ... Counter circuit, 16 ... Positional deviation amount detection circuit,
17a to 17y ... Delay circuit, 18a to 18y ... Region selection circuit, 19 ... AND circuit, 7 ... Image processing device, 20 ... Edge detection circuit, 21 ... Binarization circuit, 22 ... Mismatch detection circuit, 23 ... Delay circuit, 24 ... Alignment circuit, 25 ... Defect determination circuit, 26-29 ... Shift register, 30 ... EXO
R circuit, 31 ... Counter, 32 ... Minimum value detection circuit, 3
6, 37, 39, 40 ... Shift register, 45 ... Judgment device, 46 ... Adder, 47 ... Mismatch detection circuit, 48 ... Mismatch detection pixel number detection circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/027 (72) Inventor Makihira Tanaka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Production Technology Laboratory

Claims (22)

[Claims] 1. A pattern image of a semiconductor or the like in the process of manufacturing is detected, and the detected image signal is compared with a reference image signal to detect a positional deviation of the pattern as a shape mismatch or a pattern quality. A process for manufacturing a pattern of a semiconductor or the like, wherein the process is performed after the process treatment, and the quality of the process is judged based on the shape mismatch and the quality. 2. A pattern image of a semiconductor or the like in the process of manufacturing is detected, and the detected image signal is compared with a reference image signal to detect the positional deviation of the pattern as a shape mismatch before and after the process processing. A method of manufacturing a pattern of a semiconductor or the like, which is characterized by determining the harmfulness of a foreign substance based on the shape mismatch. 3. A method for manufacturing a pattern of a semiconductor or the like according to claim 1, wherein the quality of the process is judged by using the number or distribution of the detected shape mismatches. 4. A method for manufacturing a pattern of a semiconductor or the like according to claim 2, wherein the harmfulness of the foreign matter is judged by using the number or distribution of the detected shape mismatches. 5. A method of manufacturing a pattern of a semiconductor or the like according to claim 1, wherein the condition of the process is determined by using the number or distribution of the detected shape mismatches. 6. A method of manufacturing a pattern of a semiconductor or the like according to claim 2, wherein the quality of the process is judged by judging the harmfulness of the foreign matter by using the number or distribution of the detected shape mismatches. 7. A method of manufacturing a pattern of a semiconductor or the like according to claim 1, wherein the positional deviation of the pattern is detected by differentiating the image signal and comparing the polarities thereof. 8. An image of a pattern of a semiconductor or the like being manufactured is detected, and the detected image signal is compared with a reference image signal,
A method for manufacturing a pattern of a semiconductor or the like, wherein different process treatments are performed depending on the state of non-coincidence by detecting misalignment of patterns as a non-coincidence of shapes. 9. An image of a pattern of a semiconductor or the like being manufactured is detected, and the detected image signal is compared with a reference image signal,
A method for manufacturing a pattern of a semiconductor or the like, wherein the wafer transfer is controlled according to the state of mismatch by detecting the positional deviation of the pattern as the shape mismatch. 10. A pattern image of a semiconductor or the like in the process of manufacturing is detected, and the detected image signal is compared with a reference image signal to detect a positional deviation of the pattern as an inconsistency in shape or a condition of the pattern. A pattern manufacturing line for a semiconductor or the like having means for performing the process after the process processing and determining the quality of the process based on the shape mismatch and the quality. 11. A method for detecting a pattern image of a semiconductor or the like in the process of manufacturing, comparing the detected image signal with a reference image signal, and detecting a positional deviation of the pattern as a shape mismatch before and after the process processing. A line for manufacturing a pattern of a semiconductor or the like having means for carrying out and judging the harmfulness of a foreign substance based on this shape mismatch. 12. A pattern manufacturing line for a semiconductor or the like according to claim 10, which has means for judging the quality of the process by using the number or distribution of the detected shape mismatches. 13. A pattern manufacturing line for a semiconductor or the like according to claim 11, comprising a means for judging the harmfulness of a foreign substance by using the number or distribution of detected shape mismatches. 14. A pattern manufacturing line for a semiconductor or the like according to claim 10, further comprising means for conditionally setting a process by using the number or distribution of detected shape mismatches. 15. A pattern manufacturing line for a semiconductor or the like according to claim 11, comprising means for judging the quality of the process by judging the harmfulness of the foreign matter by using the number or distribution of the detected shape mismatches. 16. A pattern manufacturing line for a semiconductor or the like according to claim 10 or 11, wherein the positional deviation of the pattern is detected by differentiating the image signal and comparing the polarities thereof. 17. A pattern image of a semiconductor or the like in the process of manufacturing is detected, the detected image signal is compared with a reference image signal, and the positional deviation of the pattern is detected as a shape mismatch. A pattern manufacturing line for semiconductors or the like characterized by performing different process treatments. 18. A pattern image of a semiconductor or the like in the process of manufacturing is detected, the detected image signal is compared with a reference image signal, and the positional deviation of the pattern is detected as a shape mismatch, whereby the mismatch status is detected. , A pattern manufacturing line for semiconductors or the like characterized by controlling the transfer of wafers. 19. When classifying detected defects by type, it is necessary to visually identify the types of defects for unclassified defects, and to automatically classify defects of the same type as those already classified. Characteristic pattern inspection method for semiconductors and the like. 20. The pattern inspection method for a semiconductor or the like according to claim 19, wherein said defect classification is performed based on the size of the defect. 21. The pattern inspection method for a semiconductor or the like according to claim 19, wherein said defect classification is performed based on the shape of the defect and the density of light reflected from the defect portion. 22. An unclassified defect is visually inspected to identify the type of defect, and a defect of the same type as an already classified defect is not necessarily visually inspected to perform a pattern inspection to obtain a defect. A method for manufacturing a pattern of a semiconductor or the like, characterized by controlling the process based on the obtained information.