JPH0766081A - Chip type solid electrolytic capacitor - Google Patents

Abstract

PURPOSE:To provide a chip type solid electrolytic capacitor having the improved sticking strength of an anode terminal at the time of mounting a chip type solid electrolytic capacitor of a simple resin encapsulated type on a printed board. CONSTITUTION:An anode terminal consists of two layers of the by turns formed plated layer 6 and soldered layer 7 on an anode lead planted surface while consisting of three layers of the by turns formed conductive layer 4a, plated layer 6 and soldered layer 7 having unevenness of 5 to 20mum on the peripheral part of the anode lead planted surface. Accordingly, the sticking strength at the time of soldered mounting of a chip on a printed board is sharply improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type solid electrolytic capacitor, and more particularly to the structure of an anode terminal.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional chip type solid electrolytic capacitor is assembled by attaching external positive and negative electrode leads to both ends of a capacitor element 11 manufactured by a publicly known technique, and then packaging it by transfer molding. There is. However, this type of chip-type solid electrolytic capacitor has a low volumetric efficiency because the volume is taken up by the exterior resin layer 12 and the positive / negative electrode lead connecting portion. Therefore, in order to increase the volume efficiency and reduce the size, the conductor layer 17, the plating layer 18, and the solder layer 19 are three layers as shown in FIG. 4, or the plating layer 18 and the solder layer 19 are two layers as shown in FIG. There is a chip type solid electrolytic capacitor in which positive and negative terminals are directly formed on both ends of the element.

[0003]

The above-mentioned conventional chip type solid electrolytic capacitor has the following problems due to its terminal structure. (1) When the anode terminal is composed of three layers of the conductor layer 17, the plating layer 18, and the solder layer 19, the conductivity of the conductor layer that is responsible for connection with the anode lead 15 is one digit or more larger than that of the anode lead. Since it is formed of a conductive paste, the reliability of electrical connection between the anode lead and the conductor layer is low, peeling easily occurs, and the dielectric loss of the capacitor increases. (2) In order to solve the problem described in the above item (1), there is a method in which a plating layer having a thermal expansion coefficient close to that of the anode lead is connected to the anode lead, and the anode terminal is formed by two layers of the plating layer and the solder layer. However, in this case, since the exterior resin layer 16 and the anode terminal are connected by the exterior resin layer 16 having a smooth surface and the plating layer, the adhesive force is weak and the chip fixing force when mounted on a printed board is weak.

An object of the present invention is to provide a chip-type solid electrolytic capacitor which is improved in the fixing strength of the anode terminal when the simple resin-coated chip-type solid electrolytic capacitor is mounted on a printed board.

[0005]

A chip-type solid electrolytic capacitor according to the present invention is an element in which an oxide film, a solid electrolyte layer, and a cathode conductor layer are sequentially formed on an anode body made of valve metal with an anode lead set up. And the insulating outer resin layer deposited on the entire outer peripheral surface of the element except the opposing surface of the anode lead embedding surface, the anode lead embedding surface and the anode terminals formed on the peripheral portion, and the anode lead embedding surface facing each other. In a chip type solid electrolytic capacitor having a surface and a cathode terminal formed on the periphery thereof, the anode terminal is composed of two layers, a plating layer and a solder layer, which are sequentially formed on the anode lead embedding surface. On the peripheral part of the above, it is characterized by comprising three layers of a conductor layer, a plating layer and a solder layer which are sequentially formed.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a chip type solid electrolytic capacitor of one embodiment of the present invention.

As shown in FIG. 1, in a capacitor element 1 in which a cathode conductor layer (not shown) is formed by a known technique, an exterior resin is formed on the entire outer peripheral surface except the opposing surface of the anode lead 2 and the anode lead embedding surface. Form layer 3.

Next, an epoxy resin, a curing agent, a carbon powder, a palladium powder, and a calcium carbonate powder having a particle size of 5 to 20 μm are kneaded in a portion adjacent to the anode lead embedding surface and in the vicinity of the anode lead embedding surface, and a small amount. The paste diluted with the organic solvent is applied and heated in an atmosphere of 150 to 200 ° C. for 30 minutes to be thermally cured to form the first conductor layer 4a.

Subsequently, the same paste as that used to form the first conductor layer 4a is applied to the opposing surface of the anode lead embedding surface and its peripheral portion, and the paste is applied in an atmosphere of 150 ° C to 200 ° C for 30 minutes. The second conductor layer 4 is heated for a minute to be thermoset.
b is formed.

Then, a butyl acetate solution of an amine compound of palladium is applied to the anode lead 2 and the anode lead embedding surface,
Palladium, which is a metal catalyst, is attached by thermal decomposition at 185 ° C. for 30 minutes.

Next, the conductor layers 4a and 4b containing palladium
Further, the plating layer 6 is formed on the anode lead 2 and the anode lead planting surface to which palladium is attached.

Next, a solder layer 7 is formed on the plating layer 6,
The anode lead 2 is cut to form a chip type solid electrolytic capacitor.

The chip type solid electrolytic capacitor of Example 1 and the conventional example in which the anode terminal is composed of only two layers of a plating layer and a solder layer, which are sequentially formed on an exterior resin having a smooth surface, are prepared on a printed board. Solder mounting was conducted to investigate the chip adhesion strength. The results are shown in Table 1.

[0014]

[Table 1]

It can be seen from Table 1 that the adhesive strength of Example 1 is greatly improved.

FIG. 2 is a sectional view of a chip type solid electrolytic capacitor according to another embodiment of the present invention.

The exterior resin layer 3 is formed in the same manner as in Example 1. Next, an epoxy resin, a palladium powder, a carbon powder, a curing agent and a foaming agent are kneaded in a portion adjacent to the anode lead embedding surface and adjacent to the anode lead embedding surface, and a paste diluted with a small amount of an organic solvent is applied to the surface. The first porous conductor layer 5a is formed by heating for 1 hour in an atmosphere of ° C. and thermosetting. The first porous conductor layer 5a has a large number of pinholes of 5 to 20 μm due to the function of the foaming agent during heating.

Next, the same paste as that used for forming the first porous conductor layer 5a is applied to the surface opposite to the anode lead embedding surface and its peripheral portion, and the paste is applied in an atmosphere of 120 ° C.
The second porous conductor layer 5b is formed by heating for a time.

Then, a butyl acetate solution of an amine compound of palladium is applied to the anode lead 2 and the anode lead embedding surface, and 1
Thermal decomposition is performed under the conditions of 85 ° C. for 30 minutes to attach palladium as a metal catalyst.

Next, the conductor layers 5a and 5b containing palladium
Further, the plating layer 6 is formed on the anode lead 2 and the anode lead embedding surface to which palladium is attached, the solder layer 7 is formed on the plating layer, and the anode lead 2 is cut to form a chip type solid electrolytic capacitor. .

The chip type solid electrolytic capacitor of Example 2 and the conventional example, in which the anode terminal is composed of only two layers of a plating layer and a solder layer, which are sequentially formed on an outer resin having a smooth surface, are prepared on a printed board. Solder mounting was conducted to investigate the chip adhesion strength. The results are shown in Table 2.

[0022]

[Table 2]

As shown in Table 2, in Example 2 as well as in Example 1, the fixing strength was increased.

[0024]

As described above, according to the present invention, since the anode terminal is composed of the two layers of the plating layer and the solder layer which are sequentially formed on the anode lead embedding surface, high electrical connection reliability can be obtained and the anode lead can be obtained. 5-2 formed in sequence on the periphery of the planting surface
3 layers of conductor layer, plating layer and solder layer with 0 μm unevenness
Since it is a layer, it has the effect of improving the fixing strength of the chip when it is mounted on the printed board.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a chip-type solid electrolytic capacitor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a chip-type solid electrolytic capacitor of another embodiment of the present invention.

FIG. 3 is a cross-sectional view of an example of a chip-type solid electrolytic capacitor which is packaged by conventional transfer molding.

FIG. 4 is a cross-sectional view of an example of a chip-type solid electrolytic capacitor in which conventional positive and negative terminals are directly formed on both ends of the element.

FIG. 5 is a cross-sectional view of another example of a chip-type solid electrolytic capacitor in which positive and negative electrode terminals are directly formed on both ends of the element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Capacitor element 2 Anode lead 3 Exterior resin layer 4a First conductor layer 4b Second conductor layer 5a First porous conductor layer 5b Second porous conductor layer 6 Plating layer 7 Solder layer 11 Capacitor Element 12 Exterior resin layer 13 External cathode lead 14 External anode lead 15 Anode lead 16 Exterior resin layer 17 Conductor layer 18 Plating layer 19 Solder layer

Claims (2)

[Claims] 1. An element in which an oxide film, a solid electrolyte layer, and a cathode conductor layer are sequentially formed on an anode body made of valve metal having an anode lead planted thereon, and all the elements except a surface opposite to the anode lead planting surface. A chip having an insulating exterior resin layer deposited on the outer peripheral surface, an anode lead forming surface and an anode terminal formed on the peripheral portion thereof, and a surface facing the anode lead forming surface and a cathode terminal formed on the peripheral portion. -Type solid electrolytic capacitor, the anode terminal is composed of two layers, a plating layer and a solder layer, which are sequentially formed on the anode lead planting surface, and a conductor layer and a plating, which are sequentially formed on the periphery of the anode lead planting surface. 3 layers and solder layers
A chip-type solid electrolytic capacitor characterized by comprising layers. 2. The chip-type solid electrolytic capacitor according to claim 1, wherein the conductor layer is a porous conductor layer.