JPH0764520A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide an image display device capable of reducing chip nonuniformity phenomen to cause the reduction of picture quality of liquid crystal display. CONSTITUTION:This device is equipped with a controller 26 which controls every part by outputting a control signal, a reference voltage generation circuit 27, an A/D converter 28 which converts a video signal according to the voltage, a scan electrode driving circuit 29 which performs the horizontal scan of a scan electrode, a signal electrode driving circuit 30 which outputs the video signal converted to digital data, a liquid crystal panel 31, and a driving voltage generation circuit 32, and the controller 26 outputs H and V correction signals to the voltage generation circuit 27 at the switching part of an LSI chip, and the reference voltage generation circuit 27 superimposes the correction components of the H and V correction signals outputted from the controller 26 on ordinary reference voltages on High and Low sides, and supplies the reference voltages RT, BT on the High and Low sides to the A/D converter 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a liquid crystal projector, a liquid crystal television, etc., and more particularly to a liquid crystal display device having a liquid crystal display circuit for driving a liquid crystal panel with high duty and a large number of pixels. Regarding

[0002]

2. Description of the Related Art In recent years, LCD (Liquid Crystal Display)
Device) is becoming larger, but in such a large-capacity LCD, the unevenness of contrast occurs due to the dullness of the applied drive waveform, which greatly affects the image quality. Since the liquid crystal is a capacitive load and is driven via a transparent electrode having a finite resistance, the drive waveform actually applied to the liquid crystal is a more or less dull waveform. In particular, in the case of a large-capacity LCD, if the pixel size is kept constant, the capacity of the liquid crystal to be driven and the wiring resistance of the transparent electrode increase and the frequency of the drive waveform rises, so the blunting of the waveform cannot be ignored.

In a conventional liquid crystal display device, in the case of a multi-pixel device, a plurality of drivers (liquid crystal driving LSI) as shown in FIG. 9, for example, are used for display.

FIG. 9 is a diagram showing a conventional large-capacity LCD module, and FIG. 10 is a diagram showing its LCD panel.

In FIG. 9, an LCD 10 includes a segment LSI driver (segment LSI chip) 11,
Segment glass 12 on which 11 ... Is installed, common LSI driver (common LSI chip) 13, 13 ...
And a common glass 14 on which are installed, and an FPC (flexible printed cable) 15 for connecting the plurality of liquid crystal driving LSIs and a liquid crystal driving circuit (not shown).

As shown in FIG. 9, segment glass 1
2 are connected to the upper and lower two segment LSI drivers 11, 11 ... And the common glass 14 is also connected to the two common LSI drivers 13, 13 ... .. and common LSI drivers 13, 13
Four areas are created on the display screen according to the combination of the drivers.

[0007]

By the way, it is assumed that the segment LSI drivers 11, 11 ... Have a 180-output driver and the common LSI drivers 13, 13 ... Have a 110-output driver. Then, Figure 1
As shown in 0, segment electrodes (signal electrodes) Y1-Y1
80 and Y181-Y360 and common electrode (scan electrode)
With the division of X1-X110 and X111-X220,
There are four areas A, B, C and D. At this time, for example, when the same halftone is displayed on the entire display screen, Y1 to Y180 or Y181 may be caused due to the blunted output waveforms of the segment LSI drivers 11, 11 ... And the common LSI drivers 13, 13. From X to Y360 and from X1 to X110 or from X111 to X220, light and dark may occur. Here, the blunting of the output waveform is caused by the reason of the manufacturing process of the chip (circulation of the power supply, etc.) and is difficult to avoid.

For example, as a result of routing the power supply line in the segment LSI chip, the signal electrode near the power supply (eg Y1) and the signal electrode far from the power supply (eg Y180) are affected by the voltage drop due to the resistance of the power supply line. received,
There is uneven brightness as shown in FIG. In this case, the difference between bright and dark and dark and bright appears depending on whether the power line is routed from left or right. This makes Y180 and Y181
In addition, there was a case where a dividing line was seen between X110 and X111, and it might look like chip unevenness.

It is an object of the present invention to provide a liquid crystal display device capable of reducing the chip non-uniformity phenomenon which leads to the deterioration of the image quality of the liquid crystal display.

[0010]

The invention according to claim 1 is
To achieve the above object, a liquid crystal panel having a plurality of signal electrodes and a plurality of scanning electrodes, a scanning electrode drive circuit including a plurality of scanning side drivers that output horizontal scanning signals to the scanning electrodes, and a video signal are input. A liquid crystal display device having a signal electrode drive circuit including a plurality of signal side drivers for outputting display signals to the signal electrodes, wherein a video signal input to the signal electrode drive circuit is supplied to the scanning side and the signal side. It is characterized in that it is provided with a correction means for correcting so as to cancel the rounding of the waveform of the output signal from at least one driver on the side.

According to a second aspect of the present invention, a liquid crystal panel having a plurality of signal electrodes and a plurality of scanning electrodes, a scanning electrode drive circuit for outputting a horizontal scanning signal to the scanning electrodes, and an image according to a supplied reference voltage. An AD converter that converts a signal into digital data, a reference voltage generation circuit that supplies a predetermined reference voltage to the AD converter, and a video signal converted into digital data by the AD converter are input, and a display signal is input to the signal electrode. And a signal electrode driving circuit for outputting the signal electrode driving circuit, wherein the reference voltage generating circuit generates a correction signal for canceling the rounding of the output waveform from each driver, and the generated correction signal is applied to the signal electrode. Corrects the reference voltage generated so that it is superimposed on the video signal input to the drive circuit. A correction means is characterized in that so as to correct the image signal inputted to the signal electrode driving circuit by supplying the corrected reference voltage to the AD converter by the correction means.

For example, as described in claim 3, the correction means performs the correction at the transition of the plurality of drivers on at least one of the scanning side and the signal side for driving the liquid crystal panel. Good.

[0013]

According to the present invention, when the video signal is input, the input video signal is corrected by the correction means, and the corrected video signal is input to the signal electrode drive circuit. In this case, the correction means corrects the video signal input to the signal electrode drive circuit so as to cancel the rounding of the waveform of the output signal from the driver on at least one of the scanning side and the signal side. Then, the scan electrode driving circuit outputs the corrected video signal to the plurality of signal electrodes of the liquid crystal panel to drive the liquid crystal panel.

Therefore, it is possible to reduce the variation of the video signal output to the liquid crystal panel due to the rounding of the output waveform of each driver, and to reduce the chip non-uniformity phenomenon which causes the deterioration of the image quality of the liquid crystal display.

[0015]

EXAMPLES Examples will be described below with reference to FIGS.

First Embodiment FIGS. 1 to 6 are views showing a first embodiment of a liquid crystal display device, and this embodiment is an example in which the liquid crystal display device is applied to a liquid crystal television.

First, the structure will be described. FIG. 1 is a block diagram of the liquid crystal television 21.

In FIG. 1, a liquid crystal television 21 includes an antenna 22, a tuner 23, an IF circuit 24, and a chroma circuit 2.
5, controller 26, reference voltage generation circuit 2
7, an A / D converter 28, a scan electrode drive circuit 29, a signal electrode drive circuit 30, a liquid crystal panel 31, and a drive voltage generation circuit 32.

The antenna 22 receives radio waves from the tuner 2
The tuner 23 selects the designated channel according to the tuning control signal VT input from the controller 26, converts the received radio wave supplied from the antenna 22 into an intermediate frequency signal, and outputs the intermediate frequency signal to the IF circuit 24.

The IF circuit 24 is composed of an intermediate frequency amplification circuit, a video detection circuit, a video amplification circuit and the like. The intermediate frequency signal input from the tuner 23 is subjected to video detection by the video detection circuit to extract a color video signal, An audio signal is extracted from this color video signal and output to an audio circuit (not shown), the video amplification circuit amplifies the color video signal and outputs it to the chroma circuit 25. Also, from the color video signal, a horizontal synchronization signal Hsync is output. And vertical sync signal Vs
The ync is taken out and output to the controller 26.

The chroma circuit 25 separates the R, G and B color video signals from the color video signal input from the IF circuit 24 and outputs the separated video signals to the A / D converter 28.

The controller 26 is the A / D converter 2
8, CPU (Central Proc) that controls the scan electrode drive circuit 29, the signal electrode drive circuit 30, and the drive voltage generation circuit 32.
essing unit) and the like, which outputs a tuning control signal VT to the tuner 23 according to a tuning key operation, and a horizontal synchronizing signal Hsy input from the IF circuit 24.
Based on nc and the vertical synchronization signal Vsync, various timing control signals for controlling the scan electrode drive circuit 29 and the signal electrode drive circuit 30 are generated and output to the scan electrode drive circuit 29 and the signal electrode drive circuit 30.

Further, the controller 26 generates and outputs a sampling clock to the A / D converter 28,
The H correction signal and the V correction signal are output to the reference voltage generation circuit 27. The H correction signal and the V correction signal serve as trigger signal generation trigger pulses for generating the reference voltages RT and RB on which the correction signal is superimposed in the reference voltage generation circuit 27, and the segment LSI driver. Are output to the reference voltage generation circuit 27 at the transitions of the 11, 11, ..., Common LSI drivers 13, 13. For example, as shown in FIG. 10, if the segment LSI drivers 11, 11 ... Have 180 outputs and the common LSI drivers 13, 13 ... Have 110 outputs, then Y1 -Y180 and Y181-Y360 and X1-X110 and X111-X220 form four areas A, B, C, and D. At this time, Y180 changes from Y180 to Y181 and X110 changes to X111. The H correction signal shown in FIG. 3B and the V correction signal shown in FIG. 4B are output at the timing of X111.

The reference voltage generation circuit 27 supplies a high-side reference voltage R to the A / D converter 28 based on the H correction signal output from the controller 26.
It is a circuit that generates the T and Low side reference voltages RB and also generates the High side reference voltage RT and the Low side reference voltage RB that are supplied to the A / D converter 28 based on the V correction signal. That is, the reference voltage generation circuit 27 outputs the normal high-side and low-side reference voltages supplied to the A / D converter 28 from the controller 26 as shown in FIGS. 3C and 4C. A correction component (low-pass filter component) generated based on the H correction signal and the V correction signal is superimposed,
The high-side reference voltage RT and the low-side reference voltage RB are supplied to the A / D converter 28.

The A / D converter 28 includes a chroma circuit 25.
Each color video signal separated by is converted into a predetermined digital signal based on the sampling clock (High side reference voltage RT, Low side reference voltage RB) from the controller 26 and output to the signal electrode drive circuit 30.

The scan electrode drive circuit 29 is provided with a liquid crystal panel 31.
The signal electrode drive circuit 30 is composed of a plurality of (for example, two) LSI drivers that sequentially scan 220 scan electrodes provided in the liquid crystal panel 31.
A plurality of (eg, four) LSs that sequentially scan the signal electrodes of the book
It is composed of an I driver.

The drive voltage generating circuit 32 is the controller 2
6 based on the control signal output from the scan electrode drive circuit 29
And a drive voltage to be supplied to the signal electrode drive circuit 30.

As described above, in this embodiment, in order to reduce the chip unevenness phenomenon, the signal (analog) which is the source of the data (digital) to be displayed is converted by the A / D converter 28.
It is configured to be corrected at the stage of performing / D conversion.

FIG. 2 is a circuit configuration diagram of the reference voltage generating circuit 27.

In FIG. 2, the reference voltage generating circuit 27 generates a high side reference voltage RT and a low side reference voltage RB based on the H correction signal and the V correction signal from the controller 26, and generates the reference voltage. The reference voltage generation unit 41 and the stabilization unit 42 that stabilizes the generated reference voltage.

The reference voltage generator 41 includes transistors Tr1 to Tr4, inverters 43 and 44, and a resistor R1.
To R9, variable resistors VR1 to VR4 and capacitors C1,
The stabilizing unit 42 includes an operational amplifier OP.
1, OP2 and transistors Tr5 and Tr6.

The transistor Tr1 is turned on when the H correction signal input via the resistor R1 is at the H level (that is, when the H correction signal is not output), and is referred to the variable resistor VR3 via each resistor. Output voltage level.

Further, the inverted output of the H correction signal from the inverter 43 is input to the transistor Tr2, and the transistor Tr2 is turned on when the H correction signal is at the L level (that is, when the H correction signal is output). Then, the resistor R5 and the capacitor C1 generate the H correction component shown in FIG. 3C with the time constants of R5 and C1 and output the reference voltage level of the H correction component to the variable resistor VR3 via each resistor.

Similarly, the transistor Tr3 is turned on when the L correction signal is at the H level (that is, when the H correction signal is not output), and the variable resistor VR is connected via each resistor.
The reference voltage level is output to 4.

The inverted output of the V correction signal from the inverter 44 is input to the transistor Tr4, and the transistor Tr4 is turned on when the V correction signal is at the L level (that is, when the H correction signal is output). Then, the resistor R6 and the capacitor C2 generate the L correction component shown in FIG. 4C with the time constants of R6 and C2, and output the reference voltage level of the L correction to the variable resistor VR4 via each resistor.

The stabilizing unit 42 stabilizes the reference voltage generated by the reference voltage generating unit 41,
This is a circuit for outputting as the high side reference voltage RT and the low side reference voltage RB. Specifically, the operational amplifiers OP1 and OP2 lower the output impedance of the potential appearing in the variable resistors VR3 and VR4, and the transistors Tr5 and Tr6 output levels. Is stabilized and output. Output waveforms of the high-side reference voltage RT and the low-side reference voltage RB are shown in FIGS. 3 (d) (e) and 4 (d) (e).

Next, the operation of this embodiment will be described.

As described above, as a cause of the chip unevenness phenomenon, as shown in FIG. 9, one LSI (common LSI driver 13, 13, ..., Segment LSI) is used.
The outputs of the drivers 11, 11, ... Are not the same in all characteristics. That is, Y1 (Y1
81) to Y180 (Y360) or X1 (X111)
From X to X110 (X220), chip unevenness occurs in which the brightness is not constant in appearance. Here, the reason why the brightness changes although the displayed digital data itself does not change is as shown in FIG.
1 (Y181) and Y180 (Y360) or X1 (X1
It is considered that the cause is that the effective voltage of the liquid crystal changes between 11) and X110 (X220) due to the change in the waveform bluntness. The solution is
Needless to say, eliminating the bluntness is the best thing, but it is difficult at present. As a next-best method, it may be possible to make the dull manner constant. However, it is considered that the cause of this dull manner is not constant because the power supply inside the LSI is distributed. There is also a method of making the other constant, which is difficult due to the configuration of the LSI.

Therefore, in the present embodiment, by correcting the displayed data with respect to this brightness unevenness, it is possible to realize a high-quality image without chip unevenness.

As a method of correcting the data to be displayed, in this embodiment, the A / D converter 28 is used for A / D conversion.
When the D conversion is performed, the reference voltage supplied to the A / D converter 28 is corrected by using the reference voltage generation circuit 27.

First, as shown in FIG. 10, Y1 (Y18
1) to Y180 (Y360) or X1 (X111) to X110 (X220) is changed from dark to bright.

In the reference voltage generating circuit 27 of FIG. 2, the high side reference voltage RT and the low side reference voltage RB are respectively supplied to the A / D converter 28 as Hi.
Input to gh side and Low side. The respective levels of this voltage correspond to the variable resistance VR of the reference voltage generator 41.
3 and VR4, the operational amplifier OP of the stabilizing unit 42
1, OP2 and the transistors Tr3 and Tr4 are stabilized. Here, the High side of the resistor R7 and the L side of the resistor R9
Conventionally, the voltage on the ow side is fixed to a constant value, but in the present embodiment, this voltage is set to FIGS. 3 (d) (e) and 4 (d).
The correction is performed by changing as shown in (e).

Specifically, first, Y1 (Y181) → Y180 on the segment LSI driver 11, 11 ... Side.
Regarding the correction of (Y30), the H correction signal shown in FIG. 3B is a pulse signal in which the sampling start time in 1H, that is, the data indicating Y1 and the position indicating the data indicating Y181 become Low for a certain period from a certain position. Is.

This H correction signal is input to the transistor Tr1 via the resistor R1 of the reference voltage generator 41 and to the transistor Tr2 via the inverter 43 and the resistor R2. The transistor Tr1 receives the H correction signal at the H level. ON, transistor Tr2 is H
Turns on when the correction signal is at L level. A normal reference voltage is generated by the output of this transistor Tr1,
The H correction component is generated by the resistor R5 and the capacitor C1 which received the output of the transistor Tr2. The signal created in the low-pass filter portion composed of the resistor R5 and the capacitor C1 becomes the "signal at point A" shown in FIG.

The level H at that time is determined by adjusting the variable resistor VR1 of the reference voltage generator 41 shown in FIG. The level H of the signal shown in FIG. 3 (c) is a level for eliminating the luminance change of Y1 (Y181) and Y180 (Y360). By appropriately adjusting this signal level, the break point of Y180 and Y181 can be set. You can get confused. This “signal at point A” is the H of the resistor R7 of the reference voltage generator 41 shown in FIG.
The high-side reference voltage RT and the low-side reference voltage RB capable of obtaining the reference voltages RT and RB as shown in FIG. 3D and FIG.
The D / D converter 28 inputs the signals, and the A / D converter 28 converts each color video signal into a digital signal and outputs the digital signal to the signal electrode drive circuit 30.

Then, the reference voltages RT and RB
The data A / D converted by the A / D converter 28 based on the
When you try to display, the corrected data (digital) that matches this liquid crystal panel is automatically added,
The displayed picture has the same gradation on the entire screen in the Y direction segment LSI driver 11, 11, ...

Further, X1 (X111) → X110 (X2
20) For correction of (common LSI drivers 13, 13 ...) Similarly to the segment LSI drivers 11, 11, ..., Sampling start time during 1V period, that is, data for displaying X1 and data for displaying X111. The reference voltage generation unit 41 uses a pulse signal that becomes Low for a certain period from a certain position as a V correction signal (FIG. 4B).
2 is input to the resistor R3 of the resistor R9, and the "signal at the point B" shown in FIG. 2 generated based on this V correction signal is input to the low side of the resistor R9.
Get T, RB. At this time, by adjusting the "level V" of the "signal at the point B" by the variable resistor VR2 of the reference voltage generation unit 41, the boundary between X110 and X111 can be obscured.

Further, as shown in FIG. 5 which is an enlarged view of the reference signals RT and RB surrounded by circles in FIGS. 4D and 4E, when the reference voltages RT and RV are enlarged, the above-mentioned figures are obtained. It can be seen that the three reference signals RT and RB are multiplexed. As a result, the correction on the side of the segment LSI drivers 11, 11 ... and the common LSI driver 1
Reference voltage R with multiple corrections on the side
The data that has been A / D converted by T and RB is automatically corrected in both the Y direction and the X direction.
It is possible to make the boundary between 81 and X110 and X111 invisible, and to reduce the chip unevenness phenomenon.

As described above, the liquid crystal display device of the present embodiment outputs the control signal to control the respective parts, the reference voltage generating circuit 27 for supplying the corrected reference voltage to the A / D converter 28, An A / D converter 28 that converts a video signal into digital data according to the supplied reference voltage, a scan electrode drive circuit 29 that horizontally scans the scan electrodes, and an A / D converter 28
The controller 26 is provided with a signal electrode drive circuit 30 for outputting a video signal converted into digital data by a signal electrode to a signal electrode, a liquid crystal panel 31, and a drive voltage generation circuit 32.
At the transition of the SI driver, the H correction signal and the V correction signal are output to the reference voltage generating circuit 27, and the reference voltage generating circuit 27 supplies the normal high-side and low-side reference voltages to the A / D converter 28. H correction signal output from the controller 26, V
The correction component (low-pass filter component) generated based on the correction signal is superimposed, and the High-side reference voltage R
Since the T and Low-side reference voltage RB is supplied to the A / D converter 28, the chip unevenness phenomenon due to the rounding of the output waveform due to the difference in wiring resistance when the LSI driver is connected to the electrodes of the liquid crystal panel 31 and wired. Can be reduced.

In the first embodiment, Y1 (Y181) →
Y180 (Y360) or X1 (X111) → X110
The case where (X220) is from dark to bright has been described, but the same can be applied to the case where each is from bright to dark.
This will be described as an example.

Second Embodiment FIGS. 7 and 8 are views showing a second embodiment of the liquid crystal display device, FIG. 7 is a circuit configuration diagram of the reference voltage generating section 51 of the reference voltage generating circuit, and FIG. 8 is an H correction. It is a waveform diagram of a signal and a V correction signal.

In FIG. 7, the reference voltage generating section 51 of the reference voltage generating circuit 27 includes a transistor T
r11, Tr12, resistors R11 to R17, variable resistor VR
11 to VR14 and capacitors C11 and C12.

The transistor Tr11 has a resistor R11.
When the H correction signal input via the is at the H level (that is, when the H correction signal is output), it is turned on, and the reference voltage level is output to the variable resistor VR13 via each resistor. Further, the transistor Tr11 has a resistor R
12 and the capacitor C11 are connected, and R12 and C11
The H correction component shown in FIG. 8B is generated with the time constant of, and the reference voltage level of the H correction component is output to the variable resistor VR13 via each resistor.

Similarly, the transistor Tr12 is L
Turns on when the correction signal is at the H level (that is, when the V correction signal is not output), and the variable resistance V
The reference voltage level is output to R14. A resistor R14 and a capacitor C12 are connected to the transistor Tr12, and the time constants of R14 and C12 are shown in FIG.
The V correction component shown in (d) is generated and the reference voltage level of the V correction component is output to the variable resistor VR14 via each resistor.

As described above, in this embodiment, the H correction signal and the V correction signal are input to the reference voltage generator 51, and
The potentials at points A and B are changed as shown in FIGS. 8B and 8D to perform the correction. As a result, even when light → dark and dark → bright are combined, the chip unevenness due to the rounding of the output waveform can be similarly reduced.

In each of the above embodiments, the video signal is corrected by correcting the reference voltage supplied to the A / D converter, but any method can be used as long as it corrects the input video signal. It goes without saying that any method is acceptable.

In each of the above embodiments, the liquid crystal display device is applied to a liquid crystal television, but the present invention is not limited to this, and it goes without saying that it may be used in other devices such as a liquid crystal projector. .

Further, it goes without saying that the circuits, elements, the number of gates, and the types of the reference voltage generating circuit are not limited to those in the above-described embodiments.

[0059]

According to the first, second and third aspects of the present invention, the video signal input to the signal electrode drive circuit cancels the rounding of the waveform of the output signal from at least one of the scanning side and signal side drivers. Since the correction means for making such correction is provided, it is possible to reduce the variation of the video signal output to the liquid crystal panel due to the rounding of the output waveform of each driver, and to reduce the chip non-uniformity phenomenon that leads to the deterioration of the image quality of the liquid crystal display. As a result, the display quality of the image displayed on the liquid crystal panel can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a liquid crystal television of a first embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a circuit diagram of a reference voltage generation circuit of the same embodiment.

FIG. 3 is a timing chart of signal waveforms of the liquid crystal display device of the example.

FIG. 4 is a timing chart of signal waveforms of the liquid crystal display device of the example.

FIG. 5 is a timing chart of a signal waveform of a reference voltage of the liquid crystal display device of the example.

FIG. 6 is a timing chart of drive signal waveforms of the liquid crystal display device of the example.

FIG. 7 is a circuit diagram of a reference voltage generation circuit of a liquid crystal television of a second embodiment of the liquid crystal display device according to the present invention.

FIG. 8 is a timing chart of signal waveforms of the liquid crystal display device of the example.

FIG. 9 is a diagram showing a conventional large-capacity LCD module.

FIG. 10 is a diagram showing a display unevenness phenomenon of a conventional liquid crystal panel.

[Explanation of symbols]

11 Segment LSI driver (segment LS
I chip) 12 segment glass 13 common LSI driver (common LSI chip) 14 common glass 21 liquid crystal TV 22 antenna 23 tuner 24 IF circuit 25 chroma circuit 26 controller 27 reference voltage generation circuit 28 A / D converter 29 scanning electrode Drive circuit 30 Signal electrode drive circuit 31 Liquid crystal panel 32 Drive voltage generation circuit 41,51 Reference voltage generation unit 42 Stabilization unit Tr1 to Tr6, Tr11, Tr12 Transistor 43,44 Inverter R1 to R9, R11 to R17 Resistance VR1 to VR4 VR11-VR14 Variable resistance C1, C2, C11, C12 Capacitor OP1, OP2 Operational amplifier

Claims (3)

[Claims] 1. A liquid crystal panel having a plurality of signal electrodes and a plurality of scanning electrodes, a scanning electrode driving circuit including a plurality of scanning side drivers for outputting horizontal scanning signals to the scanning electrodes, and a video signal being input, A liquid crystal display device having a signal electrode drive circuit including a plurality of signal side drivers for outputting display signals to the signal electrodes, wherein a video signal input to the signal electrode drive circuit is supplied to the scanning side and the signal side. 2. A liquid crystal display device comprising: a correction unit that corrects so as to cancel the rounding of the waveform of the output signal from at least one of the drivers. 2. A liquid crystal panel having a plurality of signal electrodes and a plurality of scan electrodes, a scan electrode drive circuit for outputting a horizontal scan signal to the scan electrodes, and a video signal converted into digital data according to a supplied reference voltage. AD converter, a reference voltage generating circuit that supplies a predetermined reference voltage to the AD converter, and a signal electrode drive that inputs a video signal converted into digital data by the AD converter and outputs a display signal to the signal electrode A liquid crystal display device having a circuit, wherein the reference voltage generation circuit generates a correction signal for canceling the rounding of the output waveform from each driver, and the generated correction signal is input to the signal electrode drive circuit. A correction means for correcting the reference voltage generated so as to be superimposed on the video signal, A liquid crystal display device, wherein a video signal input to the signal electrode drive circuit is corrected by supplying the reference voltage corrected by the correction means to the AD converter. 3. The correction unit is configured to perform correction at a transition of a plurality of drivers on at least one of the scanning side and the signal side that drive the liquid crystal panel. 3. The liquid crystal display device according to any one of 2.