JP2003255909A - Display driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the driving method of a display driving device by which high display quality and low power consumption are realized. <P>SOLUTION: The gate driver 15 of the display driving device performs so- called interlaced scanning in which the driver performs scanning of odd numbered lines in the first half of a period when one picture is displayed and it performs scanning of even numbered lines in the latter half of the period. The common signal generating circuit 16 of the display device reverses the potential of a common voltage Vcom when scanning is changed over from the scanning of the odd numbered lines to the scanning of the even numbered lines, however, the circuit corrects the amplitude of the common voltage Vcom in accordance with whether a current scanning period is the scanning period of the odd numbered lines or the scanning period of the even numbered lines. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving device for driving a display panel in which pixels are arranged in a matrix, and particularly an active matrix liquid crystal display panel.

[0002]

2. Description of the Related Art A liquid crystal display device is known in which a liquid crystal is driven to display an image. In such a liquid crystal display device, an active matrix in which a plurality of scanning lines (scanning lines) and a plurality of signal lines (signal lines) are arranged orthogonally to each other on a liquid crystal display panel and pixels are formed near each intersection position. There is a method. In this active matrix liquid crystal display panel, the liquid crystal corresponding to each pixel is provided between a pixel electrode connected to a scanning line and a signal line via a switching element (for example, a thin film transistor) and a common electrode connected to a common line. And the array changes under the influence of an electric field formed between the two electrodes.

More specifically, the scanning line is connected to the gate electrode of the thin film transistor, the signal line is connected to the source electrode, a voltage is applied to the gate electrode via the scanning line to turn on the switching element, and its ON state. A voltage is applied to the pixel electrode of the pixel that has become a signal via a signal line. As a result, the voltage of the signal line is applied to the pixel electrode, and accordingly, an electric field is formed between the pixel electrode and the common electrode to drive the liquid crystal. That is,
The alignment of the liquid crystal is controlled by adjusting the voltage applied to each signal line.

A back light is arranged on the back of the liquid crystal display panel, and the light transmission amount of the back light is controlled according to the arrangement of the liquid crystal, so that the brightness (gradation) of each pixel is changed and desired. , Etc. are displayed.

In such a liquid crystal display device, inversion driving is generally performed. The inversion drive is a drive method in which the electric field (polarity) between the pixel electrode and the common electrode is inverted at a predetermined cycle.
As described above, the liquid crystal determines the arrangement (correctly, the direction) according to the electric field between the electrodes. However, if the electric field is applied only in one direction, the two glass substrates that sandwich the liquid crystal may be burned. , It may cause deterioration or damage of liquid crystal. Therefore, the electric field is reversed at any time to prevent these problems.

There are the following three inversion driving methods. However, a case will be described below in which a full image display is performed using all pixels on the liquid crystal display panel for each frame period. That is, the control system of the liquid crystal display device scans all the scanning lines within one frame period to display an image. Here, the frame is a unit of a period during which one image is displayed.

Frame inversion drive Frame inversion drive is a method of inverting the polarities (electric fields) of all the pixels arranged on the liquid crystal display panel every one frame period. FIG. 16A is a diagram showing an example of drive waveforms of a liquid crystal display device that executes frame inversion drive, and is for a case where all pixels on the liquid crystal display panel are displayed in black (or white). However, the number of scanning lines on the liquid crystal display panel is 2n. In the figure, Vcom indicates the time change of the potential of the common electrode, D indicates the time change of the potential of the signal line (signal voltage), and G _{1 to} G _2n indicate the time change of the potential of each of the 2n scanning lines. Shown respectively.

The gate driver for controlling the scanning lines G _{1 to} G _2n sequentially applies a high potential pulse of a predetermined width to each scanning line every frame period. Specifically, first, the scanning line G ₁ is in a high potential state, and after a lapse of a predetermined time, the scanning line G ₁ is in a low potential and the subsequent scanning line G ₂ is in a high potential.
In this way, the scanning lines G _{1 to} G _2n are sequentially set to a high potential, and the scanning line G _{1 is set} to a high potential again after one frame period has elapsed.

In each pixel, when the corresponding scanning line has a high potential, the switching element is turned on and is in a selected state. In this selected state, the voltage of the corresponding signal line is applied to the pixel electrode. In other words, when the scan line is at high potential,
Writing is performed on the corresponding pixels for one line.

In the frame inversion driving, the voltage applied to the common electrode simultaneously with the scanning of the _first scanning line G ₁
The signal voltage applied to the pixel electrode via the signal line is inverted. Therefore, as shown in FIG. 16B, all the pixels on the liquid crystal display panel 80 have the same polarity, and the polarities of all the pixels are inverted every one frame period.

Line inversion drive Line inversion drive is a method of inverting the polarity of each pixel for each scanning line and also inverting the polarity of each pixel for each frame period. FIG. 17A is a diagram showing an example of drive waveforms of a liquid crystal display device employing line inversion drive,
All pixels on the liquid crystal display panel are displayed in black (or white)
It is a case of making it.

According to the figure, the common voltage V is set for each scanning line.
com and the signal voltage D are inverted. In addition, the common voltage Vcom and the signal voltage D applied to each pixel on each scanning line are also inverted every frame period. That is, in the line inversion drive, the polarity is inverted spatiotemporally, the polarity is inverted spatially every scanning line, and the polarity is inverted temporally every frame period. Therefore, as shown in FIG. 17B, the polarity of each pixel on the liquid crystal display panel 80 is inverted every scanning line, and the polarity is also inverted every frame period.

Dot inversion drive Dot inversion drive means that, for pixels on a line (one scanning line), the polarity is inverted for each pixel and also for each scanning line, and also for each frame period. It is a method of reversing.

FIG. 18 (a) is a diagram showing an example of drive waveforms of a liquid crystal display device which employs dot inversion drive, and is for displaying all pixels on the liquid crystal display panel in black (or white). is there.

According to the figure, the common voltage Vcom is constant (DC). Here, the reason for using the DC voltage is that the common voltage Vcom is applied to all the pixels on the liquid crystal display panel, and it is difficult to sequentially invert each pixel. Therefore, in the dot inversion drive, only the voltage of the signal line is inverted pixel by pixel.

However, in the dot inversion drive, the signal voltage is set so that the polarity of the first pixel P ₁₁ in the first scanning line G1 and the polarity of the first pixel P _{21 in} the second scanning line G2 are opposite to each other. Adjust the polarity of. Further, the polarity of the signal voltage is controlled so that the polarity of each pixel is inverted every frame period. Therefore, as shown in FIG. 18B, the polarities of all the adjacent pixels on the liquid crystal display panel 80 are different, and the polarities of the pixels are inverted every frame period.

[0017]

As described above, each pixel in the active matrix liquid crystal display panel is provided with a switching element (thin film transistor), and a voltage is applied to the scanning line to turn on the switching element to turn on the pixel electrode and the common electrode. The voltage of the signal line is applied to the capacitance of the liquid crystal between (LCD capacitance), the scanning line becomes low potential, and the switching element becomes
It is configured so that the charge is retained in the LCD capacitor even after it is turned off. However, it is known that in a thin film transistor, there is a parasitic capacitance between the gate electrode and the drain electrode, and after the switching element is turned off, a small amount of charge held in the LCD capacitance flows from the pixel electrode through the parasitic capacitance. . Therefore, the potential of the pixel electrode decreases from the potential in the selected state with time.

Further, the potential of the pixel electrode is lowered by the field through voltage ΔV corresponding to the potential change of the scanning line due to the influence of the parasitic capacitance of the thin film transistor immediately after the scanning line becomes low potential and the thin film transistor is turned off. It is known. As a result, when the polarity of the pixel is one (potential of pixel electrode> potential of common electrode), OFF
The potential difference of the LCD capacitance is Δ
V, while the reversed polarity (pixel electrode potential <
Potential of the common electrode), the potential difference of the LCD capacitance increases by ΔV due to the potential decrease of the pixel electrode after being turned off. That is, the brightness of the pixel varies depending on the polarity of the pixel being inverted.

Therefore, when the polarities of all pixels are simultaneously inverted to the same polarity as in frame inversion driving, the brightness of the entire screen changes every frame period.
Flickering occurs. On the other hand, if the spatial period of inversion is shortened as in the dot inversion drive, the difference in luminance is canceled out throughout the entire screen, and the flicker becomes inconspicuous.

Therefore, in terms of display image quality, the image quality is improved as the spatial inversion period is shortened, and the display quality is improved in the order of frame inversion drive, line inversion drive, and dot inversion drive.

On the other hand, from the viewpoint of power consumption, since power is consumed especially for the inversion driving of the common voltage Vcom, the power consumption increases as the number of times of polarity inversion increases. In the dot inversion drive, the common voltage Vcom is constant as shown in FIG. However, since it is necessary to make the amplitude of the voltage D applied to the signal line larger than that of other inversion driving methods and to invert the polarity for each pixel, more power is required. Therefore, the power consumption increases in the order of frame inversion drive, line inversion drive, and dot inversion drive.

As described above, the request for improving the display image quality and the request for reducing the power consumption are contradictory conditions, and it has been difficult to simultaneously meet these two requests.

An object of the present invention is to provide a display driving device,
It is to realize a driving method with high display quality and low power consumption.

[0024]

In order to solve the above problems, the invention according to claim 1 is arranged in a matrix form in the vicinity of a plurality of scanning lines and a plurality of signal lines and respective intersections of the respective lines. In a display drive device for driving a display panel by applying a display signal voltage to each signal line of a display panel including a pixel having a pixel electrode and a common electrode facing each pixel electrode, one scanning line is provided. Scan control means for scanning all the scan lines of the display panel with a first scan period of interlacing and sequentially scanning, and a second scan period of sequentially scanning the scan lines skipped in the first scan period. A polarity reversing means for reversing the potentials of the pixel electrode and the common electrode of each pixel when switching from the first scanning period to the second scanning period; Characterized in that it comprises a potential difference correcting means for correcting the potential difference between pixel electrodes and the common electrode.

According to the invention of claim 1, the first
At the time of switching from the scanning period to the second scanning period, the polarity inverting means inverts the potentials of the pixel electrode and the common electrode, and so-called interlaced scanning is performed by the scanning control means. Therefore, the power consumption for driving the signal applied to the common electrode is about the same as that for the frame inversion driving, and the difference in brightness (brightness difference) between adjacent scanning lines (odd line and even line) is offset. To be done. Therefore, it is possible to suppress flicker and improve the display quality.

Here, due to the inversion of the potential of the common electrode by the polarity inversion means, in the first scanning period and the second scanning period,
The potential of the pixel electrode changes. As a result, when the potential difference applied between the pixel electrode and the common electrode is set to be constant, for example, the first scanning period and the second scanning period are caused by the leakage current based on the OFF resistance of the TFT that drives each pixel of the liquid crystal panel. Therefore, a difference occurs in the charge amount of the pixel. Therefore, the potential difference between the pixel electrode and the common electrode changes line by line, the display brightness changes, and when a single color is displayed, a striped pattern appears on the display screen and the display quality deteriorates. It is the potential difference control means that suppresses this phenomenon. That is, the potential difference control unit corrects the potential difference between the pixel electrode and the common electrode according to whether the current scanning period is the first scanning period or the second scanning period, and changes the potential difference of the charge amount of the pixel for each scanning line. By suppressing, the display quality can be improved. More specifically, for example, as in the invention described in claim 2, the potential difference control means is configured to control so as to reduce the difference in the amount of charge applied to the pixel for each scanning line. May be.

According to a third aspect of the present invention, the potential difference control means of the display driving apparatus according to the first aspect corrects the potential of the common electrode for each scanning period, so that the pixel electrode is corrected. And the potential difference between the common electrode may be corrected.

According to the third aspect of the invention, the potential difference between the pixel electrode and the common electrode can be changed only by changing the potential of the common electrode, so that the potential difference control means can be realized relatively easily. You can More specifically, for example, it may be configured as the invention according to claim 4.

That is, as in the invention described in claim 4, the potential difference control means of the display drive device according to claim 2 selects one of two types of voltages for setting the potential on the high voltage side of the common electrode.
It may be configured to include a common electrode voltage switching unit that selects one voltage from among two types of voltages that select the voltage of 1 and the voltage on the low voltage side of the common electrode.

According to the invention of claim 4, the switching circuit appropriately selects and switches from two types of high power source voltage and two types of low power source voltage to switch between the high voltage and the low voltage of the common electrode. Since the potential can be changed, it can be realized by a relatively simple circuit.

Further, as in the invention described in claim 5, the potential difference control means of the display driving device according to claim 1 corrects the gradation reference voltage range of the display signal voltage for each scanning period. By doing so, the potential difference between the pixel electrode and the common electrode may be corrected.

According to the fifth aspect of the invention, the potential difference between the pixel electrode and the common electrode can be changed only by changing the signal voltage, so that the potential difference control means can be realized relatively easily. it can. More specifically, for example, it may be configured as the invention according to claim 6.

That is, as in the sixth aspect of the invention, the potential difference control means of the display driving apparatus according to the fifth aspect is configured so that the two kinds of highest gradation reference voltages of the display signal voltage are provided for each scanning period. And a gradation reference voltage switching means for selecting one of the highest gradation reference voltage and one of the lowest gradation reference voltage, which is a reference for each gradation voltage of the signal voltage, from the two kinds of lowest gradation reference voltages. It may be configured as follows.

In general, the signal voltage is generated by dividing the potential difference between the highest gradation reference voltage and the lowest gradation reference voltage to generate the signal voltage of each gradation. According to the invention described in claim 6, the signal voltage can be changed only by switching between the highest gradation reference voltage and the lowest gradation reference voltage.

Further, as in the invention described in claim 7, the potential difference control means of the display driving device according to claim 1 converts the display signal for generating the display signal voltage in each of the scanning periods. By correcting the display signal voltage by
It may be configured to correct the potential difference between the pixel electrode and the common electrode.

According to the invention of claim 7, there is no need to change the highest gradation reference voltage or the lowest gradation reference voltage,
Since the signal voltage can be changed by correcting the display signal level itself, compared with the invention according to claim 6,
It is possible to control the potential difference more directly. More specifically, for example, it may be configured as the invention according to claim 8. That is, as in the invention described in claim 8, the potential difference control means of the display driving device according to claim 7 converts the display signal in the first scanning period to raise or lower the display signal level. And a second conversion unit that corrects the display signal in the second scanning period to correct the display signal level in another direction, either upward or downward. May be.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, first to fourth embodiments will be described with reference to the drawings. However, before that, the following two features that the display drive devices in the respective embodiments have in common will be described. (A) Interlaced scanning drive (b) Polarity reversal every 1 frame period

(A) Interlaced scan drive In the interlaced drive, regarding the scanning lines on the liquid crystal display panel, first, during the first field period (first scanning period), the odd lines of the scanning lines are sequentially scanned, and then the second field. Even lines are sequentially scanned during a period (second scanning period), and thus, all scanning lines are scanned during a two-field period (= 1 frame period) to display an image.

FIG. 1A is a diagram showing a configuration example of a liquid crystal display panel 20 according to the following embodiment. Each pixel P1, P2, ... Includes a scanning line G arranged in parallel with the horizontal direction.
_{1, G 2, G 3,} ... and G _2n, the signal lines D ₁ arranged parallel to the longitudinal direction, D _2, D _3, are formed respectively ... near the intersection of the D _m. In the embodiment described below, in the first field period (first field period), as shown in FIG. 1B, odd-numbered lines G ₁ , G ₃ , G ₅ , ... Are scanned,
In the next field period (second field period), FIG.
As shown in (c), the even lines G ₂ , G ₄ , G ₆ , ... Are scanned to display one image in two field periods.

(B) Inversion of polarity every one frame period In the embodiment described below, the polarity (electric field) between the electrodes sandwiching the liquid crystal of each pixel is inverted every two field periods (corresponding to one frame period). Let However, the reversal timing is when the scanning is completed for the odd lines and then switched to the scanning for the even lines. That is, the polarity is inverted at a timing shifted by one field period from the start of displaying one image (start of one frame period).

Next, the polarity reversal timing in the following embodiments will be described. FIG. 2 is a schematic diagram illustrating the configuration of each pixel formed on the liquid crystal display panel 20. According to the figure, each pixel includes a thin film transistor (TFT) 30, an LCD capacitor (capacitor) 31,
It mainly includes a parasitic capacitance (capacitor) 32. Note that the parasitic capacitance 32 is not provided as an independent capacitor, but due to the structure of the TFT 30, the gate electrode 30g
And a capacitor component parasitically formed between the drain electrode 30d and the drain electrode 30d.

The source electrode 30s of the TFT 30 is a signal line D
, The gate electrode 30g is connected to the scanning line G,
Further, the drain electrode 30d is the pixel electrode 3 of the LCD capacitor 31.
1a is connected. The common electrode 31b of the LCD capacitor 31 is connected to the common line 40.

In the embodiment described below, the LCD capacitor 3
The direction of the electric field formed between one pixel electrode 31a and the common electrode 31b is inverted every one frame period.
Specifically, the voltage applied to the pixel electrode 31a and the voltage applied to the common electrode 31b are inverted every two field periods at a timing shifted by one field period from the start point of one frame period.

FIG. 3 is a diagram showing an example of drive waveforms when interlaced scanning drive is performed. In the figure, the waveform corresponding to Vcom shows the time change of the potential (common voltage) of the common electrode 31b, and the waveform corresponding to D shows the time change of the potential (signal voltage) of the signal line, G ₁ , waveform corresponding to the G ₂ is, respectively showing temporal changes of the potential of the scanning line G _1, G _2. In this interlaced scanning drive, as described above, the odd lines of the scanning lines are sequentially scanned in the first field, and the even lines of the scanning lines are sequentially scanned in the subsequent second field, but the description is simplified. For simplicity, only the scanning lines G ₁ and G ₂ are shown in FIG. P ₁ indicates a pixel formed near the intersection of the signal line D ₁ and the scanning line G ₁ , P ₂ indicates a pixel formed near the intersection of the signal line D ₁ and the scanning line G ₂ , and P ₁ , P ₂ correspond to the potential Vp of the pixel electrode 31a of the pixels P ₁ and P ₂ and the common electrode 3 respectively.
The potential Vcom of 1b is shown. Pdif ₁ and Pdif ₂ are pixel P ₁ ,
The potential difference between the pixel electrode 31a and the common electrode 31b at P ₂ , that is, the potential difference VLC between the electrodes of the LCD capacitor 31.
D is shown respectively.

The gate driver for controlling the scanning lines G _{1 to} G _2n applies a high potential pulse of a predetermined width to each scanning line every frame period. However, odd-numbered lines (odd-numbered scanning lines) are sequentially scanned in the first field period, and even-numbered lines (even-numbered scanning lines) are sequentially scanned in the next field period. Specifically, the scanning lines G ₁ , G ₃ , G ₅ , ... Are scanned in the first field, and the scanning lines G ₂ , G ₄ , G ₆ , ... Are scanned in the next field.

According to the above driving method, the liquid crystal display panel 2
On 0, the polarity of the potential difference applied to the pixel of the adjacent scanning line is inverted for a half period of one frame period (corresponding to one field period). Therefore, the image quality is almost equal to that of the conventional line inversion drive. Becomes Furthermore, the common voltage V
Since the polarity inversion frequency of com is every 1 frame period,
The power consumption is equivalent to that of the conventional frame inversion drive.

However, if an image is displayed simply by using the drive waveforms shown in FIG.
The charge held in the D capacitor is reduced by the leakage,
It was found that the potential difference VLCD between the polarities of the capacitor 31 was smaller than that of the pixels on the even lines. Therefore, for example, when the liquid crystal is in the normally white mode, the brightness of the pixels on the odd lines becomes higher than the brightness of the pixels on the even lines,
When full-screen monochromatic display is performed, bright and dark striped patterns occur on the screen.

The above problem will be described below with reference to FIGS. 4 and 5. First, the scanning line G ₁ will be described.
FIG. 4 is a schematic diagram for explaining a change in the potential of the LCD capacitor 31 of the pixel P ₁ at each of the points ( ₁ ) to (3) shown in the drive waveform diagram of FIG. However, in FIG. 4, the high potential of the common voltage Vcom is 4.5 V, the low potential is −1.5 V, and the signal voltage D
High potential is 4V and low potential is 1V.

FIG. 4A is a diagram corresponding to the time points in the drive waveform diagram of FIG. When the scanning line G ₁ has a high potential, the TFT 30 is turned on, and the potential of the signal line D ₁ is TFT.
The LCD capacitor 31 of the pixel P ₁ is charged via the. When the common voltage Vcom is in the low potential state (-1.5V) and the signal voltage is in the high potential state (4V), the potential of the common electrode 31b is-.
The voltage becomes 1.5V, and the potential Vp of the pixel electrode 31a becomes 4V, which is almost the same as the potential of the signal line D ₁ . Therefore, the potential difference of the LCD capacitor 31 of the pixel P ₁ becomes VLCD = 5.5V.

Next, the scanning line G ₁ becomes low potential, and TF
When T30 is turned ON (time point), the potential Vp of the pixel electrode 31a is reduced by the field through voltage ΔV due to the influence of the parasitic capacitance 32 (FIG. 4B). Therefore, the potential difference of the LCD capacitor 31 is VLCD = (5.5−ΔV) V.

After the TFT 30 is turned off (time point), the potential difference VLCD of the LCD capacitor 31 is almost maintained.
At this time, there is a slight leak current through the OFF resistance of the TFT 30, but since it is small, the potential difference VLCD is maintained substantially constant.

Next, since the polarity inversion is performed for each frame period of the above (b), when switching from the scanning period of the odd line to the scanning period of the even line, the common voltage Vcom
And the polarity of the signal voltage D is inverted. That is, the common voltage Vco
Switching m from low potential (-1.5V) to high potential (4.5V), signal voltage D from high potential (here 4V) to low potential (here 1V)
Switch to (time point). At this time, since the potential difference VLCD of the LCD capacitor 31 is held, the potential Vp of the pixel electrode 31a is
Will be increased by the increase (6V) of the potential of the common electrode 31b. At this time, as the potential of each electrode of the LCD capacitor 31 rises, the electric charges charged in the pixel electrode 31a leak a little through the parasitic capacitance 32, so that the pixel electrode 31a
The potential Vp of V is decreased by a minute voltage Δα (Fig. 4).
(D)). From the above, the potential Vp of the pixel electrode 31a is
Becomes (10-ΔV-Δα) V, the potential of the common electrode 31b becomes 4.5V, and the potential difference of the LCD capacitor 31 becomes VLCD =
(5.5-ΔV-Δα) V.

Now, when the polarities of the signal voltage D and the common voltage Vcom are inverted, the potential Vp of the pixel electrode 31a and the signal line D ₁
The potential difference with the potential of becomes large. Specifically, the signal line D
₁ potential is approximately 1V, the potential Vp of the pixel electrode 31a (10-
ΔV-Δα) V. Therefore, the leak current from the pixel electrode 31a to the signal line D ₁ via the OFF resistance of the TFT 30 becomes large (FIG. 4 (e)), and the potential difference V of the LCD capacitor 31 is increased.
LCD decreases with time (time point).

Thus, the potential difference VLCD of the LCD capacitor 31 is
Is decreased, the brightness of the pixel P ₁ is changed, and the brightness is increased. That is, the brightness of the pixels on the odd lines changes during the scanning period of the even lines.

Next, the scanning line G ₂ will be described. The timing at which the pixel P ₂ is in the selected state is after the polarities of the common voltage Vcom and the signal voltage D are inverted, as shown in the drive waveform of FIG. Therefore, unlike the case of the pixel P _1, since a small potential difference variation between the potential Vp and the potential of the signal line D ₁ of the pixel electrode 31a, leakage to the signal line D ₁ is small.

FIG. 5 is a schematic diagram for explaining changes in the potential of the LCD capacitor 31 of the pixel P ₂ at the respective points of to shown in the driving waveform diagram of FIG. Here, as in FIG. 4, the high potential of the common voltage Vcom is 4.5V, the low potential is -1.5V, the high potential of the signal voltage D is 4V, and the low potential is 1V.

Now, when the scanning line G ₂ has a high potential (time point), the TFT 30 is turned on, and the potential of the signal line D ₁ is charged in the LCD capacitor 31 of the pixel P ₂ via the TFT. At this time, if the common voltage Vcom is high potential (4.5V) and the signal voltage D is low potential (1V), the potential of the common electrode 31b is
The voltage becomes 4.5V, and the potential Vp of the pixel electrode 31a becomes 1V which is almost equal to the potential of the signal line D ₁ (FIG. 5A). Therefore, LCD
The potential difference VLCD of the capacitor 31 is -3.5V.

Next, when the scanning line G ₂ is switched from the high potential to the low potential (time point), the potential Vp of the pixel electrode 31a is decreased by ΔV due to the influence of the parasitic capacitance 32 (FIG. 5 (b)). . Therefore, the potential difference of the LCD capacitor 31 is VLCD.
= (-3.5-ΔV) V.

The scanning line G ₂ has a low potential, and the TFT 3
After 0 is turned off (time point), since the leak current through the TFT 30 is small, the potential difference VLCD is maintained substantially constant.

[0060] In the pixel P _2, different from the case of the pixel P _1, polarity during the period up to the scanning line G ₂ next becomes a high potential (selection state) is not inverted. Therefore, the LCD capacitance 31 of the pixel P ₂
Maintains the applied potential difference when the TFT 30 is ON. Therefore, many pixels on even-numbered lines can maintain almost constant brightness. From the above, if the interlaced scanning drive and the polarity reversal for each frame period are simply performed, a bright and dark striped pattern is generated between the odd lines and the even lines, which causes flicker.

Each embodiment will be described in detail below. In each of the embodiments, the potential difference applied to the pixel electrode 31a and the common electrode 31b of each pixel is adjusted for each scanning period of the odd line and the even line to suppress the occurrence of bright and dark striped patterns.

[First Embodiment] Hereinafter, FIGS. 6 to 8 will be described.
The first embodiment will be described using. The first embodiment is characterized in that the amplitude of the common voltage Vcom is changed between the odd-numbered line scanning period and the even-numbered line scanning period.

First, the structure will be described. Figure 6
It is a figure which shows an example of a circuit structure of the display drive device 1 in this 1st Embodiment. According to the figure, the display drive device 1
Is an RGB decoder 10, an inverting amplifier 11, a memory 12, a controller 13, a source driver 14,
A gate driver 15, a common signal generation circuit 16, and a liquid crystal display panel 20 are mainly provided.

The RGB decoder 10 receives the horizontal synchronizing signal (H) from the analog video signals input from the outside,
The vertical synchronizing signal (V) is taken out and output to the controller 13.

Further, the RGB decoder 10 converts the analog video signal into a digital video signal and, in the case of a color video signal, R (red), G (green), B (blue).
Are separated into three signals. Further, the separated three types of RGB signals are converted into a data format that can be driven by the source driver 14. Specifically, a video signal for one line is read from each of the RGB digital video signals at a timing based on the extracted horizontal sync signal and vertical sync signal, and a gradation signal corresponding to the video signal is generated. . Then, the generated RGB gradation signals are supplied to the inverting amplifier 11
Output to.

The inverting amplifier 11 is responsive to the inverting control signal input from the controller 13, and the RGB decoder 1
The RGB gradation signals input from 0 are inverted to generate an inverted RGB signal, which is output to the memory 12.

The memory 12 is composed of a RAM and temporarily stores each gradation signal for one frame (one screen) input from the inverting amplifier 11. When writing a gradation signal in the memory 12, the controller 13 described later writes display data in units of one line (one scanning line) while designating an address. On the contrary, when reading the written gradation signal, each gradation signal of a desired line is output in a desired transfer order by designating an address. Therefore, when interlaced scanning is performed by the gate driver 15, an image can be properly displayed by designating addresses in the interlaced scanning order.

The controller 13 controls the entire display driving device 1. For example, the horizontal control signal and the vertical control signal for driving the liquid crystal of each pixel of the liquid crystal display panel 20 are generated based on the horizontal synchronization signal and the vertical synchronization signal input from the RGB decoder 10. The generated horizontal control signal is output to the source driver 14, and the vertical control signal is output to the gate driver 15.

The horizontal control signal is an STI signal for timing control for sampling the gradation signal by the source driver 14, a CKN signal for timing control for outputting a signal voltage based on the latched gradation signal to each signal line, and the source driver. A basic clock signal for driving 14 is included.

The vertical control signal is a CDB signal for determining the scanning start timing of the scanning lines and the selection period (ON state period) of each scanning line, and the scanning lines scanned by the gate driver 15 are sequentially shifted every other scanning line. The CNB signal for performing the operation is included.

Further, the controller 13 generates the FRP signal and the ADJ signal based on the horizontal synchronizing signal and the vertical synchronizing signal and outputs them to the common signal generating circuit 16. FRP
The signal is a signal used when forming a basic waveform of the common voltage Vcom, and is a signal that is inverted (H / L) every two frame periods with a period of two frames. The inversion timing is when the odd line scanning period is switched to the even line scanning period. The ADJ signal is a signal for changing the amplitude of the basic waveform of the common voltage Vcom for each scanning period (that is, for each field), and has a period of two frame periods and is inverted (H / H) for each frame period. L) signal. The ADJ signal is shifted by +1/4 cycle, that is, one field period as compared with the FRP signal, and is inverted when switching from the even line scanning period to the odd line scanning period.

Further, the controller 13 generates an inversion control signal for inverting each gradation signal of RGB based on the horizontal synchronization signal and the vertical synchronization signal to generate the inversion amplifier 1.
Output to 1. Further, a memory control signal for instructing the write / read timing of display data to the memory 12 and an address control signal for controlling the write / read address of the memory 12 are generated and output to the memory 12.

As shown in FIG. 1A, the liquid crystal display panel 20 has a plurality of scanning lines and a plurality of signal lines arranged orthogonally to each other, and each pixel is provided in the vicinity of the intersection of each scanning line and each signal line. Are formed. The configuration of each pixel is as described with reference to FIG. Each scan line is a gate driver 1
5 and each signal line is connected to the source driver 14.

The gate driver 15 is the controller 13
A scanning voltage is generated based on a vertical control signal input from the liquid crystal display panel 20, and the scanning voltage is sequentially applied to the scanning lines G _{1 to} G _2n of the liquid crystal display panel 20. In this case, as described above, one scan line
Every other scan is interlaced and the odd lines are sequentially scanned, and then the even lines are sequentially scanned.

The source driver 14 stores a data latch circuit (not shown) for holding the gradation signal input from the memory 12 in association with each signal line, and a signal voltage based on the latched gradation signal. It has a driver circuit (not shown) for generating and applying it to each signal line, and applies a signal voltage to each signal line based on a horizontal control signal input from the controller 13.

The common signal generation circuit 16 is the controller 1
The common voltage Vcom is generated on the basis of the FRP signal and the ADJ signal input from 3, and is supplied to the common electrode 31b of each pixel of the liquid crystal display panel 20. Specifically, the basic waveform of the common voltage Vcom is formed based on the FRP signal, and AD
The amplitude of the common voltage Vcom is changed based on the J signal.
More precisely, the common voltage Vcom is formed so that the amplitude of the odd line scanning period is larger than that of the even line scanning period.

Next, FIG. 7 is a diagram for explaining the configuration of the common signal generation circuit 16 in the first embodiment. As shown in the figure, in the first embodiment, the common voltage Vcom is generated using the amplifier (operational amplifier) 50. The ADJ signal is input to the inverting input terminal 51 of the amplifier 50 through the resistor R1 and the FRP signal is input through the resistor R2.
A signal is input. A resistor R3 is connected between the minus inverting input terminal 51 and the output terminal 53. The power supply voltage V _DC (DC) is applied to the non-inverting input terminal 52 of the amplifier 50.
Is entered. Here, the power supply voltage V _DC is the common voltage V co
It becomes the standard potential of m.

Now, according to the amplifier 50 shown in FIG. 7, the output Vcom becomes Vcom =-(R3 / R1) V _ADJ- (R3 / R2) V _FRP + V _DC (1). That is, with V _DC as the reference potential (center voltage), F
A basic waveform of the common voltage Vcom is formed according to the cycle and inversion timing of the RP signal V _FRP , and the basic waveform A
The waveforms of the DJ signal V _ADJ will be added.

In the following, for convenience, (R3 / R1) V _ADJ
= Ω (amplitude based on ADJ signal), and (R3 / R2) V
Let _FRP = Ω (amplitude based on FRP signal).

The operation of the common signal generation circuit 16 will be described below with reference to the drive waveforms shown in FIG. As described above, the FRP signal has a period of two frame periods and is inverted every one frame period.

Similarly, the ADJ signal has a period of two frame periods and is inverted every frame period, and its polarity is inverted by 1/4 period (one field period) later than the FRP signal.

Now, when both the ADJ signal and the FRP signal are at high potential (H) (FIG. 8; period a), according to the amplifier 50 (equation (1)) shown in FIG. 7, the FRP signal V _FRP The amplitude of the ADJ signal V _ADJ is added and inverted to the amplitude of the common voltage Vcom at the lowest potential; V _LL = (V _DC −Ω
−ω).

Then, when the FRP signal switches from the high potential (H) to the low potential (L) (period b), the common voltage Vcom switches from the low potential state (L) to the high potential state (H). . But,
In period b, the ADJ signal is at high potential (H), so FR
The amplitude ω based on the ADJ signal is subtracted from the amplitude Ω based on the P signal, and the common voltage Vcom is a quasi-high potential; V _HL = (V
_DC + Ω-ω).

Both FRP signal and ADJ signal are low potential (L)
Then (period c), the amplitude ω of the FRP signal is added with the amplitude ω of the ADJ signal and inverted, and the common voltage Vco
m is the highest potential; V _HH = (V _DC + Ω + ω).

Then, when the FRP signal switches from the low potential (L) to the high potential (H) (period d), the potential of the common voltage Vcom changes from the high potential state (H) to the low potential state (L). Switch. However, in the period d, since the ADJ signal has the low potential (L), the amplitude ω of the ADJ signal is subtracted from the amplitude Ω of the FRP signal, and the common voltage Vcom has a quasi-low potential; _VLH = (V _DC −
Ω + ω).

As described above, the common voltage Vcom is ADJ
V _LL , V _HL , V _HH , based on the signal and the FRP signal.
It changes in the order of V _LH , V _LL , ....
Note that the relationship of each potential is V _HH > V _HL > V _LH > V _LL .

That is, the common voltage Vcom is the same as the ADJ signal and F
When the polarities of the RP signals match, the amplitude increases (V _HH o
r V _LL ), the amplitude decreases (V _HL or V _HL ) when the ADJ signal and the FRP signal have opposite polarities.

Next, the operation of the display drive device 1 will be described using the drive waveforms shown in FIG. 8, focusing on the characteristic parts of the first embodiment. In FIG. 8, V
The waveform corresponding to com indicates the time change of the common voltage generated by the common signal generation circuit 16. The waveform corresponding to D indicates the time change of the signal voltage applied by the source driver 14 to each of the signal lines D _{1 to} D _2n on the liquid crystal display panel 20. Here, it is assumed that all pixels on the liquid crystal display panel 20 are displayed in black (or white) and the potential V
Inverted with amplitude φ based on _DC (high potential: V _DH
= V _DC + φ, low potential: V _DL = V _DC −φ). For the waveforms corresponding to G _{1 to} G _2n , the gate driver 15 scans each scanning line G ₁ to G ₂
The time change of the voltage applied to G _2n is shown.

P ₁ is a pixel corresponding to the intersection of the signal line D ₁ and the scanning line G ₁ on the liquid crystal display panel 20 shown in FIG. 1, and P ₂ is the pixel line of the signal line D ₁ and the scanning line G ₂ . Pixels located near the intersection. The waveforms corresponding to P ₁ and P ₂ in FIG. 8 are the potential V of the pixel electrode 31a of each pixel P ₁ and P ₂ , respectively.
p and the time change of the potential of the common electrode 31b are shown. Further, Pdif ₁ indicates the time change of the potential difference between the pixel electrode 31a and the common electrode 31b of the pixel P ₁ , and Pdif ₂ is
The time change of the potential difference between the pixel electrode 31a and the common electrode 31b of the pixel P ₂ is shown.

Now, the controller 13 generates various signals based on the horizontal synchronizing signal and the vertical synchronizing signal input from the RGB decoder 10. At that time, the ADJ signal and the F signal are generated.
The memory control signal, the horizontal control signal, and the vertical control signal are arranged so that the odd line scanning period corresponds to the period in which the polarities of the RP signal match and the even line scanning period corresponds to the period in which the polarities of the ADJ signal and the FRP signal are opposite to each other. And so on. Also,
The inversion control signal is generated and output to the inverting amplifier 11 so that the period of the polarity inversion of the signal voltage matches the period of the FRP signal.

In the odd line scanning period, the gate driver 15 sequentially skips even lines to generate G ₁ , G ₃ ,
Scanning lines are scanned in the order of G ₅ , ..., G _2n-1 , and odd-numbered lines are sequentially skipped during the even-line scanning period,
The scanning lines are scanned in the order of G ₂ , G ₄ , G ₆ , ..., G _2n .

According to FIG. 8, the common voltage Vcom is the lowest potential V _LL and the signal voltage D is the signal voltage D in the period a when the ADJ signal and the FRP signal are both in the high potential state and the common voltage Vcom is the lowest potential V _LL. It has a high potential V _DH .

Now, at this time, when the scanning line G ₁ has a high voltage and the TFT 30 is turned on (time point), the pixel electrode 31
The potential Vp of a is substantially equal to the potential V _DH of the signal line D ₁ . On the other hand, since the value of the common voltage Vcom is the lowest potential V _LL , the potential of the common electrode 31b is V _LL . Therefore, the pixel P
Potential difference VLCD between ₁ pixel electrode 31a and common electrode 31b
Becomes (V _DH −V _LL ).

Next, in the period a, the scanning line G₁Is low
When the potential is turned on and the TFT 30 is turned off (time point),
Due to the influence of the raw capacitance 32, the potential Vp of the pixel electrode 31a is
ΔV lowers (V_DH-ΔV). Therefore, the pixel P₁LCD content
The potential difference of quantity 31 is VLCD = (V _DH-V_LL-ΔV)
Is kept almost constant.

Next, the odd line scanning period is switched to the even line scanning period (period b), and at the same time, the polarities of the common voltage Vcom and the signal voltage D are inverted. At this time,
The ADJ signal and the FRP signal have opposite polarities, and the common voltage Vco
The value of m becomes the quasi-high potential V _HL . Further, the potential on the signal line becomes the low potential V _DL .

The potential Vp of the pixel electrode 31a of the pixel P ₁ at the time of switching to the even line scanning period (time point)
, The electric charge charged with the reversal of the polarity slightly leaks through the parasitic capacitance 32, so that the potential decreases by Δα. Therefore,
The potential Vp of the pixel electrode 31a of the pixel P ₁ is (V _DH + V _HL −
V _LL −ΔV−Δα). Further, the potential difference of the LCD capacitor 31 of the pixel P ₁ is VLCD = (V _DH −V _LL −ΔV−Δ
α).

[0097] Incidentally, the polarity of the signal lines D ₁ is inverted, and the potential Vp of the pixel electrode 31a of the pixel P _1, the signal line D ₁
Since the potential difference from the upper potential V _DL becomes large, the charges charged in the pixel electrode 31a of the pixel P ₁ leak to the signal line through the OFF resistance of the TFT 30. Therefore, the potential Vp of the pixel electrode 31a of the pixel P ₁ drops, and when this is Δβ,
During the even line scanning period (period), the LCD capacitance 31
Potential difference of VLCD = (V _DH −V _LL −ΔV−Δα−Δ
β).

On the other hand, in the pixel P ₂ , when the scanning line G ₂ has a high voltage and the TFT 30 is turned on (time point), the signal line D ₁
The voltage V _DL is applied to the pixel electrode 31a via the. The potential Vp of the pixel electrode 31a at this time is the potential V _{DL of the} signal line.
Is almost the same as On the other hand, the potential of the common electrode 31b is V _HL
Therefore, the potential difference VLCD of the LCD capacitor 31 is (V _{D L}
-V _HL ).

After that, the scanning line G ₂ has a high voltage and TF
When T30 is turned off, the potential Vp of the pixel electrode 31a decreases by ΔV due to the influence of the parasitic capacitance 32.
The potential difference of the capacitor 31 is VLCD = (V _DL −V _HL −ΔV).

Now, the potential difference between the LCD capacitors 31 of the pixels P ₁ and P _{2 in} the even line scanning period (period b) is compared. The potential difference of the pixel P ₁ is VLCD = (V _DH −V _LL −Δ
V-Δα-Δβ), and the potential difference of the pixel P2 is VLCD.
= (V _DL −V _HL −ΔV). Where (V _DH = V _DC
+ Φ), (V _DL = V _DC −φ), (V _LL = V _DC −Ω−
ω), (V _HL = V _DC + Ω−ω), comparing the absolute value of each potential difference, the potential difference of the LCD capacitor 31 of the pixel P ₁ is equal to (2ω−2ΔV−Δα−Δβ). Pixel P
_It is larger than the potential difference of the _second LCD capacitor 31.

The above results show that the common voltage Vcom and ADJ
When the signal and the FRP signal start in opposite phases (period c,
The same holds true for d).

Therefore, ω is set based on ΔV (field through voltage), Δα (voltage decrease due to leakage to the parasitic capacitance) and Δβ (voltage decrease due to leakage through the TFT), and By setting to the value shown in (2), the amount of charge charged in the LCD capacitor 31 of the pixel P ₁ is corrected, and can be made substantially equal to the amount of charge of the LCD capacitor 31 of the pixel P ₂ . ω = (2ΔV + Δα + Δβ) / 2 (2) As a result, the striped pattern for each line is eliminated, and flicker can be prevented.

As described above, in the first embodiment,
Scanning is divided into odd lines and even lines, and interlaced scanning is performed for each. At that time, by making the amplitude of the common voltage Vcom in the scanning period of the odd lines larger than the amplitude of the common voltage Vcom in the scanning periods of the even lines, it is possible to eliminate the bright and dark striped pattern for each line caused by the influence of the leak current. It will be possible.

[Second Embodiment] The second embodiment will be described below with reference to FIG. In the first embodiment, the common signal generation circuit 16 has been described as using the amplifier (operational amplifier) 50 shown in FIG. 7 when generating the common voltage Vcom.

In the second embodiment, the common voltage Vcom
The output of is not generated by using an amplifier, but one power supply voltage is appropriately selected from four power supply voltages by a logic circuit, and a required waveform is formed. The required waveform of the common voltage Vcom is the same as the waveform described in the first embodiment (see FIG. 8).

That is, the second embodiment is almost the same as the display drive device 1 described in the first embodiment,
Only the configuration of the common signal generation circuit 16 is different. Therefore, hereinafter, the configuration and operation of the common signal generation circuit 16 will be mainly described, the description of the functions and configurations equivalent to those of the first embodiment will be omitted, and the same reference numerals and names will be used.

FIG. 9 is a diagram for explaining the circuit configuration of the common signal generation circuit 16 in the second embodiment. That is, the common signal generation circuit 16 includes the first power supply voltage V _HH , the second power supply voltage V _HL , the third power supply voltage V _LH , and the fourth power supply voltage V _LL.
A power supply for generating four kinds of voltage, the switch S ₁ is connected to the first power supply voltage V _HH, a switch S ₂ is connected to the second power supply voltage V _HL, connected to the third power supply voltage V _LH a switch S ₃ that, with the switch S ₄ is connected to the fourth power supply voltage V _LL, mainly includes an inverter 60, a. Each of the switches S1 to S4 is composed of, for example, a transistor.

The first power supply voltage V _HH is connected to the first terminal 61 of the inverter 60 via the switch S ₁ ,
The power supply voltage V _HL is connected to the first terminal 61 of the inverter 60 via the switch S ₂ . On the other hand, the third power supply voltage V _LH is connected to the second terminal 62 of the inverter 60 via the switch S ₃ , and the fourth power supply voltage V _LL is connected to the second terminal 62 of the inverter 60 via the switch S _4. . Further, the FRP signal is input to the third terminal 63 of the inverter 60.

Switch S₁~ S_FourIs based on ADJ signal
ON / OFF is determined. Switch S ₁, S₃Is ADJ
Signal is low potential (L), it is ON, and high potential (H) is OF
Become F. Switch S₂, S_FourThe ADJ signal is high potential (H)
It turns on when is and turns off when the potential is low (L).

In the inverter 60, the FRP signal has a low potential.
When the potential is (L), the potential of the first terminal 61 is output to the output terminal 64, and when the potential is high (H), the potential of the second terminal 62 is output to the output terminal 64. The output from the output terminal 64 is supplied to the common electrode 31b of each pixel of the liquid crystal display panel 20.

Now, when both the ADJ signal and the FRP signal are at the high potential (H) (FIG. 8; period a), the switches S ₂ and S _{4 are}
Is turned on, the second power supply voltage V _HL is input to the first terminal 61 of the inverter 60, and the fourth power supply voltage V _LL is input to the second terminal 62.
Is entered. The inverter 60 has a high potential for the FRP signal.
Since it is (H), the input of the second terminal 62 is output to the output terminal 64. Therefore, in this case, the fourth power supply voltage V _LL is output as Vcom.

When the ADJ signal is at high potential (H) and the FRP signal is at low potential (L) (FIG. 8; period b), the switches S ₂ , S
₄ is turned on, and the second terminal is connected to the first terminal 61 of the inverter 60.
The power supply voltage V _HL and the fourth power supply voltage V _LL are input to the second terminal 62. The FRP signal of the inverter 60 has a low potential
Since it is (L), the input of the first terminal 61 is output to the output terminal 64. Therefore, the second power supply voltage V _HL is output as Vcom.

Both ADJ and FRP signals are low voltage (L)
(FIG. 8; period c), the switches S ₁ and S ₃ are turned on, the first power supply voltage V _HH is applied to the first terminal 61 of the inverter 60, and the third power supply voltage is applied to the second terminal 62. V _LH is input. The inverter 60 outputs the input of the first terminal 61 to the output terminal 64 because the FRP signal has a low potential (L).
Therefore, the first power supply voltage V _HH is output as Vcom.

When the ADJ signal is low potential (L) and the FRP signal is high potential (H) (FIG. 8; period d), the switches S ₁ and S
₃ is turned on, and the first terminal 61 of the inverter 60 has the first
The power supply voltage V _HH and the third power supply voltage V _LH are input to the second terminal 62. In the inverter 60, the FRP signal has a high potential (H).
Therefore, the input of the second terminal 62 is output to the output terminal 64. Therefore, the third power supply voltage V _LH is output as Vcom.

As described above, according to the second embodiment, the waveform of the common voltage Vcom required by selecting the potential from the four power supply voltages at any time based on the ADJ signal and the FRP signal. To form.

As described above, in the second embodiment,
Vcom by controlling the power supply voltage changeover switch
Is generating the required waveforms for. Therefore, this circuit can be realized by incorporating it into a driver or a power supply IC, and it is possible to reduce the number of parts and drive the liquid crystal with low power.

[Third Embodiment] The third embodiment will be described below with reference to FIGS. 10 to 12. In the first embodiment, the common voltage Vcom is switched to different amplitudes in the odd line scanning period and the even line scanning period, thereby making the bright and dark striped pattern of each line caused by the leak current inconspicuous. did.

On the other hand, in the third embodiment, the amplitude of the common voltage Vcom is kept constant, and the output range of the signal voltage (gradation voltage) is switched according to each scanning period. That is, in the first embodiment, the potential difference VLC between the electrodes of the LCD capacitor 31 is changed by changing the voltage applied to the common electrode 31b.
Although D is changed for each scanning period, in the third embodiment, the potential difference VLCD of the LCD capacitor 31 is changed by changing the voltage applied to the pixel electrode 31a.

The third embodiment will be described in detail below, but the explanation of the same functions and configurations as those of the first embodiment will be omitted, and the same names and reference numerals will be used. The difference will be mainly described.

First, the structure of the display driving apparatus 100 according to the third embodiment will be described. FIG. 10 is a diagram showing an example of a circuit configuration of the display drive device 100 according to the third embodiment. According to the figure, the display driving device 100 according to the third embodiment is different from the display driving device 1 according to the first embodiment described with reference to FIG. 6 in that the display driving device 100 according to the third embodiment includes the gradation voltage selection circuit 70. different.

The controller 13 'in the third embodiment outputs to the inverting amplifier 11 on the basis of the horizontal synchronizing signal and the vertical synchronizing signal input from the RGB decoder 10 as in the first embodiment. It generates an inversion control signal, a memory control signal and an address control signal to be output to the memory 12, a horizontal control signal to be output to the source driver 14 ', and a vertical control signal to be output to the gate driver 15, and also generates an ADJ signal and an FRP signal. . ADJ
The waveforms of the signal and the FRP signal are the same as the waveforms described in the first embodiment.

However, in the third embodiment, the ADJ
The signal is used as a signal for changing the output range of the signal voltage, and the controller 13 ′ outputs the generated ADJ signal to the gradation voltage selection circuit 70. Further, only the FRP signal is output to the common signal generation circuit 16 '.

The common signal generating circuit 16 'receives the common voltage V based on the FRP signal input from the controller 13'.
com is generated and supplied to the common electrode 31b of each pixel on the liquid crystal display panel 20. However, the common voltage Vcom in the third embodiment has a polarity opposite to the polarity of the FRP signal, and the amplitude is always constant. For example, a signal obtained by inverting and amplifying the FRP signal using a differential amplifier or the like is output to the liquid crystal display panel 20 as the common voltage Vcom.

In the following, the common voltage Vcom is a signal oscillating with an amplitude Ω (amplitude based on the FRP signal) with the potential V _DC as a reference potential (center voltage) (Vcom = V _DC ± Ω).

The gradation voltage selection circuit 70 is supplied with four levels of voltage (VRH1, VRH2, VRL1, VRL2), and either one of VRH1 and VRH2, depending on the ADJ signal input from the controller 13 ', VRL1,
One of the voltages VRL2 is selected to generate a VRH signal and a VRL signal. And the generated VR
The H signal and the VRL signal are applied to the source driver 14 'as a reference voltage (grayscale reference voltage) for setting the grayscale voltage.

FIG. 11 shows the voltage levels of the VRH signal and the VRL signal. The VRH signal changes the high potential state to VRH1,
This is a signal that sets the low potential state to VRH2. For convenience, VR
Signal of H signal, the amplitude λ centered voltage V _RHC (= V
_RHC ± λ, VRH1 = V _RHC + λ, VRH2 = V _RHC −
λ). Further, the center potential V _RHC is set to a potential Λ higher than the oscillation reference potential V _DC of the common voltage Vcom (V _RHC = V
_DC + Λ).

The VRL signal is a signal that sets the high potential state to VRL1 and the low potential state to VRL2. For convenience, VRL
The signal is a signal of amplitude λ with V _RLC as the center voltage (= V _{RLC
± λ, VRL1 = V RLC +} λ, VRL2 = V RLC -λ) to. In addition, the potential V _RLC is a potential Λ lower than the oscillation reference potential V _DC of the common voltage Vcom (V _RLC = V _DC -Λ).

The source driver 14 'determines the output range of the signal voltage by using the VRH signal and the VRL signal input from the grayscale voltage selection circuit 70 as the grayscale reference voltages, and determines the output range (potential difference) by, for example, a plurality of output ranges. By dividing the voltage with a resistor, a voltage for each gradation is generated. And the memory 12
The voltage corresponding to the gradation signal input from is determined as the signal voltage D output to each signal line.

As shown in FIG. 11, for example, when the VRH signal and the VRL signal are in the high potential state, the output range is VR.
As L1 to VRH1, a potential corresponding to the gradation signal is uniquely determined from among these and is output to the signal line as a signal voltage. On the other hand, when the VRH signal and the VRL signal are in the low potential state)), the output range is set to VRL2 to VRH2, and the potential corresponding to the gradation signal is uniquely determined from this and output to the signal line.

The operation of the display driving apparatus 100 according to the third embodiment will be described below with reference to FIG. Figure 1
2 is the display drive device 100 according to the third embodiment.
It is a figure which shows an example of the drive waveform of. In the figure, all pixels of the liquid crystal display panel 20 are supposed to display black (or white).

Now, in the figure, the ADJ signal, FRP
During the period a in which both signals are in the high potential state, since the FRP signal is in the high potential, the common voltage Vcom is in the low voltage state (V _DC
-Ω) and VRH signal, VR synchronized with ADJ signal
Both the L signals are in the high potential state. Also, ADJ signal, F
Since the RP signals have the same polarity, the controller 13 '
Determines that the period is an odd line scanning period.

At this time, the scanning line G ₁ is at a high voltage and T
When the FT 30 is turned on, the potential Vp of the pixel electrode 31a of the pixel P ₁ becomes substantially equal to the potential of the signal line. At this time, since the signal voltage D applied to the signal line D ₁ is VRH1,
The potential Vp of the pixel electrode 31a of the pixel P ₁ becomes VRH1. Next, the scanning line G ₁ becomes low potential, and the TFT 30 becomes O
At FF, due to the influence of the parasitic capacitance 32, the pixel electrode 31
The potential Vp of a becomes (V _RH1- ΔV). Therefore, the pixel P ₁
Potential difference VLCD of the LCD capacitor 31 of VLCD = (VRH1
−ΔV−Vcom) = (V _RH1 −ΔV−V _DC + Ω).

When the odd line scanning period is switched to the even line scanning period (period b), the common signal generation circuit 16 inverts the common voltage Vcom to the high potential state (V _DC + Ω). Further, the inverting amplifier 11 inverts the signal voltage D from a low potential to a high potential. However, at this time,
The VRH signal and the VRL signal remain in the high potential state. Therefore, the signal voltage D is inverted from VRH1 to VRL1.

At this time, the scanning line G ₂ has a high voltage and TF
When T30 is turned on, a signal voltage is applied to the pixel P ₂ and the potential Vp of the pixel electrode 31a becomes VRL1. Then, the scanning lines G ₂ becomes a low potential, the TFT30 is OFF, the due to the influence of the parasitic capacitance 32, the potential Vp of the pixel electrode 31a becomes (VRL1-ΔV). The potential difference of the LCD capacitor 31 of the pixel P ₂ is VLCD = (VRL1-V _DC −Ω−Δ
V).

On the other hand, in the pixel P ₁ , when the common voltage Vcom is inverted, the electric charge of the pixel electrode 31a slightly leaks through the parasitic capacitance 32, so that the electric potential decreases by Δα and the electric potential Vp of the pixel electrode 31a becomes a signal. Since the potential is relatively higher than the line potential, a leak current is generated through the OFF resistance of the TFT 30. The decrease in the potential of the pixel electrode 31a due to this is Δ
Assuming β, the potential difference of the pixel P ₁ is VLCD = (V _RH1 −V _DC
-Ω-ΔV-Δα-Δβ).

Now, the potential difference VLCD of the LCD capacitor 31 of the pixel P ₁ and L of the pixel P _{2 in} the even line scanning period.
Comparing the absolute values of the potential difference VLCD of the CD capacitor 31, the potential difference of the LCD capacitor 31 of the pixel P ₁ is (2λ−
2ΔV−Δα−Δβ) for the LCD capacity 3 of the pixel P _2.
It is larger than the potential difference of 1.

The above results show that the common voltage Vcom,
The same holds true when the ADJ signal and the FRP signal start in opposite phases.

This conclusion is equivalent to the result in the first embodiment, and if the value of λ is set to the value shown in the following expression (3), the charge amount charged in the LCD capacitor 31 of the pixel P ₁ becomes. It can be corrected to be substantially equal to the charge amount of the LCD capacitor 31 of the pixel P ₂ . λ = (2ΔV + Δα + Δβ) / 2 (3) As a result, the striped pattern for each line is eliminated, and flicker can be prevented.

[Fourth Embodiment] A fourth embodiment will be described below with reference to FIGS. 13 to 15. In the third embodiment described above, the potential difference of the LCD capacitor 31 of each pixel is changed for each scanning period by appropriately changing the output range of the signal voltage.

On the other hand, in the fourth embodiment, the memory 1
The display data (specifically, the gradation signal) stored in 2 is converted, and as a result, the potential difference applied to the LCD capacitor 31 of each pixel is changed for each scanning period.

Hereinafter, the fourth embodiment will be described in detail, but the description of the same functions and configurations as those of the first embodiment will be omitted, and the same reference numerals and names will be used. The difference will be mainly described.

First, the structure of the display driving apparatus 200 according to the fourth embodiment will be described. FIG. 13 is a diagram showing an example of a circuit configuration of the display drive device 200 according to the fourth embodiment. According to the figure, the display driving apparatus 200 according to the fourth embodiment is different from the first embodiment described with reference to FIG. 6 in that the ROM 71 is provided between the memory 12 and the source driver 14. The display drive device 1 in FIG.

The controller 13 ″ in the fourth embodiment outputs to the inverting amplifier 11 based on the horizontal synchronizing signal and the vertical synchronizing signal input from the RGB decoder 10 as in the first embodiment. It generates an inversion control signal, a memory control signal and an address control signal output to the memory 12, a horizontal control signal output to the source driver 14, and a vertical control signal output to the gate driver 15, and also generates an ADJ signal and an FRP signal. The waveforms of the ADJ signal and the FRP signal are the same as the waveforms described in the first embodiment.

However, in the fourth embodiment, the ADJ
The signal is not used as a signal for changing the amplitude of the common voltage Vcom, but is used as a signal for determining the timing of converting the gradation signal. The controller 1
3 ″ is for the ROM 71, the memory control signal, the FRP
Signal and ADJ signal are output. Further, only the FRP signal is output to the common signal generation circuit 16 '.

The common signal generation circuit 16 ′ uses the common voltage Vco based on the FRP signal input from the controller 13.
m is generated and supplied to the common electrode 31b of each pixel on the liquid crystal display panel 20. However, the common voltage Vcom in the fourth embodiment has a polarity opposite to the polarity of the FRP signal, and the amplitude is always constant. For example, a signal obtained by inverting and amplifying the FRP signal using a differential amplifier or the like is output to the liquid crystal display panel 20 as the common voltage Vcom.

The ROM 71 has two types of conversion tables A,
B, using the conversion tables A and B, the memory 1
The gradation signal input from 2 is converted for each line (scanning line). Then, the converted result is output to the source driver 14.

FIG. 14 is a diagram for explaining the concept of gradation signal conversion by the ROM 71. The conversion examples A and B correspond to the conversion tables A and B included in the ROM 71, respectively. In the figure, each gradation signal is represented by a hexadecimal number (H). In addition, a low value (00H) in hexadecimal is associated with a high potential (VRH),
A high value (3FH) corresponds to a low potential (VRL).

In FIG. 14, according to the conversion table A, the input data (gradation signal) from the memory 12 is "0.
"0H" corresponds to "00H" and "1FH" becomes "1B"
"3FH" is made to correspond to "37H". That is, the input data from the memory 12 is set to a value on the high potential side, and the input data having a higher value is set to be shifted to the higher potential side more.

On the other hand, according to the conversion table B, the memory 1
Input data "00H" from 2 is associated with "07H", "1FH" is associated with "23H", and "3FH" is associated with "3FH". That is, the input data from the memory 12 is set to a value on the lower potential side, and the lower the value of the input data, the more the input data is shifted to the lower potential side.

The ROM 71 determines the switching timing of the conversion tables A and B based on the ADJ signal and the FRP signal input from the controller 13 ″. Further, based on the memory control signal input from the controller 13 ″,
The gradation signals for one line are sequentially converted in synchronization with signal input / output with the memory 12 and the source driver 14.

The source driver 14 determines a signal voltage based on the gradation signal for one line input from the ROM 71 and outputs it to each signal line. The processing method is the same as that of the first embodiment.

FIG. 15 is a diagram showing an example of drive waveforms of the display drive device 200 according to the fourth embodiment. In the following, a case will be described as an example in which all pixels of the liquid crystal display panel 20 perform black display (or white display).

Common voltage Vcom, scanning lines G ₁ , G ₂ , ADJ
The waveforms of the signal and the FRP signal are the same as those described in the third embodiment, and thus the description thereof is omitted here.

The ROM 71 reads the conversion table A for shifting the gradation signal to the high potential side when the ADJ signal in the figure is in the high potential state (period A), and performs the conversion process.

For example, when the signal “00H” is input from the memory 12 to the ROM 71 during the odd line scanning period of the period A, the ROM 71 outputs “00H” to the source driver 14. Therefore, the pixel P ₁ has “00
The voltage VRH corresponding to "H" is applied.

On the other hand, in the even line scanning period of the period A,
The signal is inverted by the inverting amplifier 11, and “3FH” is input from the memory 12 to the ROM 71. In the period A, that is, when the ADJ signal is in the high potential state, the conversion table A is selected.
The “3FH” signal input from 2 is converted to “37H” and output to the source driver 14. Thus, the pixel P ₂ is a possible voltage corresponding to the signal of "37H" is applied.

Now, in the period A, the pixel electrode 3 of the pixel P ₁ is
The potential difference between the potential Vp applied to 1a and the inversion reference potential V _DC (intermediate potential between V _RH and V _RL ) of the common voltage Vcom, and the pixel P
Comparing the potential Vp applied to the _second pixel electrode 31a and the potential difference between the inversion reference potential V _DC , the pixel electrode 31 of the pixel P ₁
The potential Vp applied to a has a larger potential difference with respect to the inversion reference potential V _DC, and as a result, a state equivalent to that of the above-described third embodiment can be obtained.

Therefore, when the odd-numbered line scanning period is switched to the even-numbered line scanning period, the increase in leak of each pixel on the odd-numbered line is compensated for, the change in brightness of the odd-numbered line and the even-numbered line is suppressed, and flicker is prevented. It becomes possible.
Note that the same is true in the period B, that is, when the ADJ signal is in the low potential state.

As described above, according to the conversion example shown in FIG. 14 according to the fourth embodiment, by converting the gradation signal, as a result, the output range of the signal voltage changes for each frame. . Therefore, the same effect as that of the third embodiment can be obtained.

The detailed portions described in the above embodiments are not limited to the above contents, but can be changed as appropriate. For example, in the above-described first to fourth embodiments, it has been described that the odd line is scanned in the first field, the even line is scanned in the second field, and the polarity is inverted every frame. However, when using a liquid crystal display panel with a relatively small number of scanning lines, 1 /
Scan odd and even lines every 2 fields and
The polarity may be inverted for each field.

In the above embodiment, the case of scanning from an odd line has been described as an example, but it goes without saying that scanning may be performed from an even line. However, in this case, the timing of inverting the polarity is preferably set to switch from the even line to the odd line.

[0162]

According to the present invention, from the first scanning period to the second scanning period.
At the time of switching to the scanning period, the polarity reversing means inverts the electric potentials of the pixel electrode and the common electrode, and so-called interlaced scanning is performed by the scanning control means. Therefore, the power consumption for driving the signal applied to the common electrode is about the same as that for the frame inversion driving, and the difference in brightness (brightness difference) between adjacent lines (odd line and even line) is canceled. It Therefore, it is possible to suppress flicker and improve the display quality.

Here, due to the inversion of the potential of the common electrode by the polarity determining means, in the first scanning period and the second scanning period,
The potential of the pixel electrode changes. As a result, when the potential difference applied between the pixel electrode and the common electrode is set to be constant, for example, the first scanning period and the second scanning period are caused by the leakage current based on the OFF resistance of the TFT that drives each pixel of the liquid crystal panel. Then, a difference occurs in the charge amount of the pixel for each scanning line, the brightness of the pixel changes, and the display quality deteriorates. In contrast,
The potential difference control unit corrects the potential difference between the pixel electrode and the common electrode according to whether the current scanning period is the first scanning period or the second scanning period, and, for example, considering the influence of leak current,
The control is performed so as to reduce the difference in the charge amount of the pixels for each scanning line. More specifically, for example, the potential difference control means,
By considering the amount of leak current and setting the potential difference between the pixel electrode and the common electrode, the difference in magnitude of leak current is eliminated,
As a result, it is possible to improve the display quality by eliminating the difference in the luminance of the pixels for each scanning line.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a liquid crystal display panel including pixels of 2n × 2n dots.

FIG. 2 is a diagram schematically showing a configuration of a pixel formed on a liquid crystal display panel.

FIG. 3 is a diagram showing an example of drive waveforms of a display drive device when performing interlaced scanning drive.

FIG. 4 is a schematic diagram illustrating changes in the potential of the LCD capacitor 31 of the pixel P ₁ .

FIG. 5 is a schematic diagram illustrating changes in the potential of the LCD capacitor 31 of the pixel P ₂ .

FIG. 6 is a diagram showing an example of a circuit configuration of a display driving device in the first embodiment.

FIG. 7 is a diagram illustrating a configuration of a common signal generation circuit according to the first embodiment.

FIG. 8 is a diagram showing an example of drive waveforms of the display drive device according to the first embodiment.

FIG. 9 is a diagram illustrating a circuit configuration of a common signal generation circuit according to a second embodiment.

FIG. 10 is a diagram showing an example of a circuit configuration of a display drive device according to a third embodiment.

FIG. 11 is a schematic diagram showing an output range of a signal voltage according to the third embodiment.

FIG. 12 is a diagram showing an example of drive waveforms of the display drive device according to the third embodiment.

FIG. 13 is a diagram showing an example of a circuit configuration of a display drive device according to a fourth embodiment.

FIG. 14 is a diagram for explaining an example of conversion of a gradation signal by a ROM.

FIG. 15 is a diagram showing an example of drive waveforms of the display drive device according to the fourth embodiment.

16A is a diagram showing an example of drive waveforms of a liquid crystal display device which performs frame inversion drive. FIG. FIG. 6B is a diagram showing a state of polarity inversion on the liquid crystal display panel in frame inversion driving.

FIG. 17A is a diagram showing an example of drive waveforms of a liquid crystal display device which performs line inversion drive. FIG. 6B is a diagram showing a state of polarity inversion on the liquid crystal display panel in the line inversion drive.

FIG. 18A is a diagram showing an example of drive waveforms of a liquid crystal display device which performs dot inversion drive. FIG. 6B is a diagram showing a polarity inversion state on the liquid crystal display panel in dot inversion drive.

[Explanation of symbols]

1,100,200 display drive 10 RGB decoder 11 Inverting amplifier 12 memories 13, 13 ', 13 "controller 14,14 'Source driver 15 Gate driver 16, 16 'common signal generation circuit 20 LCD display panel 30 TFT 31 LCD capacity 31a Pixel electrode 32 common electrode 32 parasitic capacitance 70 gradation signal selection circuit 71 ROM

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 621 G09G 3/20 621B 622 622N 624 624C 641 641P F term (reference) 2H092 JA24 NA01 NA26 PA06 2H093 NA16 NA31 NA41 NC03 NC34 NC35 ND10 ND39 5C006 AC21 AC25 AC27 AF42 AF46 BB16 BF24 BF25 BF43 FA23 FA36 FA47 5C080 AA10 BB05 DD06 DD26 EE28 FF11 JJ02 JJ03 JJ04

Claims (8)

[Claims] 1. A display comprising a plurality of scanning lines, a plurality of signal lines, pixels having pixel electrodes arranged in a matrix in the vicinity of respective intersections of the respective lines, and a common electrode facing the respective pixel electrodes. In a display driving device that applies a display signal voltage to each of the signal lines of a panel to drive, a first scanning period in which each of the scanning lines is interleaved and sequentially scanned, and an interlacing is performed in the first scanning period. A second scanning period for sequentially scanning the scanning lines, and scanning control means for scanning all the scanning lines of the display panel; and, at the time of switching from the first scanning period to the second scanning period, Polarity inversion means for inverting the potentials of the pixel electrode of each pixel and the common electrode; and potential difference correction means for correcting the potential difference between the pixel electrode of each pixel and the common electrode for each scanning period. A display drive device characterized by the above. 2. The display drive device according to claim 1, wherein the correction of the potential difference is performed so as to reduce the difference in the amount of electric charge applied to the pixel for each scanning line. 3. The potential difference control unit corrects the potential difference between the pixel electrode and the common electrode by correcting the potential of the common electrode for each scanning period. Display drive device. 4. The potential difference control means selects one voltage from two types of voltages for setting the high-voltage side potential of the common electrode, and selects two types of voltage for setting the low-voltage side potential of the common electrode. The display drive device according to claim 3, further comprising a common electrode voltage switching unit that selects one voltage from the voltages. 5. The potential difference control means corrects the potential difference between the pixel electrode and the common electrode by correcting the gradation reference voltage range of the display signal voltage for each scanning period. The display drive device according to claim 1. 6. The potential difference control means, in each of the scanning periods, a grayscale voltage of a signal voltage from among two types of the highest grayscale reference voltage of the display signal voltage and two types of the lowest grayscale reference voltage. 6. The display drive device according to claim 5, further comprising: a gradation reference voltage switching unit that selects 1 highest gradation reference voltage and 1 lowest gradation reference voltage, which serve as a reference. 7. The potential difference control means corrects the potential difference between the pixel electrode and the common electrode by converting the display signal for generating the display signal voltage and correcting the display signal voltage for each scanning period. The display drive device according to claim 1, wherein: 8. The potential difference control means converts the display signal in the first scanning period to correct the display signal level in one of upper and lower directions, and the second scanning period. 8. The display drive device according to claim 7, further comprising: a second conversion unit that converts the display signal and corrects the display signal level in another direction of up and down.