JPH0758948B2 - Multiprocessing frame synchronization circuit - Google Patents
Multiprocessing frame synchronization circuitInfo
- Publication number
- JPH0758948B2 JPH0758948B2 JP1124432A JP12443289A JPH0758948B2 JP H0758948 B2 JPH0758948 B2 JP H0758948B2 JP 1124432 A JP1124432 A JP 1124432A JP 12443289 A JP12443289 A JP 12443289A JP H0758948 B2 JPH0758948 B2 JP H0758948B2
- Authority
- JP
- Japan
- Prior art keywords
- synchronization state
- current
- state information
- signal
- condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多重フレーム信号の同期状態を示す信号の送
出を行なうフレーム同期回路に関するものである。TECHNICAL FIELD The present invention relates to a frame synchronization circuit for transmitting a signal indicating a synchronization state of a multiplex frame signal.
かゝるフレーム同期回路においては、現在の多重フレー
ム信号と直前の同期状態を示す同期状態情報との比較に
基づく現在の同期状態情報をROM等のメモリへテーブル
として格納のうえ、現在の多重フレーム信号と直前の同
期状態情報とによりメモリの読出しアドレスを指定し、
これにより読出した内容を現在の同期状態を示す信号と
して送出するものとなつている。In such a frame synchronization circuit, the current synchronization state information based on the comparison between the current multiplex frame signal and the synchronization state information indicating the immediately previous synchronization state is stored in a memory such as a ROM as a table, and then the current multiplex frame is stored. The read address of the memory is specified by the signal and the previous synchronization status information,
As a result, the read content is transmitted as a signal indicating the current synchronization state.
しかし、従来においては、ROMの内容として特定条件の
多重フレーム信号に対応する同期状態情報しか格納され
ておらず、多重フレーム信号のフレームビツト数、同期
状態を維持するための保護段数等、多重フレーム信号の
条件が変更された場合、ROMを交換せねばならず、フレ
ーム同期回路としての汎用性に欠如する欠点を生じてい
た。However, in the past, only the synchronization state information corresponding to the multiplex frame signal of a specific condition is stored as the contents of the ROM, and the number of frame bits of the multiplex frame signal, the number of protection steps for maintaining the synchronization state, etc. When the signal conditions are changed, the ROM has to be replaced, which causes a drawback of lacking versatility as a frame synchronization circuit.
前述の課題を解決するため、本発明はつぎの手段により
構成するものとなつている。In order to solve the above-mentioned problems, the present invention comprises the following means.
すなわち、上述のフレーム同期回路において、多重フレ
ーム信号の条件に応ずる現在の同期状態情報を各個に格
納し、多重フレーム信号の条件を示す選択信号、およ
び、現在の多重フレーム信号、ならびに、直前の同期状
態情報により読出しアドレスの指定を受けるメモリを設
けたものである。That is, in the above frame synchronization circuit, the current synchronization state information corresponding to the condition of the multiplex frame signal is stored in each of them, and the selection signal indicating the condition of the multiplex frame signal, the current multiplex frame signal, and the immediately previous synchronization signal are stored. A memory provided with a read address specified by the status information is provided.
したがつて、多重フレーム信号の条件に応じて選択信号
を設定することにより、メモリから条件に対応した同期
状態情報の読出しがなされ、フレーム同期回路としての
汎用性が得られる。Therefore, by setting the selection signal according to the condition of the multiplex frame signal, the synchronization state information corresponding to the condition is read out from the memory, and versatility as a frame synchronization circuit is obtained.
以下、実施例を示すブロツク図によつて本発明の詳細を
説明する。The present invention will be described in detail below with reference to block diagrams showing examples.
同図においては、メモリとしてROM1が設けてあり、これ
には、多重フレーム信号のフレームビツト数、同期状態
維持用の保護段数等の条件に応じ、かつ、各条件毎に、
現在の多重フレーム信号と直前の同期状態情報との比較
に基づく現在の同期状態情報が各個に複数のテーブルと
して格納されている。In the figure, a ROM 1 is provided as a memory, which includes the number of frame bits of a multiplex frame signal, the number of protection stages for maintaining a synchronization state, and the like, and for each condition,
The current synchronization state information based on the comparison between the current multiplex frame signal and the immediately previous synchronization state information is stored in each as a plurality of tables.
ROM1は、多重フレーム信号の条件に応じて設定されるｌ
ビツトの選択信号（以下、SEL）２、および、１ビツト
の多重フレーム信号（以下、MFS）３、ならびに、RAM4
からのｍ−１ビツトによる直前の同期状態情報５によ
り、ｌ＋ｍビツトの読出しアドレス指定を受けており、
SEL2に応ずる条件かつMFS3ならびに同期状態情報５にし
たがい、現在の同期状態が同期または非同期であるか等
を示すｍ−１ビツトの同期状態情報６を送出する。ROM1 is set according to the condition of the multi-frame signal
Bit selection signal (SEL) 2 and 1-bit multiple frame signal (MFS) 3 and RAM4
The read address designation of the l + m bit is received by the immediately preceding synchronization state information 5 by the m-1 bit from
According to the condition according to SEL2 and the MFS3 and the synchronization state information 5, the synchronization state information 6 of m-1 bit indicating whether the current synchronization state is synchronous or asynchronous is transmitted.
この、現在の同期状態情報６は、ラツチ回路７によりラ
ツチ信号（以下、LS）８に応じて保持され、現在時点ｎ
の同期状態を示す信号SFとして送出されると共に、バツ
フア回路９にも与えられており、RAM4への読出し／書込
み信号（以下、R/W）10が書込み状態のとき、バツフア
回路９が活性化し、これを介して現在の同期状態情報６
がRAM4へ与えられ、書込みパルス（以下、WP）11にした
がつてRAM4へ格納され、この内容がつぎの時点において
直前の時点ｎ−１における同期状態情報５となり、ROM1
のアドレス指定に用いられるものとなつている。This current synchronization state information 6 is held by the latch circuit 7 in accordance with the latch signal (hereinafter, LS) 8 and the current time n.
Is sent as a signal SF indicating the synchronization state of the buffer and is also given to the buffer circuit 9. When the read / write signal (hereinafter, R / W) 10 to the RAM 4 is in the write state, the buffer circuit 9 is activated. , Through this the current sync state information 6
Is given to the RAM4 and stored in the RAM4 in accordance with the write pulse (hereinafter referred to as WP) 11, and the contents become the synchronization state information 5 at the immediately preceding time point n-1 at the next time point, and the ROM1
It is supposed to be used for addressing.
また、RAM4のアドレス指定は、MFS3のクロツクパルス
（以下、CLK）12をカウントする多重カウンタ13のカウ
ント出力により行なわれており、これに応じたアドレス
へ現在の同期状態情報６が格納されると共に、同様に内
容の読出しが行なわれるものとなつている。In addition, the addressing of the RAM4 is performed by the count output of the multiple counter 13 that counts the clock pulse (hereinafter, CLK) 12 of the MFS3, and the current synchronization state information 6 is stored in the address corresponding to this. Similarly, the contents are supposed to be read out.
なお、LS8、R/W10、WP11等は、CLK12に基づき互に一定
の時間関係として与えられる。Note that LS8, R / W10, WP11, etc. are given to each other as a fixed time relationship based on CLK12.
したがつて、SEL2に応じてROM1中のテーブルが選択さ
れ、MFS3の条件に対応する現在の同期状態情報６が得ら
れるため、MFS3の条件変更にしたがいSEL2を設定するこ
とにより、ROM1を交換せずに対処することができる。Therefore, the table in ROM1 is selected according to SEL2, and the current synchronization status information 6 corresponding to the condition of MFS3 is obtained. Can be dealt with without.
以上の説明により明らかなとおり本発明によれば、多重
フレーム信号の条件に応ずる現在の同期状態情報をメモ
リへ各個に格納し、多重フレーム信号の条件を示す選択
信号も併せてメモリの読出しアドレス指定に用いるもの
としたことにより、多重フレーム信号の条件が変更され
てもメモリの交換が不要となるため、フレーム同期回路
の汎用性が実現し、多重フレーム信号の同期状態検出に
おいて顕著な効果が得られる。As is apparent from the above description, according to the present invention, the current synchronization state information according to the condition of the multiplex frame signal is stored in each memory, and the selection signal indicating the condition of the multiplex frame signal is also specified together with the read address designation of the memory. Since it is not necessary to replace the memory even if the conditions of the multiplex frame signal are changed, the versatility of the frame synchronization circuit is realized and a remarkable effect is obtained in detecting the synchronization state of the multiplex frame signal. To be
図は本発明の実施例を示すブロツク図である。 １……ROM、２……選択信号、３……多重フレーム信
号、５……直前の同期状態情報、６……現在の同期状態
情報。The figure is a block diagram showing an embodiment of the present invention. 1 ... ROM, 2 ... selection signal, 3 ... multiplex frame signal, 5 ... immediately previous sync status information, 6 ... current sync status information.
Claims (1)
情報との比較に基づく現在の同期状態情報を格納したメ
モリを備え、前記現在の多重フレーム信号と直前の同期
状態情報とにより前記メモリの読出しアドレスを指定
し、該読出した内容を現在の同期状態として送出するフ
レーム同期回路において、前記多重フレーム信号の条件
に応ずる前記現在の同期状態情報を各個に格納し前記条
件を示す選択信号および現在の多重フレーム信号ならび
に直前の同期状態情報により読出しアドレスの指定を受
けるメモリを設けたことを特徴とする多重処理形フレー
ム同期回路。1. A memory is provided which stores current synchronization state information based on a comparison between a current multiplex frame signal and immediately previous synchronization state information, and the memory stores the current multiplex frame signal and the immediately previous synchronization state information. In a frame synchronization circuit for designating a read address and transmitting the read content as a current synchronization state, the current synchronization state information corresponding to the condition of the multiplex frame signal is stored in each of them, and a selection signal indicating the condition and a current condition A multi-processing type frame synchronization circuit, which is provided with a memory for receiving a designation of a read address in accordance with the multiplex frame signal and the immediately preceding synchronization state information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1124432A JPH0758948B2 (en) | 1989-05-19 | 1989-05-19 | Multiprocessing frame synchronization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1124432A JPH0758948B2 (en) | 1989-05-19 | 1989-05-19 | Multiprocessing frame synchronization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02305131A JPH02305131A (en) | 1990-12-18 |
| JPH0758948B2 true JPH0758948B2 (en) | 1995-06-21 |
Family
ID=14885342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1124432A Expired - Lifetime JPH0758948B2 (en) | 1989-05-19 | 1989-05-19 | Multiprocessing frame synchronization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758948B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2692438B2 (en) * | 1991-07-15 | 1997-12-17 | 日本電気株式会社 | Frame synchronization circuit |
-
1989
- 1989-05-19 JP JP1124432A patent/JPH0758948B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02305131A (en) | 1990-12-18 |
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