JPS61163741A - Multiplexing device - Google Patents

Abstract

PURPOSE:To simplify a device by omitting the multiplexing to 64 kilobits per second, and executing directly the multiplexing to 1.544 megabits per second from a low bit rate. CONSTITUTION:Plural input data are multiplexed directly by a single multiplexing device 1. As for a bit constitution, one frame is constitute of a synchronizing bit of 1 bit and a data bit of 192 bits, and also a synchronizing bit 2 is formed by using 1 bit in 192 bits. 1 bit in one multi-frame is 1 bit per 2.5msec, therefore, information of 400BPS can be transmitted. Accordingly, when executing a transmission of 400xnBPS, a data extending from a low sped to a high speed can be multiplexed directly by assigning (n) bits in one multi-frame.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexing device that multiplexes, for example, a plurality of input data (digital signals) of 400 to 96008 PS into data of TS 44 MBPs.

[Conventional technology]

FIG. 4 shows an example of the configuration of this type of device that has been used conventionally.

In the figure, (7) represents 64 KB of data of 0, 4 to 9.6 KB)'S input in parallel from each terminal machine (not shown).
The multiplexer L, +81 that multiplexes the PS data is the multiplexed output data 64KH of these multiplexers 1 (7).
This is a multiplexer layer that multiplexes PS into 1.544MBPS.

In Figure 4, data input is normally 200BPS to 96BPS.
The QOBPS digital signals are multiplexed into a 64KB)'S signal in a multiplexer I (7).

The degree to which multiplexing is possible depends on whether the input data is synchronous or asynchronous, and is not necessarily constant.

64KBPS data is transmitted at the multiplexer layer (8) by 1.5
It is multiplexed into 44MBPS (of which 5KB)'S is additional information necessary for synchronization).

Since these are commonly used in the world, detailed explanations will be omitted.

[Problem that the invention seeks to solve]

Conventional multiplexers are not configured as described above, so
This method has the disadvantage that multiplexing devices must be used frequently and the cost is extremely high.

This invention was made to solve the above problems, and aims to provide the same functions simply and at a low cost.

[Means for resolving gaps in studying]

The multiplexing device according to the present invention omits multiplexing to 64KBPS and directly converts the low bit rate to 1.544MB).
The purpose of this is to simplify the device since the car number is multiplexed to 'S.

[Effect]

Direct multiplexing in this invention omits the multiplexing part to 64KBPS, so the more data to be multiplexed, the more effective it is.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall diagram of the present invention, shown for comparison with the prior art (υ is a multiplexing device).

FIG. 2 is a diagram showing the internal configuration of Ill of the multiplexing device in FIG. 1, in which (2) is a gate circuit, (3) is an address decoder, (4) is a memory such as [) IVI, is a counter, and (6) is a synchronization bit generation circuit.

Further, FIG. 8 is a time chart (frame structure) for explaining the operation of FIG. 2.

Next, the operation will be explained. As shown in FIG. 1, the present invention directly multiplexes a plurality of input data with a single multiplexing ratio value filtt>. In FIG. 8, a standard configuration of a PCM signal is shown. As for the bit structure, one frame consists of one synchronization bit and 192 data bits. Here, 1 bit out of 192 bits is used as synchronization bit 2. If a code having one cycle every 20 frames is used for synchronization bit 2, it becomes possible to detect the cycle every 20 frames. One multiframe of these 20 frames is 125μS
Since it is eC, 1 multiframe is 2.5m5eC. Therefore, 1 bit in 1 multiframe is 2.5m5
Since ec is 1 bit, 4008 PS of information can be transmitted.

Therefore, by allocating n bits in one multiframe for transmission of 400xnBPs, data from low speed to high speed can be directly multiplexed. There is 198×20=8860 bits of data in one multiframe.

Next) In this Figure 2, the counter (5) is this 886
It operates cyclically with a cycle of °. Counter (5
) is connected to the address of memory t41,
This indicates the order of bits within the multiframe.

Since the memory (4) corresponds to addresses and has information on which input data should be obtained, it outputs the required address of the gate (2) as an output. The address decoder (3) determines from the output of the memory whether or not it corresponds, and if instructed, outputs an ON signal to the gate (2).

The synchronization bit generation circuit (6) sends the synchronization bit to the data output at the timing when the synchronization bit should be generated from the output of the counter (6).

Since all bits of the multiframe are managed, data at any bit rate can be directly multiplexed at any data transmission rate in units of 4008 PS.

〔Effect of the invention〕

As described above, according to the present invention, the frame (multi-frame) length is formed to cover the lowest and highest transmission speeds of input data, and low-speed input data is directly multiplexed, thereby simplifying the configuration of the device. The effect is that the greater the number of input data, the higher the efficiency of increasing the blood count.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of an embodiment of the present invention;
Fig. 2 is a block diagram showing the internal configuration of Fig. @1, Fig. 8 is a time chart (frame structure) diagram for explaining the operation of Fig. 2, and Fig. 4 is a block diagram showing a conventional multiplexing device. It is. In the figure, (2) is a gate circuit, (3) is an address decoder, (4) is a memory, (5) is a counter, and (6) is a synchronization bit generation circuit. or a corresponding portion.

Claims (1)

[Claims] (1) A plurality of input data having a transmission speed of f, 2f, 3f...nf [BPS] is transmitted at a transmission speed of F [BP].
S], which converts the speed into high-speed data and multiplexes it for transmission, the length of one frame is formed by l/(nf) [sec], the number of frame bits is F/(nf), and this frame is A multiplexing device comprising a multiplexing circuit that forms a multi-frame consisting of n pieces, and multiplexing and transmitting the plurality of input data using the multi-frame formed by the multiplexing circuit as a unit period.