JPH0756869B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a mesa type semiconductor device having a high breakdown voltage and a high-speed switching characteristic, and particularly to achieve both a high breakdown voltage and a high switching characteristic. It is related to the formation of the PN junction exposed on the mesa surface.

(Prior Art) In a conventional semiconductor device having high breakdown voltage and high switching characteristics, for example, a transistor, a base region of a one-step structure having a substantially uniform depth in the thickness direction of a substrate is separated by a mesa groove, The exposed end surface of the collector-base junction has a passivation (passiv) having a positive charge (positive ion).
A method of coating with a material to give pressure resistance is generally performed. For example, it has a structure as shown in FIG. 7 or 8. An N-type substrate 1 in which an N ⁺ collector region 2 and an N ^- collector region 3 are stacked is diffused to form a P
Base region 4A (Fig. 7) or P base region 4B (Fig. 8)
Figure) is formed, and each emitter region 5 is diffused and formed in each region. Further, a base electrode 6 and an emitter electrode 7 which make ohmic contact with the respective base region and emitter region are provided. Also, a mesa groove 8 for separating the base region is dug and filled with a passivation material 9. The transistor illustrated in FIG. 7, the base width (hereinafter referred to as W _B) is wider than the FIG. 8, the switching characteristics compared to the transistor of Figure 8 is slow.

As the passivation material to fill the mesa groove, glass (SiO ₂ ) or rubber, gel-based joint coating material (Junction coating material JCR), etc. have been generally used, and most of them are positive type materials. Charge (eg Na ⁺
I have) etc. To generally have a high-speed switching characteristics to a transistor, it is known as it is necessary to form narrow (W _B shown in FIG. ₇₎ the base width. In this case, when forming the base layer by diffusion, the depth of the base layer (X _jB shown in FIG. 7) must be shallow. Such W _B is narrow, shallow or base-collector junction of X _jB there is a problem that it is difficult to high breakdown voltage in a shallow transistor from the substrate surface.
For example, FIG. 9 shows the base of such a transistor.
6 is a characteristic curve showing an example of the relationship between V _CB and I _CB when a reverse bias is applied between collectors. When V _CB is small, 1 _CB is almost equal to 0, and when V _CB increases, I _CB becomes remarkable from a certain point, and when V _CB exceeds a certain value, I _CB increases.
_CB rises sharply and shows a bent waveform.
The junction breaks down. This breakdown voltage does not change significantly even if the width W _C of the N ⁻ collector region is increased.

(Problems to be Solved by the Invention) As described above, the PN junction exposed in the mesa groove is located at a shallow position from the substrate surface, and in particular, the one having a positive charge in the passivation material which protects the junction end face cannot have a higher withstand voltage. There is a problem that it is difficult.

While the PN junction, in the case of bonding between the base and collector of the transistor, forming the PN junction at a deep position from the substrate surface, that is, when deep X _jB W _B becomes wide, therefore a high _T ransition frequency f _T and the high-speed It becomes difficult to obtain switching characteristics.

An object of the present invention is to solve the above problems and to provide a semiconductor device having both high breakdown voltage characteristics and high-speed switching characteristics.

[Structure of the Invention] (Means for Solving the Problems) The present invention is directed to a one-conductivity-type semiconductor substrate and two steps in which the depth from the main surface is selectively formed on one main surface side. An opposite conductivity type region of the structure; and a mesa groove that extends from the main surface of the substrate of the deeply formed opposite conductivity type region portion to the one conductivity type region of the substrate through the deeply formed opposite conductivity type region. A junction between the one conductivity type region and the opposite conductivity type region is exposed in the mesa groove at the bottom of the deeply formed opposite conductivity type region, and the mesa groove is filled with a passivation material. Semiconductor device.

(Function) When the PN junction exposed in the mesa groove is located at a shallow position from the substrate surface and the exposed junction end face is protected by a passivation material containing a positive charge, these may cause difficulty in increasing the withstand voltage. Become. Taking the collector-base junction of an NPN transistor as an example, the reason why it is difficult to increase the breakdown voltage will be described below. FIG. 6 is a sectional view in which only a necessary portion is enlarged for the purpose of explaining the reason. In the mesa groove 8, the junction J _CB between the P base region 4C and the low-concentration N ⁻ collector region 3 is exposed and contains a positive charge. The end surface of the joint J _CB is protected by the passivation material 9. When a reverse bias is applied to this junction J _CB , a depletion layer 10 (a region between two curves indicated by a dotted line) is formed as shown in FIG. Since the passivation material containing positive charges is formed near the exposed end of the junction, the depletion layer near the surface bends as shown by the dotted line in the figure.
This phenomenon becomes more pronounced as the amount of positive charge contained in the passivation material increases.

Here, as described above, when X _jB is made shallow in order to improve the high-speed switching characteristics, the depletion layer on the P base region 4C side easily reaches the edge portion between the main surface of the semiconductor substrate and the mesa groove. When the edge of the depletion layer reaches the surface of the substrate, the extension of the depletion layer is hindered and the electric field concentrates on the edge portion, causing a local breakdown. It was inferred that it was difficult to increase the withstand voltage of a mesa transistor that was passivated with a passivation material having a positive charge when X _jB was made shallow in this way, and it was also confirmed by trial.

The present invention has been completed based on the above reasoning.

That is, the present invention solves the above-mentioned problems by, for example, making the structure of the base layer a shallow two-stage structure in the depth direction and increasing the base depth near passivation, that is, the depth of the exposed J _CB end. Is. More specifically, in the present invention, a mesa groove is formed in a base region portion having a deep X _jB, and an end of the junction J _jB affected by the positive charge of the passivation material is formed at a deep position from the substrate surface. while securing a high breakdown voltage, the transistor active part influencing the switching characteristics, formed in a shallow base region of X _jB, it is obtained by securing a high-speed switching characteristics by narrowing the W _B.

(Embodiment) An embodiment of the present invention will be described with an NPN high breakdown voltage high speed switching transistor as an example. FIG. 1 is a schematic sectional view of the transistor. In addition, the last digit of the code is the same as in FIG. 7 or FIG. An N type (one conductivity type) semiconductor substrate 11 in which an N ⁺ collector region 12 and an N ⁻ collector region 13 are stacked is provided with a deep P type base region (referred to as P ₁ base region) 14a by selective diffusion. A P-type (opposite conductivity type) base region 14 having a shallow deep two-stage structure, which is composed of a shallow P-type base region (referred to as P ₂ base region) 14b, is provided. An N ⁺ emitter region 15 is formed by selective diffusion in the shallow P ₂ base region. Further, a mesa groove 18 is formed from the main surface of the substrate in the deep P ₁ base region portion through the P ₁ region to reach the N-type region, and a passivation material (eg, SiO ₂ ) 19 is filled. Base electrode 16 in ohmic contact with P base region 14 and N ⁺ emitter region
And an emitter electrode 17 are provided.

Next, an example of the outline of the method for manufacturing the NPN transistor will be described with reference to the schematic sectional view of FIG. In FIG. 3A, an N-type semiconductor substrate 11 having an N ⁺ layer 12 and an N ⁻ layer 13 laminated is prepared. Next, in FIG. 2b, an oxide film is
21a is formed, a deep P ₁ region forming portion is opened, and, for example, boron-doped oxide is _deposited and diffused to form a P ₁ base region 14a having a depth X _jP1 of about 50 μm. Similarly, as shown in FIG. 3C, an oxide film 21b having an opening for forming a shallow P ₂ region is formed, and a boron-doped oxide 22 is deposited. P ₂ then at the (d) of FIG
The region 14b is diffused so that the predetermined depth X _jP2 becomes about 30 μm. As a result, the P base region 14 having a two-step structure _having the depths X _jP1 and X _jP2 is formed. Next, as shown in FIG. (E) P ₂
An N ⁺ emitter region 15 is provided in the region 14b so that a desired current amplification factor β can be obtained. Next, in FIG. (F), a deep P ₁
A mesa groove 18 is formed from the substrate main surface of the region 14a through the region to the N-type region of the substrate 11, the groove is filled with a passivation material made of, for example, SiO _2, and the base electrode 16 and the emitter electrode are formed by a known method. Form 17. After that, a semiconductor device as a product is manufactured by the conventional technique.

The transistor having the above structure, the diffusion depth of the N ⁺ emitter layer 15 and P ₂ base layer 14b is shallower, the base width W _B is also narrower, with good high-speed switching characteristic can be obtained, the base-collector exposed to the mesa groove Since the inter-junction end is provided at a deep position, even if a high reverse bias is applied to J _CB , its
The spread of the depletion layer of the P ₁ base layer does not reach the edge portion of the surface substrate, and the withstand voltage characteristic is significantly improved.

The effects of the present invention in this embodiment will be described below.
FIG. 3 is a diagram for explaining the effect of increasing the breakdown voltage. That is, the third
The figure shows the maximum collector-base voltage V _{CB0 with the} emitter open.
And the thickness of the N ^- collector region that mainly bears the breakdown voltage W _C
(See FIG. 8 and FIG. 2 (f)) FIG. The _mark X _{indicates the} conventional technique and the depth of the P base region X _jB.
In the case of 30 μm, the _{∘ mark} represents the case where the depth of the P base region is X _jP1 50 μm and X _jP2 30 μm in this embodiment. Effective I in which more transistors of the prior art W _C to about 100μm near
Layer ^- V _CB0 eliminates the correlation between the width W _C of the (N layers) whereas saturated, strong correlation with W _C in the embodiment of the present invention, V _CB0 also with increasing W _C The absolute value thereof increases and the absolute value thereof is higher than that of the conventional technique, and a significant effect of improving the withstand voltage is seen. In the transistor of the present invention, the value of W _C for obtaining a desired breakdown voltage characteristic can be set in a wide range.

FIG. 4 and FIG. 5 are diagrams showing the effect of improving the switching characteristics of the embodiment of the present invention. The vertical axis of FIG. 4 is the storage time t _stg (μs) of the time difference between the output waveform and the input waveform in the switching characteristics, and the horizontal axis is mainly determined by the minority carrier lifetime of the collector. Time τ _s (μs). The vertical axis of FIG. 5 represents the fall time (Fall timing) of the output waveform of the switching characteristic.
e) t _f (μs), and the horizontal axis represents the decreasing slope (−di _B ) / dt (A / μs) of the base current i _B. 4 and 5
In all of the figures, the mark x is the result when X _jB = 50 μm in the prior art, and the mark ◯ is the result when X _jP1 = 50 μm and X _jP2 = 30 μm in this embodiment. In FIG. 4, for the same τ _s value, in this embodiment, t
_{The stg} is short and the slope of the curve is relaxed, and the effect of improving the switching characteristics can be seen. Also in Figure 5 _{t f} pair (-di _B / dt)
In the curve, the minimum value of t _f is lowered in this embodiment as compared with the conventional technique, and the effect of improving the switching characteristics can be seen. Although the NPN transistor has been described in this embodiment, the present invention is not limited to the PNP transistor.
It can also be applied to high breakdown voltage diodes, etc., and has a wide range of uses.

[Effects of the Invention] The semiconductor device of the present invention is a mesa semiconductor device having high breakdown voltage and high switching characteristics, for example, in which a P region having a shallow deep two-step structure is formed on an N-type substrate and a mesa groove is formed in the deep P region portion. Since the PN junction end exposed to the mesa groove is located deeper than the substrate surface, the depletion layer spreads at the junction end at the time of reverse bias is hard to reach the substrate surface edge of the mesa groove. Withstand voltage is improved. Further, the active region of the device is mainly formed in the shallow P layer region portion, and its depth can be set to the optimum value for the high speed switching device.

Therefore, as can be seen from the effect of the NPN transistor of the above-mentioned embodiment, the present invention can provide a semiconductor device having both high breakdown voltage characteristics and high-speed switching characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device of FIG. 1, and FIGS. 3 to 5 are the present invention and the prior art. in comparison characteristic diagram of a semiconductor device, FIG. 3 is V _CB0 and W _C, Fig. 4 t _stg and tau _s, characteristic diagram showing the respective relationships Fig. 5 and t _f (-di _{B /} dt) FIG. 6 is a partially enlarged cross-sectional view for explaining the problems of the prior art, FIGS. 7 and 8 are cross-sectional views of a conventional semiconductor device, and FIG. 9 is a view for explaining the problems of the prior art. is there. 1, 11 ... N-type semiconductor substrate, 2, 12 ... N ⁺ collector region, 3, 13 ... N ^- collector region, 4A, 4B ... P base region, 5, 15 ... N ⁺ emitter region, 8 , 18 …… Mesa groove,
9, 19 ...... Passivation material filling the mesa groove, 10
... Depletion layer, 14 ... P-base region with shallow two-stage structure, 14a
...... Deep P ₁ base region part, 14b ・ ・ ・ Shallow P ₂ base region part, J _CB …… Collector-base junction.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an opposite conductivity type region selectively formed on one main surface side of the substrate and having a deep and shallow two-step structure from the main surface, and the deeply formed region. A mesa groove that extends from the main surface of the substrate of the opposite conductivity type region portion to the one conductivity type region of the substrate through the deeply formed opposite conductivity type region, and joins the one conductivity type region and the opposite conductivity type region Is exposed in the mesa groove at the bottom of the deeply formed opposite conductivity type region and the mesa groove is filled with a passivation material.