JPH0756072B2 - Method for manufacturing conductor pattern - Google Patents
Method for manufacturing conductor patternInfo
- Publication number
- JPH0756072B2 JPH0756072B2 JP62038965A JP3896587A JPH0756072B2 JP H0756072 B2 JPH0756072 B2 JP H0756072B2 JP 62038965 A JP62038965 A JP 62038965A JP 3896587 A JP3896587 A JP 3896587A JP H0756072 B2 JPH0756072 B2 JP H0756072B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- substrate
- ion implantation
- conductor
- adhesive strength
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/146—By vapour deposition
Landscapes
- Physical Vapour Deposition (AREA)
Description
【発明の詳細な説明】 〔概要〕 接着強度の優れた導体パターンの製法として、被処理基
板に真空蒸着とイオン注入を併用することによって蒸着
金属原子と基板構成物との混合物からなる導体パターン
を形成する方法。DETAILED DESCRIPTION OF THE INVENTION [Outline] As a method for producing a conductor pattern having excellent adhesive strength, a conductor pattern made of a mixture of vapor-deposited metal atoms and a substrate component is formed on a substrate to be processed by using vacuum vapor deposition and ion implantation in combination. How to form.
〔産業上の利用分野〕 本発明は密着強度の優れた導体パターンの製造方法に関
する。[Field of Industrial Application] The present invention relates to a method for producing a conductor pattern having excellent adhesion strength.
大量の情報を迅速に処理するため情報処理技術の進歩は
著しく、情報処理装置の主要部を構成する半導体装置は
単位素子の小形化による大容量化が進んでおり、これと
共に配線パターンの高密度化が行われている。Information processing technology has progressed remarkably in order to process a large amount of information quickly, and semiconductor devices that form the main part of information processing devices are becoming larger in capacity due to the miniaturization of unit elements. Is being implemented.
すなわち、従来のICやLSIよりも一段と大容量化したVLS
Iが実用化されており、また半導体素子に対するパッシ
ベーション技術の進歩によってセラミック回路基板に半
導体チップを直接にダイボンディングしたり、フリップ
チップボンディングすることが可能となった。In other words, VLS has a larger capacity than conventional ICs and LSIs.
I has been put to practical use, and advances in passivation technology for semiconductor devices have made it possible to directly die-bond or flip-chip bond a semiconductor chip to a ceramic circuit board.
ここで、半導体チップの周辺に設けられている端子数は
多く、セラミック基板上にはかゝる半導体チップが密に
搭載されているために配線パターンは高密度化し、必然
的に多層配線構造がとられている。Here, the number of terminals provided in the periphery of the semiconductor chip is large, and since such semiconductor chips are densely mounted on the ceramic substrate, the wiring pattern has a high density and inevitably has a multilayer wiring structure. It is taken.
次に、LSIやVLSIなどの半導体チップを構成する単位素
子の小形化により半導体チップの電力消費量は4W以上と
なっており、更に増加する傾向にある。Next, due to the miniaturization of unit elements that constitute a semiconductor chip such as LSI and VLSI, the power consumption of the semiconductor chip is 4 W or more, which tends to further increase.
そのため半導体チップの冷却法も従来の空冷或いは強制
空冷法に代わって液冷法が必要な趨性にある。Therefore, the cooling method of the semiconductor chip also has a tendency to require a liquid cooling method instead of the conventional air cooling or forced air cooling method.
多数の半導体チップを装着する回路基板はアルミナ（α
−Al2O3）など耐熱性セラミックスから構成され、この
上に厚膜法か薄膜法を用いて微細な配線パターンが形成
されている。A circuit board on which a large number of semiconductor chips are mounted is made of alumina (α
-Al 2 O 3 ) and other heat-resistant ceramics, on which a fine wiring pattern is formed by the thick film method or thin film method.
すなわち、厚膜法はセラミック基板上に金（Au）やパラ
ジウム・銀（Pd-Ag）などの導体ペーストをスクリーン
・プリントして配線パターンを作り、これを焼成する方
法であり、一方、薄膜法は真空蒸着法やスパッタ法を用
いて基板上に銅（Cu）などの導体金属膜を形成し、これ
に写真蝕刻技術（フォトリソグラフィ）を使用して配線
パターンを形成する方法である。That is, the thick film method is a method of screen-printing a conductor paste such as gold (Au) or palladium / silver (Pd-Ag) on a ceramic substrate to form a wiring pattern, and then firing the wiring pattern. Is a method of forming a conductive metal film such as copper (Cu) on a substrate by using a vacuum deposition method or a sputtering method, and forming a wiring pattern on the conductive metal film by using a photo-etching technique (photolithography).
然しながら、これらの方法は何れも問題点をもってい
る。However, all of these methods have problems.
すなわち、厚膜法により形成した導体パターンは基板と
の間に2Kg/mm2程度の接着強度をもっているが、この上
には半田付けができないと云う問題がある。That is, the conductor pattern formed by the thick film method has an adhesive strength of about 2 kg / mm 2 with the substrate, but there is a problem that soldering cannot be performed on this.
その理由として、厚膜導体ペーストは金属粉末を主体と
し、これにバインダとしてガラス粉末を加え、溶剤によ
り混合してペースト状としたものであり、スクリーン印
刷した後に焼成するとガラス粉末は溶融してアルミナ基
板に接着するため、比較的強い接着強度が得られるもの
ゝ、焼結した金属粉末の周囲にはガラスが存在するため
に半田付けを行っても半田が乗らず、またワイヤボンデ
ィングを行ってもそのままでは接着しない。The reason for this is that the thick-film conductor paste is mainly composed of metal powder, and glass powder is added as a binder to this, and mixed with a solvent to form a paste. Since it adheres to the substrate, relatively strong adhesive strength can be obtained.Since glass exists around the sintered metal powder, solder does not get on even if soldered, and even if wire bonding is performed. It does not adhere as it is.
一方、薄膜法により形成した導体パターンは半田付けや
溶接などが可能であるが、基板との接着強度は1Kg/mm2
程度と少なく、剥離が生じ易く信頼性に問題がある。On the other hand, the conductor pattern formed by the thin film method can be soldered or welded, but the adhesive strength with the substrate is 1 kg / mm 2
The degree is small, peeling easily occurs, and there is a problem in reliability.
さて、半導体チップを搭載したセラミック回路基板は先
に記したように電圧印加の有無により急熱と急冷があ
り、また冷媒中に浸漬して使用する場合もあるので、厚
膜法で形成した導体パターンよりも接着強度が大きく、
急熱急冷に耐え、また半田付け可能な導体パターンの形
成法が求められている。As described above, a ceramic circuit board with a semiconductor chip is subject to rapid heating and rapid cooling depending on the presence or absence of voltage application, and it may be immersed in a refrigerant for use. Greater adhesive strength than patterns,
There is a demand for a method of forming a conductor pattern that can withstand rapid heating and quenching and can be soldered.
以上記したように厚膜法で形成した導体パターンは半田
付けができず、また薄膜法で形成した導体パターンは接
着強度が不足し、温度サイクルにより基板との剥離が生
じ易い。As described above, the conductor pattern formed by the thick film method cannot be soldered, and the conductor pattern formed by the thin film method has insufficient adhesive strength, and is easily peeled from the substrate due to the temperature cycle.
そこで、接着強度が厚膜法による場合よりも強く、また
半田付け可能な導体パターン形成法を実用化することが
課題である。Therefore, it is an object to put into practical use a conductor pattern forming method which has a stronger adhesive strength than that of the thick film method and which can be soldered.
上記の問題は真空蒸着源を備えたイオン注入装置のター
ゲット部に金属マスクを被覆した被処理基板を装着し、
導体パターン形成金属の真空蒸着と加速した不活性ガス
イオンのイオン注入とを同時に行って、該被処理基板上
に導体金属原子と基板構成材料との混合物よりなるパタ
ーンを形成する導体パターンの製造方法により解決する
ことができる。The above problem is to mount a target substrate coated with a metal mask on the target portion of an ion implantation apparatus equipped with a vacuum deposition source,
Method for producing a conductor pattern in which a vacuum deposition of a conductor pattern forming metal and accelerated ion implantation of inert gas ions are simultaneously performed to form a pattern made of a mixture of conductor metal atoms and a substrate constituent material on the substrate to be processed. Can be solved by.
本発明は真空蒸着法とイオン注入法とを併用し、ことに
より蒸着金属を部分的に基板中にまで侵入させて混合物
を作ることにより、接着強度が高く、また半田付けや熔
着が可能な導体パターンを形成するものである。The present invention uses both the vacuum vapor deposition method and the ion implantation method, whereby the vapor-deposited metal partially penetrates into the substrate to form a mixture, so that the adhesive strength is high and soldering or welding is possible. A conductor pattern is formed.
然し、薄膜法で用いられているように被処理基板上に前
面に導体金属膜を形成した後、写真蝕刻して導体パター
ンを形成することは蒸着金属粒子が基板と混合体を形成
していることから不要部分の金属膜を完全に除去するこ
とは困難である。However, the conductive metal film is formed on the front surface of the substrate to be processed as used in the thin film method, and then the conductive pattern is formed by photo-etching so that the vapor-deposited metal particles form a mixture with the substrate. Therefore, it is difficult to completely remove the unnecessary metal film.
そこで、本発明においては金属マスクを用い、選択的に
蒸着とイオン注入を行うようにしたものである。Therefore, in the present invention, a metal mask is used to selectively perform vapor deposition and ion implantation.
イオン注入装置の中にCuの蒸着源を用意し、アルゴン
（Ar）イオンの注入を行うターゲット部にモリブデン
（Mo）製のマスクを被覆したアルミナ被処理基板を設置
した。A Cu vapor deposition source was prepared in an ion implanter, and an alumina-treated substrate coated with a molybdenum (Mo) mask was placed on a target portion for implanting argon (Ar) ions.
そして、設置内を10-4Pa以上にまで排気し、加速電圧20
KeVでアルミナ基板にArイオンのイオン注入を行いなが
らCuの真空蒸着を行った。Then, exhaust the inside of the installation to 10 -4 Pa or more, and accelerate the voltage to 20
Vacuum deposition of Cu was performed while Ar ion implantation was performed on the alumina substrate by KeV.
ここで、イオン注入と真空蒸着を併用するには10-4Pa以
上の真空度が必要であって、これ以下の真空度ではイオ
ン注入が行われなくなる。Here, in order to use both ion implantation and vacuum deposition, a vacuum degree of 10 -4 Pa or higher is required, and at a vacuum degree lower than this, ion implantation will not be performed.
また、イオン注入を行うには10KeV以上の加速電圧が必
要であって、これ以下ではスパッタが生じてしまい本発
明の実施には適さなくなる。In addition, an accelerating voltage of 10 KeV or higher is required to perform ion implantation, and if the accelerating voltage is lower than 10 KeV, sputtering will occur, which is not suitable for carrying out the invention.
このようにするとCuと基板との接合部には100〜1000Å
の混合層が形成されるために接着強度が向上し、また導
体パターンの表面層はCuからなるために従来の薄膜法に
より得られるものと同様であって、半田付けや熔着が可
能である。In this way, 100 to 1000Å at the joint between Cu and the substrate.
Since the mixed layer is formed, the adhesive strength is improved, and since the surface layer of the conductor pattern is made of Cu, it is the same as that obtained by the conventional thin film method and can be soldered or welded. .
このようにして得られた導体パターンは測定の結果、接
着強度は2.3Kg/mm2と厚膜法によるよりも優れた値を得
ることができた。As a result of the measurement of the conductor pattern thus obtained, the adhesive strength was 2.3 Kg / mm 2, which was superior to that obtained by the thick film method.
以上記したように本発明の使用により接着強度が従来の
厚膜法によるものよりも優れ、また半田付け可能な導体
パターンの形成が可能となる。As described above, by using the present invention, the adhesive strength is superior to that by the conventional thick film method, and it becomes possible to form a solderable conductor pattern.
フロントページの続き (72)発明者 今中 佳彦 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 坂井 強志 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 青木 重憲 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 昭60−100673（ＪＰ，Ａ)Front page continued (72) Inventor Yoshihiko Imanaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited (72) Inventor Takeshi Sakai 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Shigenori Aoki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (56) References JP-A-60-100673 (JP, A)
Claims (1)
ゲット部に金属マスクを被覆した被処理基板を装着し、
導体パターン形成金属の真空蒸着と加速した不活性ガス
イオンのイオン注入とを同時に行って、該被処理基板上
に導体金属原子と基板構成材料との混合物よりなるパタ
ーンを形成することを特徴とする導体パターンの製造方
法。1. A target substrate of an ion implantation apparatus equipped with a vacuum evaporation source is mounted with a target substrate coated with a metal mask,
Vacuum deposition of a conductor pattern forming metal and ion implantation of accelerated inert gas ions are performed simultaneously to form a pattern made of a mixture of conductor metal atoms and a substrate constituent material on the substrate to be processed. A method for manufacturing a conductor pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62038965A JPH0756072B2 (en) | 1987-02-20 | 1987-02-20 | Method for manufacturing conductor pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62038965A JPH0756072B2 (en) | 1987-02-20 | 1987-02-20 | Method for manufacturing conductor pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63206465A JPS63206465A (en) | 1988-08-25 |
| JPH0756072B2 true JPH0756072B2 (en) | 1995-06-14 |
Family
ID=12539875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62038965A Expired - Fee Related JPH0756072B2 (en) | 1987-02-20 | 1987-02-20 | Method for manufacturing conductor pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0756072B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60100673A (en) * | 1983-11-02 | 1985-06-04 | Mitsubishi Electric Corp | Formation of wiring pattern by masked vapor deposition |
| JPS61277118A (en) * | 1985-06-03 | 1986-12-08 | 株式会社日立製作所 | Conducting thin film and formation of conducting pattern |
-
1987
- 1987-02-20 JP JP62038965A patent/JPH0756072B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63206465A (en) | 1988-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |