JP3134234B2 - Metallized substrate and manufacturing method thereof - Google Patents
Metallized substrate and manufacturing method thereofInfo
- Publication number
- JP3134234B2 JP3134234B2 JP03316327A JP31632791A JP3134234B2 JP 3134234 B2 JP3134234 B2 JP 3134234B2 JP 03316327 A JP03316327 A JP 03316327A JP 31632791 A JP31632791 A JP 31632791A JP 3134234 B2 JP3134234 B2 JP 3134234B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- metallized substrate
- metallized
- powder composition
- wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は厚膜電子回路の導体層形
成及びセラミック基板上に実装された電子機器用素子，
部品等が動作することによって発生する熱を拡散するた
めの銅回路を形成するためのメタライズセラミックス基
板とこのメタライズセラミックス基板を製造する方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductor layer of a thick film electronic circuit and an element for electronic equipment mounted on a ceramic substrate.
The present invention relates to a metallized ceramic substrate for forming a copper circuit for diffusing heat generated by the operation of components and the like, and a method for manufacturing the metallized ceramic substrate.
【０００２】[0002]
【従来の技術】電子回路基板には，高絶縁性，機械的強
度，他の電子素子を劣化させないこと、金属導体と容易
に接合体となること，熱伝導率が大きいなどの性質が要
求されている。このような基板としては，アルミナ、窒
化物等のセラミックスがある。2. Description of the Related Art Electronic circuit boards are required to have properties such as high insulation properties, mechanical strength, not deteriorating other electronic elements, being easily joined with metal conductors, and having high thermal conductivity. ing. Examples of such a substrate include ceramics such as alumina and nitride.
【０００３】しかし，セラミックス単体では，電子機器
に用いられるトランジスタ，ダイオード，ＩＣ，ＬＳ
Ｉ，その他各種の電子部品を直接実装することができな
い。[0003] However, ceramics alone require transistors, diodes, ICs, and LSs used in electronic equipment.
I. Other electronic components cannot be directly mounted.
【０００４】そのため，セラミックス表面に金属化膜を
形成し，導体あるいは金属とを接合することにより，電
子回路を製造している。このセラミックス表面に金属化
膜を形成したものをメタライズ基板と呼ぶ。[0004] Therefore, an electronic circuit is manufactured by forming a metallized film on a ceramic surface and joining it with a conductor or a metal. The metalized film formed on the ceramic surface is called a metallized substrate.
【０００５】図３は従来のメタライズセラミックス基板
の半田付けによる金属片の接合状態を示す断面図であ
る。図３において，セラミックス基板１に，このセラミ
ックスに対して高い接合強度が得られるペースト状のメ
タライズ用金属粉末組成物２を必要な回路に印刷し，そ
の上のワイヤー結線部に金属片５´を半田６によって，
接合してメタライズ基板としている。このメタライズ基
板に，ＩＣ等の電子部品３がクリーム半田６により接合
され，金属片５´及び電子部品３間はワイヤー４のは半
田付けにより接続されている。尚，図中の符号４ａは接
続用の半田である。FIG. 3 is a cross-sectional view showing a state in which metal pieces are joined by soldering a conventional metallized ceramic substrate. In FIG. 3, a paste-like metallizing metal powder composition 2 having a high bonding strength with respect to the ceramic is printed on a ceramic substrate 1 on a required circuit, and a metal piece 5 'is placed on a wire connection portion thereon. By solder 6
Joined to form a metallized substrate. An electronic component 3 such as an IC is joined to the metallized substrate by cream solder 6, and a wire 4 is connected between the metal piece 5 'and the electronic component 3 by soldering. Note that reference numeral 4a in the drawing denotes a connecting solder.
【０００６】[0006]
【発明が解決しようとする課題】従来，電子回路を形成
したメタライズ金属粉末組成物上へのワイヤーによる直
接の結線は困難であり，ワイヤー結線部に金属片を半田
により接合し，その金属片にワイヤーを結線し回路を構
成していた。この場合，半導体電子部品を実装するため
の半田と金属片を結線部に接合させるための半田は，熱
抵抗の関係から組成が異なってくる。そのため，半田付
け温度及び雰囲気が異なることが有り，半田の選択が必
要になる。また，メタライズ用金属粉末組成物から形成
された金属化膜は，直径２５〜５０μｍのＡｕ線による
直接の結線は可能であるが，大電流を流す必要の有る場
合に使用されるような２５０μｍ以上のＡｌ，Ｃｕ線に
よる直接結線は困難であった。Conventionally, it has been difficult to directly connect a metal piece to a metallized metal powder composition on which an electronic circuit has been formed, using a wire. Wires were connected to form a circuit. In this case, the composition of the solder for mounting the semiconductor electronic component and the solder for joining the metal piece to the connection portion differ from each other due to the relationship of thermal resistance. Therefore, the soldering temperature and the atmosphere may be different, and it is necessary to select the solder. Further, the metallized film formed from the metallizing metal powder composition can be directly connected with an Au wire having a diameter of 25 to 50 μm, but it is more than 250 μm used when a large current needs to flow. It was difficult to directly connect the Al and Cu wires.
【０００７】そこで，本発明の技術的課題は，半田の選
択及び直径２５０μｍ以上のＡｌ，Ｃｕ線による結線を
容易にすることができるメタライズ基板及びメタライズ
基板の製造方法を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a metallized substrate and a method for manufacturing the metallized substrate, which can facilitate selection of solder and connection with Al and Cu wires having a diameter of 250 μm or more.
【０００８】[0008]
【課題を解決するための手段】本発明によれば，チップ
部品を搭載して，Ａｌ又はＣｕからなるワイヤーによる
配線を行うセラミックスと金属粉末組成物とからなるメ
タライズ基板において，前記金属粉末組成物は，Ｃｕを
７０〜９５重量％，残部がＴｉからなり、前記ワイヤー
の結線部に金属片を有し、前記金属片はメタライズ用金
属粉末組成物のメタライズ温度より融点の高Ｃｕ，Ａ
ｇ，Ｆｅ，Ａｕの内の少なくとも一種であることを特徴
とするメタライズ基板が得られる。According to the present invention, there is provided a metallized substrate comprising a ceramic and a metal powder composition on which a chip component is mounted and which is wired by a wire made of Al or Cu . Replaces Cu
70 to 95% by weight, with the balance being Ti , having a metal piece at the wire connection portion , wherein the metal piece is metallizing metal.
Cu, A having a melting point higher than the metallizing temperature of the metal powder composition
A metallized substrate characterized by at least one of g, Fe and Au is obtained.
【０００９】本発明によれば，前記メタライズ基板，前
記金属片は少なくとも２層に積層されていることを特徴
とする用いるメタライズ基板が得られる。According to the present invention, there is provided a metallized substrate used in which the metallized substrate and the metal pieces are laminated in at least two layers.
【００１０】[0010]
【００１１】[0011]
【００１２】本発明によれば，チップ部品を搭載して，
Ａｌ又はＣｕからなるワイヤーによる配線を行うセラミ
ックスと金属粉末組成物とからなるメタライズ基板を製
造する方法において，前記金属粉末組成物として，Ｃｕ
を７０〜９５重量％，残部がＴｉからなる金属粉末組成
物を用い、前記ワイヤーの結線部の接合に金属片を用
い、前記金属片は前記金属粉末組成物のメタライズ温度
より融点の高Ｃｕ，Ａｇ，Ｆｅ，Ａｕの内の少なくとも
一種であることを特徴とするメタライズ基板の製造方法
が得られる。According to the present invention, a chip component is mounted,
In a method of manufacturing a metallized substrate made of a ceramic and a metal powder composition for wiring with a wire made of Al or Cu , the metal powder composition may be made of Cu
Powder composition consisting of 70 to 95% by weight, with the balance being Ti
A metal piece is used for joining the connection portion of the wire , and the metal piece is a metallizing temperature of the metal powder composition.
At least one of Cu, Ag, Fe, and Au having a higher melting point
A method for manufacturing a metallized substrate, which is a kind, is obtained.
【００１３】本発明によれば，前記メタライズ基板の製
造方法において，前記ワイヤー接合の際，前記金属粉末
組成物を塗布するときに，ワイヤーの接続部に前記金属
片を付けて同時にメタライズ焼成を行い接合させること
を特徴とするメタライズ基板の製造方法が得られる。According to the present invention, in the method of manufacturing a metallized substrate, when the metal powder composition is applied at the time of the wire bonding, the metal piece is attached to a connecting portion of the wire, and metallization firing is performed simultaneously. A method for manufacturing a metallized substrate characterized by joining is obtained.
【００１４】本発明によれば，前記したいずれかのメタ
ライズ基板の製造方法において，前記金属片として少な
くとも２層を有する積層金属片を用いることを特徴とす
るメタライズ基板の製造方法が得られる。According to the present invention, there is provided a method for manufacturing a metallized substrate according to any one of the above-described methods for manufacturing a metallized substrate, wherein a laminated metal piece having at least two layers is used as the metal piece.
【００１５】[0015]
【００１６】[0016]
【００１７】ここで，本発明のセラミックス基板とし
て，窒素化合物，例えば，ＡｌＮやＳｉ3 Ｎ4 及び酸化
物，例えばＡｌ2 Ｏ3 等あるいは数％の焼結助剤を含む
セラミックス焼結体が適用できるが，これらに限定され
るものではない。Here, as the ceramic substrate of the present invention, a ceramic sintered body containing a nitrogen compound, for example, AlN or Si 3 N 4 and an oxide, for example, Al 2 O 3 or a sintering aid of several percent is applied. Yes, but not limited to.
【００１８】[0018]
【実施例】以下，本発明の実施例について図面を参照し
て説明する。図１は本発明の実施例に係るメタライズ基
板を示す平面図である。図１において，セラミックス基
板１にセラミックスに対して高い接合強度が得られるペ
ースト状のメタライズ用金属粉末組成物２を所望する回
路パターンとなるように印刷し，他の回路結線部に金属
片５を形成してメタライズ基板１０としている。このメ
タライズ基板１０上にＩＣ等による電子部品３が設けら
れ，金属片５とがワイヤー４によって，半田４ａで接続
されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a metallized substrate according to an embodiment of the present invention. In FIG. 1, a paste-like metallizing metal powder composition 2 having a high bonding strength to ceramics is printed on a ceramic substrate 1 so as to have a desired circuit pattern, and a metal piece 5 is attached to another circuit connection portion. The metallized substrate 10 is formed. An electronic component 3 such as an IC is provided on the metallized substrate 10, and the metal piece 5 is connected to the metal piece 5 by a wire 4 by a solder 4 a.
【００１９】図２は図１のメタライズ基板の断面図であ
る。図２において，メタライズ用金属粉末組成物２と電
子部品３の接着は，クリーム半田６によって行われ，金
属片５は，メタライズ用金属粉末組成物２上には，Ａｇ
片７，ワイヤー４との結線表面はＣｕ片８との積層され
て構成されている。FIG. 2 is a sectional view of the metallized substrate of FIG. In FIG. 2, the bonding between the metallizing metal powder composition 2 and the electronic component 3 is performed by a cream solder 6, and the metal piece 5 is made of Ag on the metallizing metal powder composition 2.
The connection surface with the piece 7 and the wire 4 is formed by laminating with the Cu piece 8.
【００２０】次に，図１及び図２を参照して本発明の実
施例のメタライズ基板を製造する方法について説明す
る。まず，メタライズ用金属粉末組成物は，重量％表示
で主成分のＣｕは、７０〜９５％，Ｔｉは５〜３０％の
組成を有するように，夫々平均粒径１〜１０μｍの微粉
末を秤量し混合を行い，次に，ビヒクルを添加混合し
て，三本のロールミル等を用いて十分混練し、均一に分
散させ，スクリーン印刷に適した粘度に調整しペースト
状とした。更に，バインダーとして，アクリル系樹脂な
ど通常用いられているものを混合した。このメタライズ
用金属粉末組成物をＡｌＮからなるセラミックス基板１
に塗布し，形成されたメタライズ組成物回路上に，Ｃｕ
片８とＡｇ片７との積層金属片であるクラッド材からな
る金属片５をワイヤー４のボンディングによる結線部と
して設け，高真空雰囲気中乃至不活性ガス雰囲気中にお
いて熱処理を施した。Next, a method of manufacturing a metallized substrate according to an embodiment of the present invention will be described with reference to FIGS. First, the metal powder composition for metallization is weighed to have a composition of 70 to 95% of Cu and 5 to 30% of Ti in terms of% by weight. Then, the vehicle was added and mixed, and the mixture was sufficiently kneaded using three roll mills or the like, uniformly dispersed, adjusted to a viscosity suitable for screen printing, and formed into a paste. Further, a commonly used binder such as an acrylic resin was mixed as the binder. The metal powder composition for metallization is applied to a ceramic substrate 1 made of AlN.
On the metallized composition circuit formed and
A metal piece 5 made of a clad material, which is a laminated metal piece of the piece 8 and the Ag piece 7, was provided as a connection portion by bonding the wire 4, and heat treatment was performed in a high vacuum atmosphere or an inert gas atmosphere.
【００２１】尚，このメタライズ用金属粉末組成物２上
にＣｕ粉末組成物を塗布することもできるが，このＣｕ
粉末組成物は，上記メタライズ用金属粉末組成物と同様
の方法によって作られたペースト状のものとすることが
できる。また，金属片５は，セラミックス基板１に塗布
したペーストとの接着性が高く，メタライズ用金属粉末
組成物の熱処理温度より融点の高いものとするため，及
び結線に使用されるワイヤーの材質を考慮してＣｕ，Ａ
ｕ，とＡｇ単体及びこれらの金属を２層以上に形成した
ものを用いた。このようにメタライズ用金属粉末組成物
を使用し，金属片５を接合したために，セラミックス基
板に対して高い接合強度が得られ，回路形成の結線が容
易にすることができる。It is to be noted that a Cu powder composition can be applied on the metallizing metal powder composition 2.
The powder composition can be in the form of a paste prepared by the same method as the metal powder composition for metallization. The metal piece 5 has a high adhesiveness to the paste applied to the ceramic substrate 1 and has a melting point higher than the heat treatment temperature of the metal powder composition for metallization, and the material of the wire used for connection is taken into consideration. And Cu, A
u, Ag alone and those formed of these metals in two or more layers were used. Since the metal pieces 5 are joined by using the metal powder composition for metallization as described above, high joining strength can be obtained with respect to the ceramic substrate, and connection for forming a circuit can be facilitated.
【００２２】[0022]
【発明の効果】以上説明したように，本発明によれば，
半導体電子部品の半田付けのみとなり，半田の選択の必
要がなくなり，半田の選択及び直径２５０μｍ以上のＡ
ｌ，Ｃｕ線による結線を容易にするための金属片の接合
の問題を解決することができ，工程を簡略化したメタラ
イズ基板及びその製造方法を提供することができる。As described above, according to the present invention,
Only the soldering of semiconductor electronic components is required, and the selection of solder is not required.
It is possible to solve the problem of joining metal pieces for facilitating the connection using the l and Cu wires, and to provide a metallized substrate with a simplified process and a method for manufacturing the same.
【図１】本発明の実施例に係るメタライズ基板の平面図
である。FIG. 1 is a plan view of a metallized substrate according to an embodiment of the present invention.
【図２】図１のメタライズ基板の断面図である。FIG. 2 is a cross-sectional view of the metallized substrate of FIG.
【図３】従来のメタライズ基板の一例を示す断面図であ
る。FIG. 3 is a sectional view showing an example of a conventional metallized substrate.
１ セラミックス基板 ２ メタライズ用金属粉末組成物 ３ 電子部品 ４ ワイヤー ５，５´ 金属片 ６ クリーム半田 REFERENCE SIGNS LIST 1 ceramic substrate 2 metal powder composition for metallizing 3 electronic component 4 wire 5,5 ′ metal piece 6 cream solder
フロントページの続き (56)参考文献 特開 昭59−161096（ＪＰ，Ａ) 特開 昭63−56996（ＪＰ，Ａ) 特開 昭62−197376（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 1/09 H01L 23/12 H05K 3/32 H05K 3/38 H05K 7/20 Continuation of the front page (56) References JP-A-59-161096 (JP, A) JP-A-63-56996 (JP, A) JP-A-62-197376 (JP, A) (58) Fields studied (Int .Cl. 7 , DB name) H05K 1/09 H01L 23/12 H05K 3/32 H05K 3/38 H05K 7/20
Claims (5)
らなるワイヤーによる配線を行うセラミックスと金属粉
末組成物とからなるメタライズ基板において，前記金属粉末組成物は，Ｃｕを７０〜９５重量％，残部
がＴｉからなり、 前記ワイヤーの結線部に金属片を有し、前記金属片はメ
タライズ用金属粉末組成物のメタライズ温度より融点の
高Ｃｕ，Ａｇ，Ｆｅ，Ａｕの内の少なくとも一種である
ことを特徴とするメタライズ基板。Claims 1. A chip component is mounted, and Al or Cu
In a metallized substrate composed of a ceramic and a metal powder composition for wiring with a metal wire, the metal powder composition contains 70 to 95% by weight of Cu, with the balance being Cu.
Is made of Ti, and has a metal piece at a connection portion of the wire.
Melting point of metallizing temperature
A metallized substrate characterized in that it is at least one of high Cu, Ag, Fe, and Au .
て，前記金属片は少なくとも２層に積層されていること
を特徴とする用いるメタライズ基板。2. A metallized substrate according to claim 1, wherein said metal pieces are laminated in at least two layers.
らなるワイヤーによる配線を行うセラミックスと金属粉
末組成物とからなるメタライズ基板を製造する方法にお
いて，前記金属粉末組成物として，Ｃｕを７０〜９５重
量％，残部がＴｉからなる金属粉末組成物を用い、前記
ワイヤーの結線部の接合に金属片を用い、前記金属片は
前記金属粉末組成物のメタライズ温度より融点の高Ｃ
ｕ，Ａｇ，Ｆｅ，Ａｕの内の少なくとも一種であること
を特徴とするメタライズ基板の製造方法。3. A method for mounting a chip component on an Al or Cu chip .
In a method of manufacturing a metallized substrate composed of a ceramic and a metal powder composition for performing wiring by a wire comprising
The amount%, a metal powder composition and the balance of Ti, the metal pieces used for joining connecting portion of the wire, the metal strip
High C having a melting point higher than the metallizing temperature of the metal powder composition
A method for manufacturing a metallized substrate, wherein at least one of u, Ag, Fe, and Au is used.
法において，前記ワイヤー接合の際，前記金属粉末組成
物を塗布するときに，ワイヤーの接続部に前記金属片を
付けて同時にメタライズ焼成を行い接合させることを特
徴とするメタライズ基板の製造方法。4. The method for manufacturing a metallized substrate according to claim 3 , wherein said metal piece is attached to a connection portion of a wire and metallized and baked simultaneously when said metal powder composition is applied during said wire bonding. A method for manufacturing a metallized substrate, characterized by joining.
製造方法において，前記金属片として少なくとも２層を
有する積層金属片を用いることを特徴とするメタライズ
基板の製造方法。5. The method for manufacturing a metallized substrate according to claim 3 , wherein a laminated metal piece having at least two layers is used as said metal piece.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03316327A JP3134234B2 (en) | 1991-11-29 | 1991-11-29 | Metallized substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03316327A JP3134234B2 (en) | 1991-11-29 | 1991-11-29 | Metallized substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05152696A JPH05152696A (en) | 1993-06-18 |
| JP3134234B2 true JP3134234B2 (en) | 2001-02-13 |
Family
ID=18075898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03316327A Expired - Fee Related JP3134234B2 (en) | 1991-11-29 | 1991-11-29 | Metallized substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3134234B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5482257B2 (en) * | 2010-02-05 | 2014-05-07 | 三菱マテリアル株式会社 | Power module substrate with identification symbol and method for manufacturing the same |
-
1991
- 1991-11-29 JP JP03316327A patent/JP3134234B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05152696A (en) | 1993-06-18 |
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