JP3252743B2 - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JP3252743B2 JP3252743B2 JP4502897A JP4502897A JP3252743B2 JP 3252743 B2 JP3252743 B2 JP 3252743B2 JP 4502897 A JP4502897 A JP 4502897A JP 4502897 A JP4502897 A JP 4502897A JP 3252743 B2 JP3252743 B2 JP 3252743B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- external connection
- connection
- circuit board
- ceramic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明はセラミックス回路基
板に関し、より詳細にはＬＳＩ等の電子部品を搭載する
セラミックス回路基板に関する。The present invention relates to a ceramic circuit board, and more particularly, to a ceramic circuit board on which electronic components such as an LSI are mounted.
【０００２】[0002]
【従来の技術】ＬＳＩ等の電子部品を搭載するセラミッ
クス回路基板として従来から汎用されているアルミナ多
層回路基板は、その焼成温度が１５５０℃前後と高いた
め、内部導体に融点の高いＷやＭｏ等を用いる必要があ
る。しかし、これらＷやＭｏは比抵抗が大きいため、前
記アルミナ多層回路基板内における信号の伝送損失が大
きくなる。また、アルミナの比誘電率（εr ）は、通
常、８〜１０と大きいことから、信号遅延が大きくな
る。2. Description of the Related Art Alumina multilayer circuit boards, which have been widely used as ceramic circuit boards on which electronic parts such as LSIs are mounted, have a high firing temperature of about 1550 ° C., so that the internal conductor has a high melting point such as W and Mo. Must be used. However, since W and Mo have large specific resistance, signal transmission loss in the alumina multilayer circuit board becomes large. Further, the relative dielectric constant (ε r ) of alumina is usually as large as 8 to 10, so that the signal delay increases.
【０００３】最近の電子機器における信号処理の高速化
にともない、多層回路基板内において生じる信号の伝送
損失や信号遅延が大きな問題となってきており、伝送損
失や信号遅延が小さい多層回路基板が求められている。With the recent increase in the speed of signal processing in electronic equipment, transmission loss and signal delay of signals occurring in a multilayer circuit board have become a serious problem, and a multilayer circuit board with small transmission loss and signal delay has been demanded. Have been.
【０００４】このような背景から、近年、比誘電率が低
く、低温で軟化焼結するガラスをその成分とするガラス
セラミックス回路基板が注目されている。前記ガラスセ
ラミックス回路基板は、９５０℃以下の焼成温度で緻密
化させることができるため、比抵抗が小さく、伝送損失
の小さいＡｇ、Ｃｕ、Ａｕ、Ａｇ−Ｐｄ合金等を使用す
ることができ、また、これらの金属は比誘電率も小さい
ため、配線の信号遅延を小さくすることができる等の種
々の利点を有する。[0004] From such a background, in recent years, a glass-ceramic circuit board containing a glass having a low relative dielectric constant and softening and sintering at a low temperature as a component thereof has attracted attention. Since the glass-ceramic circuit board can be densified at a firing temperature of 950 ° C. or less, Ag, Cu, Au, an Ag—Pd alloy having a low specific resistance and a small transmission loss can be used, and Since these metals also have a small relative dielectric constant, they have various advantages such as a reduction in signal delay of wiring.
【０００５】一般に、ガラスセラミックス回路基板は以
下の方法により製造される。Generally, a glass ceramic circuit board is manufactured by the following method.
【０００６】まず、ガラス材料と骨材と呼ばれる無機材
料との混合粉末に樹脂（バインダ）、有機溶剤等を添加
してスラリを調製し、このスラリを用いてドクタブレー
ド法等によりグリーンシートを作製する。First, a slurry is prepared by adding a resin (binder), an organic solvent, and the like to a mixed powder of a glass material and an inorganic material called an aggregate, and a green sheet is prepared using the slurry by a doctor blade method or the like. I do.
【０００７】次に、このグリーンシートに必要によりパ
ンチング等の加工処理を施した後、Ａｇ等の導体を主成
分とする導体ペーストを用いてその表面に所定パターン
の導体ペースト層を形成し、ビアホールに導体ペースト
を充填する。Next, the green sheet is subjected to a processing such as punching as necessary, and then a conductor paste layer having a predetermined pattern is formed on the surface thereof using a conductor paste mainly composed of a conductor such as Ag, thereby forming a via hole. Is filled with a conductive paste.
【０００８】次に、これらの処理が施されたグリーンシ
ートを積層、熱圧着させてグリーンシート積層体を形成
し、空気中で脱脂、焼成した後、必要によりメッキ処理
等を施し、ガラスセラミックス回路基板を完成させる。
一旦、焼成により内部導体層のみを有するガラスセラミ
ックス板を製造した後、その表面に導体ペースト層を形
成し、焼き付け等の処理を施し、その表面に外部接続用
パッド等を形成する方法もある。Next, the green sheets subjected to these treatments are laminated and thermocompression-bonded to form a green sheet laminate, degreased and fired in the air, and then subjected to a plating treatment or the like, if necessary, to obtain a glass ceramic circuit. Complete the substrate.
There is also a method in which a glass-ceramic plate having only an internal conductor layer is once manufactured by baking, and then a conductor paste layer is formed on the surface of the glass ceramic plate, baking or the like is performed, and external connection pads and the like are formed on the surface.
【０００９】図２は上記方法により製造されたガラスセ
ラミックス回路基板の一例として、フリップチップ回路
基板を模式的に示した断面図である。FIG. 2 is a sectional view schematically showing a flip-chip circuit board as an example of a glass ceramic circuit board manufactured by the above method.
【００１０】ガラスセラミックス層１８の表面には、Ｃ
ｕ、Ａｇ−Ｐｄ合金等、比抵抗の小さい金属からなる外
部接続用パッド１１、及び表面導体層１６が形成され、
これらの表面にＮｉメッキ層２２が形成されている。半
導体素子搭載面２３側においては、このＮｉメッキ層２
２で被覆された外部接続用パッド１１と、半導体素子１
７に形成されたパッド１７ａとが接続用半田ボール１３
を介して接続されている。また、マザーボード搭載面２
４側においても、Ｎｉメッキ層２２で被覆された外部接
続用パッド１１に接続用半田ボール１３が溶融、接着さ
れている。一方、ガラスセラミックス層１８の内部には
内部導体層１４及びビア１５が形成され、内部導体層１
４はビア１５を介してそれぞれ表面の外部接続用パッド
１１や表面導体層１６に接続されている。On the surface of the glass ceramic layer 18, C
u, an external connection pad 11 made of a metal having a small specific resistance such as an Ag-Pd alloy, and a surface conductor layer 16 are formed;
A Ni plating layer 22 is formed on these surfaces. On the semiconductor element mounting surface 23 side, the Ni plating layer 2
2 and an external connection pad 11 covered with
7 are connected to the solder balls 13 for connection.
Connected through. Also, motherboard mounting surface 2
Also on the fourth side, the connection solder balls 13 are melted and bonded to the external connection pads 11 covered with the Ni plating layer 22. On the other hand, the inner conductor layer 14 and the via 15 are formed inside the glass ceramic layer 18, and the inner conductor layer 1 is formed.
4 are connected to the external connection pads 11 and the surface conductor layer 16 on the surface via the vias 15, respectively.
【００１１】このフリップチップ回路基板２０におい
て、マザーボード（図示せず）等の他の装置との接続
は、Ｎｉメッキ層２２で被覆された外部接続用パッド１
１及び接続用半田ボール１３を介して行われており、接
続用半田ボール１３として、通常は、金属との濡れ性に
優れ、かつ安価なＰｂ−Ｓｎ半田が使用されている。In this flip-chip circuit board 20, connection with other devices such as a motherboard (not shown) is performed by connecting external connection pads 1 covered with a Ni plating layer 22.
1 and the connection solder ball 13, and as the connection solder ball 13, an inexpensive Pb—Sn solder having excellent wettability with metal is usually used.
【００１２】[0012]
【発明が解決しようとする課題】外部接続用パッド１１
の表面にＮｉメッキ層２２が形成されているのは、以下
のような理由による。すなわち、前記Ｐｂ−Ｓｎ半田の
Ｓｎ成分は外部接続用パッド１１を構成するＣｕやＡｇ
−Ｐｄ合金と反応し易いので、接続用半田ボール１３を
外部接続用パッド１１に直接溶融、接着させた場合、フ
リップチップ回路基板２０が装備された電子機器が動作
し、半導体素子１７が発熱して高温状態になると、外部
接続パッド１１と接続用半田ボール１３との接続界面に
おいて反応が進行し、金属間化合物が生成される。その
結果、外部接続パッド１１と接続用半田ボール１３との
接続界面が脆化し、接続の信頼性を維持できなくなる。SUMMARY OF THE INVENTION Pad for external connection 11
The Ni plating layer 22 is formed on the surface for the following reason. That is, the Sn component of the Pb-Sn solder is composed of Cu or Ag constituting the external connection pad 11.
Since it easily reacts with the -Pd alloy, if the connection solder ball 13 is directly melted and adhered to the external connection pad 11, the electronic device equipped with the flip-chip circuit board 20 operates and the semiconductor element 17 generates heat. When the temperature becomes high, the reaction proceeds at the connection interface between the external connection pad 11 and the connection solder ball 13, and an intermetallic compound is generated. As a result, the connection interface between the external connection pad 11 and the connection solder ball 13 becomes brittle, and the reliability of the connection cannot be maintained.
【００１３】そこで、このような外部接続パッド１１と
接続用半田ボール１３との接続界面における反応を防止
するため、外部接続用パッド１１の表面に、Ｎｉメッキ
層２２が形成されているのである。Therefore, in order to prevent such a reaction at the connection interface between the external connection pad 11 and the connection solder ball 13, the Ni plating layer 22 is formed on the surface of the external connection pad 11.
【００１４】しかし、外部接続用パッド１１にＮｉメッ
キ処理を施す場合、高価なメッキ処理装置やメッキ液が
必要となり、そのためにセラミックス回路基板の製造コ
ストが高くなるという課題があった。However, when the external connection pads 11 are subjected to Ni plating, an expensive plating apparatus and a plating solution are required, which causes a problem that the manufacturing cost of the ceramic circuit board is increased.
【００１５】また、メッキ液によりガラス成分が浸食さ
れてガラスセラミックス層１８が劣化し、バッドの密着
強度が低下するという課題もあった。Further, there is another problem that the glass component is eroded by the plating solution and the glass ceramic layer 18 is deteriorated, and the adhesion strength of the pad is reduced.
【００１６】本発明は上記課題に鑑みなされたものであ
り、接続用Ｓｎ含有半田を介して外部との接続が行われ
る形式のセラミックス回路基板において、外部接続用パ
ッド表面に、前記接続用Ｓｎ含有半田や外部接続用パッ
ドとの密着性に優れ、かつ前記接続用Ｓｎ含有半田と外
部接続用パッドとの反応を阻止することができる層が形
成された、接続信頼性が高く、安価なセラミックス回路
基板を提供することを目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in a ceramic circuit board of a type in which connection to the outside is made via a Sn-containing solder for connection, a surface of the pad for external connection includes the Sn-containing solder for connection. A highly reliable and inexpensive ceramic circuit having a layer having excellent adhesion to solder and external connection pads and having a layer capable of preventing a reaction between the connection Sn-containing solder and the external connection pads. It is intended to provide a substrate.
【００１７】[0017]
【課題を解決するための手段及びその効果】上記目的を
達成するために本発明に係るセラミックス回路基板
（１）は、接続用Ｓｎ含有半田を介して外部との接続が
行われる形式のセラミックス回路基板において、該セラ
ミックス回路基板がガラスセラミックス回路基板であ
り、ＣｕあるいはＡｇ−Ｐｄ合金により形成された外部
接続用パッドが前記接続用Ｓｎ含有半田よりＳｎ含有量
が少なく、かつ融点の高い半田層により被覆されている
ことを特徴としている。In order to achieve the above object, a ceramic circuit board (1) according to the present invention comprises a ceramic circuit of a type in which connection to the outside is made via a Sn-containing solder for connection. In the substrate, the ceramic
The mixed circuit board is a glass ceramic circuit board
In addition, an external connection pad formed of Cu or Ag-Pd alloy is covered with a solder layer having a lower Sn content and a higher melting point than the connection Sn-containing solder.
【００１８】[0018]
【００１９】上記セラミックス回路基板（１）によれ
ば、前記半田層は前記接続用Ｓｎ含有半田よりＳｎ含有
量が少ないので、前記半田層が前記外部接続用パッドと
反応しにくい。また、前記半田層の融点が前記接続用Ｓ
ｎ含有半田の融点より高いので、前記半田層で被覆され
た前記外部接続用パッドに前記接続用Ｓｎ含有半田を溶
融・接着させる際に、前記半田層が溶融して前記接続用
Ｓｎ含有半田と混和せず、前記半田層で前記外部接続用
パッドを被覆した状態が保たれる。そのため、セラミッ
クス回路基板と他の装置、部品、素子等とを接続した後
も、前記外部接続用パッドに接着している前記半田層は
Ｓｎ含有量の少ない半田であり、搭載された半導体素子
が動作して前記セラミックス回路基板が高温になった際
も、前記外部接続用パッドと前記半田層とが反応しにく
く、前記外部接続用パッドの脆化を防止することができ
る。また、前記半田層は前記外部接続用パッド及び前記
接続用Ｓｎ含有半田との密着性に優れるため、前記外部
接続用パッドと前記接続用Ｓｎ含有半田との密着強度を
大きく保つことができる。According to the ceramic circuit board (1), the solder layer has a smaller Sn content than the connection Sn-containing solder, so that the solder layer hardly reacts with the external connection pads. Further, the melting point of the solder layer is equal to the S
Since the melting point of the n-containing solder is higher than the melting point of the solder, the solder layer is melted when the solder for connection is melted and bonded to the external connection pad covered with the solder layer. Without mixing, the state where the external connection pads are covered with the solder layer is maintained. Therefore, even after the ceramic circuit board is connected to another device, component, element, or the like, the solder layer adhered to the external connection pad is a solder having a small Sn content, and the mounted semiconductor element is not used. Even when the ceramic circuit board becomes hot due to the operation, the external connection pads and the solder layer hardly react with each other, and the external connection pads can be prevented from becoming brittle. Further, since the solder layer has excellent adhesion to the external connection pad and the connection Sn-containing solder, the adhesion strength between the external connection pad and the connection Sn-containing solder can be kept large.
【００２０】また、本発明に係るセラミックス回路基板
（２）は、上記セラミックス回路基板（１）において、
前記接続用Ｓｎ含有半田がＳｎを５９〜６５重量％含有
するＰｂ−Ｓｎ半田からなり、前記半田層がＳｎを１〜
１９重量％含有するＰｂ−Ｓｎ半田からなることを特徴
としている。Further, the ceramic circuit board ( 2 ) according to the present invention is characterized in that in the ceramic circuit board (1),
The connection Sn-containing solder is made of Pb-Sn solder containing Sn in an amount of 59 to 65% by weight, and the solder layer contains Sn in an amount of 1 to 5.
It is characterized by being made of Pb-Sn solder containing 19% by weight.
【００２１】上記セラミックス回路基板（２）によれ
ば、前記半田層のＳｎ含有量が１〜１９重量％であるの
で、前記外部接続用パッドと反応しない。また、前記接
続用Ｓｎ含有半田と前記半田層とが同じ種類の半田から
なるので、より密着性に優れている。他方、Ｓｎ含有量
の違いから両者の融点の差は大きく、前記半田層は高融
点なので、前記半田層で被覆された外部接続用パッドに
前記接続用Ｓｎ含有半田を溶融・接続する際に、前記半
田層が溶融して前記接続用Ｓｎ含有半田と混和せず、前
記半田層で前記外部接続用パッドを被覆した状態が保た
れる。そのため、セラミックス回路基板と他の装置、部
品、素子等とを接続した後も、前記外部接続用パッドに
接着している前記半田層はＳｎ含有量の少ない半田であ
り、搭載された半導体素子が動作して前記セラミックス
回路基板が高温になった際も、前記外部接続用パッドと
前記半田層とが反応しにくく、前記外部接続用パッドの
脆化を防止することができる。According to the ceramic circuit board ( 2 ), since the Sn content of the solder layer is 1 to 19% by weight, it does not react with the external connection pads. Further, since the connection Sn-containing solder and the solder layer are made of the same kind of solder, the adhesion is more excellent. On the other hand, the melting point difference between the two is large due to the difference in the Sn content, and since the solder layer has a high melting point, when melting and connecting the connection Sn-containing solder to an external connection pad covered with the solder layer, The solder layer is melted and does not mix with the connection Sn-containing solder, so that the external connection pad is covered with the solder layer. Therefore, even after the ceramic circuit board is connected to another device, component, element, or the like, the solder layer adhered to the external connection pad is a solder having a small Sn content, and the mounted semiconductor element is not used. Even when the ceramic circuit board becomes hot due to the operation, the external connection pads and the solder layer hardly react with each other, and the external connection pads can be prevented from becoming brittle.
【００２２】[0022]
【発明の実施の形態】以下、本発明に係るセラミックス
回路基板の実施の形態を説明する。実施の形態に係るセ
ラミックス回路基板の構成材料は特に限定されるもので
はないが、外部接続用パッドとして使用されるＣｕ、又
はＡｇ−Ｐｄ合金とＰｂ−Ｓｎ半田との反応が問題にな
る場合に特に有効であることから、ガラスセラミックス
が主たる対象となる。また、セラミックス回路基板の種
類としては、ボールグリッドアレイ（ＢＧＡ）タイプや
フリップチップ接続を行う基板を主たる対象としてい
る。従って、以下においては、ガラスセラミックスから
なるフリップチップ回路基板を例にとって説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the ceramic circuit board according to the present invention will be described. The constituent material of the ceramic circuit board according to the embodiment is not particularly limited. However, when a reaction between Cu or an Ag-Pd alloy used as an external connection pad and Pb-Sn solder becomes a problem. Particularly effective is glass ceramics. In addition, as a type of the ceramic circuit board, a ball grid array (BGA) type or a board for performing flip chip connection is mainly targeted. Therefore, in the following, a flip-chip circuit board made of glass ceramics will be described as an example.
【００２３】図１は、実施の形態に係るセラミックス回
路基板を模式的に示した断面図である。実施の形態に係
るセラミックス回路基板（フリップチップ回路基板）１
０は、外部接続用パッド１１がＮｉメッキ層２２ではな
く、半田層１２により被覆されている他は、従来の図２
に示したフリップチップ回路基板２０と同様に構成され
ている。従って、ここでは外部接続用パッド１１及び半
田層１２に関する事項についてのみ説明する。FIG. 1 is a sectional view schematically showing a ceramic circuit board according to the embodiment. Ceramic circuit board (flip chip circuit board) 1 according to the embodiment
0 indicates that the external connection pad 11 is covered with the solder layer 12 instead of the Ni plating layer 22.
Has the same configuration as the flip-chip circuit board 20 shown in FIG. Therefore, only the matters relating to the external connection pads 11 and the solder layers 12 will be described here.
【００２４】フリップチップ回路基板１０に形成された
外部接続用パッド１１は、通常、低温で焼成することが
できる低抵抗のＣｕやＡｇ−Ｐｄ合金等の金属により構
成されており、この外部接続用パッド１１は半田層１２
により被覆されている。半田層１２は、外部との接続を
行う接続用半田ボール１３（接続用Ｓｎ含有半田）より
Ｓｎ含有量が少なく、かつ融点が高い半田により形成さ
れている。The external connection pads 11 formed on the flip chip circuit board 10 are usually made of a low-resistance metal such as Cu or Ag-Pd alloy which can be fired at a low temperature. The pad 11 is a solder layer 12
Coated with The solder layer 12 is formed of solder having a lower Sn content and a higher melting point than the connection solder balls 13 (connection Sn-containing solder) for connection to the outside.
【００２５】通常、接続用半田ボール１３等の接続用Ｓ
ｎ含有半田としては、Ｐｂ−Ｓｎ半田が用いられてお
り、このＰｂ−Ｓｎ半田はＳｎ含有量が６３重量％の共
晶組成を境として、Ｓｎ含有量が少なくなるに従い融点
が上昇する。そして、Ｓｎ含有量が６３〜１９重量％の
範囲においては、固相線が共晶組成の融点と同じである
ため、半田層として使用することができないが、Ｓｎの
含有量が１９重量％以下の組成では固相線が共晶組成の
融点より高いので、半田層として使用することができ
る。また、Ｓｎ含有量が６３重量％の半田はＣｕやＡｇ
−Ｐｄ合金等と反応し易いが、Ｓｎの含有量が１９重量
％以下の高融点半田はＣｕやＡｇ−Ｐｄ合金等と殆ど反
応しない。Normally, the connection S such as the solder ball 13 for connection is used.
As the n-containing solder, Pb-Sn solder is used, and the melting point of the Pb-Sn solder increases as the Sn content decreases with respect to a eutectic composition having a Sn content of 63% by weight. When the Sn content is in the range of 63 to 19% by weight, the solidus cannot be used as a solder layer because the melting point of the eutectic composition is the same, but the Sn content is 19% by weight or less. In the above composition, the solidus line is higher than the melting point of the eutectic composition, so that it can be used as a solder layer. Further, the solder having the Sn content of 63% by weight is made of Cu or Ag.
Although high-melting-point solder having a Sn content of 19% by weight or less hardly reacts with Cu, Ag-Pd alloy or the like.
【００２６】そこで、フリップチップ回路基板１０にお
ける接続用半田ボール１３の形成に、Ｓｎを６３重量％
程度含有し、その融点が１８３℃のＰｂ−Ｓｎ半田を使
用し、半田層１２を構成する半田としては、Ｓｎ含有量
が１〜１９重量％で、その融点が２７５〜３２５℃の半
田を使用することが望ましい。In order to form the solder balls 13 for connection on the flip-chip circuit board 10, 63% by weight of Sn was used.
Pb-Sn solder having a melting point of 183 ° C. is used, and a solder having a Sn content of 1 to 19% by weight and a melting point of 275 to 325 ° C. is used as the solder constituting the solder layer 12. It is desirable to do.
【００２７】ただし、接続用Ｓｎ含有半田のＳｎ含有量
を５９〜６５重量％としても、半田層１２のＳｎ含有量
を少なめに設定することにより、上記した本発明の効果
を奏することができる。However, even if the Sn content of the connection Sn-containing solder is set to 59 to 65% by weight, the above-described effect of the present invention can be obtained by setting the Sn content of the solder layer 12 to a small value.
【００２８】外部接続用パッド１１上に形成する半田層
１２の厚みは３０〜３００μｍ程度が好ましい。半田層
１２の厚みが３０μｍ以下では、半田付けの際又はその
後の使用中に接続用半田ボール１３のＳｎ成分が外部接
続用パッド１１まで達して反応し、他方、半田層１２の
厚みを３００μｍ以上に設定することは経済的でない。The thickness of the solder layer 12 formed on the external connection pads 11 is preferably about 30 to 300 μm. If the thickness of the solder layer 12 is 30 μm or less, the Sn component of the connection solder ball 13 reaches the external connection pad 11 and reacts during soldering or during subsequent use, while the thickness of the solder layer 12 is 300 μm or more. Setting it to is not economic.
【００２９】上記構成のフリップチップ回路基板１０に
電子部品の端子等を接続する場合には、接続用半田ボー
ル１３の溶融温度を、接続用半田ボール１３の融点より
も高く、半田層１２を構成する半田の固相線より低い温
度とする。When connecting the terminals of the electronic components to the flip-chip circuit board 10 having the above-described configuration, the melting temperature of the connection solder balls 13 is higher than the melting point of the connection solder balls 13 so that the solder layer 12 is formed. Temperature lower than the solidus of the solder to be soldered.
【００３０】接続用半田ボール１３の溶融温度を上記条
件に設定することにより、半田付けの際に半田層１２が
接続用半田ボール１３に溶解することはなく、半田付け
後も外部接続用パッド１１が半田層１２により被覆され
ているため、接続用半田ボール１３と外部接続用パッド
１１との反応を阻止し、外部接続用パッド１１と半田層
１２との界面の脆化を防止することができる。By setting the melting temperature of the connection solder ball 13 to the above condition, the solder layer 12 does not dissolve in the connection solder ball 13 at the time of soldering and the external connection pad 11 Is covered with the solder layer 12, the reaction between the connection solder ball 13 and the external connection pad 11 is prevented, and embrittlement at the interface between the external connection pad 11 and the solder layer 12 can be prevented. .
【００３１】次に、実施の形態に係るフリップチップ回
路基板１０の製造方法を説明する。本実施の形態に係る
フリップチップ回路基板１０の製造方法は、外部接続用
パッド１１上に半田層１２を形成する工程を除いて、従
来のセラミックス基板の製造方法と同様である。Next, a method of manufacturing the flip-chip circuit board 10 according to the embodiment will be described. The method of manufacturing the flip-chip circuit board 10 according to the present embodiment is the same as the conventional method of manufacturing a ceramic substrate except for the step of forming the solder layer 12 on the external connection pads 11.
【００３２】例えば、ＭｇＯ−ＳｉＯ2 −Ａｌ2 Ｏ3 系
ガラス粉末と、アルミナ粉末とを配合した粉末に、バイ
ンダ、溶剤、可塑剤等を添加して混合することにより、
スラリを調製し、このスラリを用いてドクターブレード
法等によりグリーンシートを作製する。For example, by adding a binder, a solvent, a plasticizer and the like to a powder obtained by mixing an MgO—SiO 2 —Al 2 O 3 system glass powder and an alumina powder, and mixing them.
A slurry is prepared, and a green sheet is prepared using the slurry by a doctor blade method or the like.
【００３３】次に、グリーンシートを所定のサイズに切
断し、必要によりパンチング等の加工処理を施し、Ｃｕ
やＡｇ−Ｐｄ合金等の金属を含む導体ペーストの塗布や
充填等を行った後、積層、熱圧着してグリーンシート積
層体を作製する。Next, the green sheet is cut into a predetermined size, and if necessary, processing such as punching is performed.
After applying or filling a conductive paste containing a metal such as a metal and an Ag-Pd alloy, a green sheet laminate is produced by laminating and thermocompression bonding.
【００３４】前記工程の後、空気中、８５０〜９５０℃
で１０分〜１０時間焼成し、内部に内部導体層１４及び
ビア１５が形成され、その表面に外部接続用パッド１１
や表面導体層１６が形成されたガラスセラミックス基板
を製造する。After the above step, in air, 850-950 ° C.
For 10 minutes to 10 hours to form the internal conductor layer 14 and the via 15 inside, and the external connection pads 11
A glass ceramic substrate on which the surface conductor layer 16 is formed is manufactured.
【００３５】上記工程において、グリーンシート積層体
の表面には、外部接続用パッド１１を形成するための導
体ペースト層を印刷せず、焼成によりガラスセラミック
ス基板を製造した後、表面に内部導体層を構成する金属
とは別の金属を含む導体ペースト層を印刷し、熱処理を
施して外部接続用パッド１１を形成してもよい。In the above process, a conductive paste layer for forming the external connection pads 11 is not printed on the surface of the green sheet laminate, and a glass ceramic substrate is manufactured by firing. The external connection pad 11 may be formed by printing a conductive paste layer containing a metal different from the constituent metal and performing heat treatment.
【００３６】この後、外部接続用パッド１１を有するガ
ラスセラミックス基板を、Ｓｎ含有量が１〜１９重量％
のＰｂ−Ｓｎ半田浴槽に浸漬し、外部接続用パッド１１
表面に半田層１２を形成し、セラミックス回路基板（フ
リップチップ回路基板）１０の製造を完了する。ただ
し、外部との接続に使用されない表面導体層１６は必ず
しも半田層１２により被覆されていなくてもよい。Thereafter, the glass-ceramic substrate having the external connection pads 11 was replaced with a Sn content of 1 to 19% by weight.
Dipped in a Pb-Sn solder bath, and
The solder layer 12 is formed on the surface, and the manufacture of the ceramic circuit board (flip chip circuit board) 10 is completed. However, the surface conductor layer 16 not used for connection to the outside need not necessarily be covered with the solder layer 12.
【００３７】上記実施の形態においては、接続用半田ボ
ール１３と接続される外部接続用パッド１１について説
明したが、外部接続用パッド１１は上記実施の形態に示
したものに限定されず、半田を介して外部と接続される
パッドであれば、どのような種類のパッドであってもよ
いことは勿論である。In the above embodiment, the external connection pad 11 connected to the connection solder ball 13 has been described. However, the external connection pad 11 is not limited to the one shown in the above embodiment. Of course, any kind of pad may be used as long as the pad is connected to the outside through the pad.
【００３８】[0038]
【実施例及び比較例】以下、本発明の実施例に係るセラ
ミックス回路基板を説明する。また、比較例として、外
部接続用パッド１１表面に半田層１２を形成しないセラ
ミックス回路基板を用い、実施例の場合と同様の方法で
評価を行った。Examples and Comparative Examples Hereinafter, ceramic circuit boards according to examples of the present invention will be described. As a comparative example, a ceramic circuit board in which the solder layer 12 was not formed on the surface of the external connection pad 11 was used, and evaluation was performed in the same manner as in the example.
【００３９】（１）セラミックス回路基板の製造条件 ＜実施例１＞ (i) グリーシートの作製 固形分中の各粉末の組成 ガラス粉末：５０重量部、アルミナ粉末：５０重量部、
固形分中の粉末の平均粒径：１〜５μｍ グリーンシートの厚み：２００μｍ (ii)導体ペースト層の形成 金属粉末の種類 Ａｇ−Ｐｄ（Ａｇ：８０，Ｐｄ：２０（重量％）） 導体ペースト層の厚み：２０μｍ 導体ペーストパターンの形状：焼成収縮後に２ｍｍ×２
ｍｍの寸法となる正方形 (iii) 焼成 焼成雰囲気：大気雰囲気 焼成条件：９００℃、３０分 (iv) 半田層１２の形成 ３３０℃に保持された、Ｓｎを１０重量％含有するＰｂ
−Ｓｎ半田浴槽に、焼成後のガラスセラミックス基板を
５秒間浸漬し、外部接続用パッド１１上に半田層１２を
形成した。半田層１２の厚みは１５０μｍであった。(1) Manufacturing conditions of ceramic circuit board <Example 1> (i) Preparation of grease sheet Composition of each powder in solid content Glass powder: 50 parts by weight, alumina powder: 50 parts by weight,
Average particle size of powder in solid content: 1 to 5 µm Thickness of green sheet: 200 µm (ii) Formation of conductive paste layer Kind of metal powder Ag-Pd (Ag: 80, Pd: 20 (% by weight)) Conductive paste layer Thickness: 20 μm Conductor paste pattern shape: 2 mm × 2 after firing shrinkage
(iii) Sintering Sintering atmosphere: air atmosphere Sintering conditions: 900 ° C., 30 minutes (iv) Formation of solder layer 12 Pb containing 10% by weight of Sn kept at 330 ° C.
The fired glass ceramic substrate was immersed in a Sn solder bath for 5 seconds to form a solder layer 12 on the external connection pad 11. The thickness of the solder layer 12 was 150 μm.
【００４０】＜実施例２＞グリーンシート上に導体ペー
スト層を形成しなかった他は、実施例１の場合と同様の
条件でグリーンシートを作製して焼成した。得られたガ
ラスセラミックス基板表面にＣｕ粉末と微量のガラスフ
リットとを含有する導体ペーストを印刷し、窒素雰囲気
中、９００℃、１０分の条件で焼き付け、２ｍｍ×２ｍ
ｍのＣｕからなる外部接続用パッド１１を形成した。Example 2 A green sheet was prepared and fired under the same conditions as in Example 1 except that no conductive paste layer was formed on the green sheet. A conductor paste containing Cu powder and a small amount of glass frit was printed on the surface of the obtained glass ceramic substrate and baked in a nitrogen atmosphere at 900 ° C. for 10 minutes, 2 mm × 2 m
An external connection pad 11 made of m Cu was formed.
【００４１】その後は、実施例１の場合と同様に、外部
接続用パッド１１上に半田層１２を形成した。Thereafter, the solder layer 12 was formed on the external connection pads 11 as in the case of the first embodiment.
【００４２】＜比較例１＞半田層１２を形成しなかった
他は、実施例１の場合と同様にセラミックス回路基板を
製造した。Comparative Example 1 A ceramic circuit board was manufactured in the same manner as in Example 1 except that the solder layer 12 was not formed.
【００４３】＜比較例２＞半田層１２を形成しなかった
他は、実施例２の場合と同様にセラミックス回路基板を
製造した。Comparative Example 2 A ceramic circuit board was manufactured in the same manner as in Example 2 except that the solder layer 12 was not formed.
【００４４】（２）製造されたセラミックス回路基板の
評価 半田層１２により被覆された外部接続用パッド１１（実
施例）、及び半田層１２により被覆されていない外部接
続用パッド１１（比較例）に、２５０℃で溶融したＳｎ
含有量が６３重量％のＰｂ−Ｓｎ半田を用いて直径０．
６ｍｍのＳｎメッキＣｕ線を固定した。(2) Evaluation of the manufactured ceramic circuit board The external connection pads 11 covered by the solder layer 12 (Example) and the external connection pads 11 not covered by the solder layer 12 (Comparative example) , Sn melted at 250 ° C
A Pb-Sn solder having a content of 63% by weight has a diameter of 0.
A 6-mm Sn-plated Cu wire was fixed.
【００４５】次に、前記Ｃｕ線が固定されたセラミック
ス回路基板を１５０℃の恒温槽に５００〜１０００時間
放置する前及びした後、ピール強度を測定し、密着性の
評価を行った。Next, before and after the ceramic circuit substrate to which the Cu wire was fixed was left in a thermostat at 150 ° C. for 500 to 1000 hours, the peel strength was measured to evaluate the adhesion.
【００４６】ピール強度の測定は、引張試験機によりＣ
ｕ線を垂直上方に１０ｍｍ／分の速度で引っ張ることに
より行い、破断したときの強度をピール強度とした。サ
ンプル数は一実施例又は一比較例につき１６個とし、ピ
ール強度としてその平均値をとった。The peel strength was measured using a tensile tester.
The u-line was pulled vertically upward at a rate of 10 mm / min, and the strength at break was defined as the peel strength. The number of samples was 16 for one example or one comparative example, and the average value was taken as the peel strength.
【００４７】実施例１〜２、及び比較例１〜２に係るセ
ラミックス回路基板の評価結果を下記の表１に示す。The evaluation results of the ceramic circuit boards according to Examples 1 and 2 and Comparative Examples 1 and 2 are shown in Table 1 below.
【００４８】[0048]
【表１】 [Table 1]
【００４９】上記表１に示した結果からも明らかなよう
に、実施例１及び２に係るセラミックス回路基板におい
ては、５００時間経過後、又は１０００時間経過後もピ
ール強度に殆ど変化が生じておらず、外部接続用パッド
１１上に形成された半田層１２（Ｓｎ含有量：１０重量
％）が外部接続用パッド１１及び接続用Ｓｎ含有半田
（Ｓｎ含有量：６３重量％）との密着性に優れ、かつ１
５０℃の高温下に長時間晒された場合においてもその密
着性を低下させず、外部接続用パッド１１及び接続用Ｓ
ｎ含有半田との反応を進行させず、接続用Ｓｎ含有半田
と外部接続用パッド１１との接続界面が脆化しないこと
が実証された。As is clear from the results shown in Table 1, the peel strength of the ceramic circuit boards according to Examples 1 and 2 hardly changed even after 500 hours or 1000 hours. In addition, the solder layer 12 (Sn content: 10% by weight) formed on the external connection pad 11 has improved adhesion to the external connection pad 11 and the connection Sn-containing solder (Sn content: 63% by weight). Excellent and 1
Even when exposed to a high temperature of 50 ° C. for a long time, the adhesion is not reduced, and the external connection pad 11 and the connection S
It was demonstrated that the reaction with the n-containing solder did not proceed and the connection interface between the connection Sn-containing solder and the external connection pad 11 did not become brittle.
【００５０】一方、比較例１及び２に係るセラミックス
回路基板の場合には、５００時間経過後、及び１０００
時間経過後のいずれの場合にも、密着性が大きく低下し
ており、外部接続用パッド１１が半田層１２により被覆
されていない場合、１５０℃の高温下に長時間晒される
ことにより、外部接続用パッド１１と接続用Ｓｎ含有半
田との反応が進行し、接続用Ｓｎ含有半田と外部接続用
パッド１１との接続界面が脆化することが証明された。On the other hand, in the case of the ceramic circuit boards according to Comparative Examples 1 and 2, after 500 hours,
In any case after the lapse of time, the adhesion is greatly reduced. If the external connection pad 11 is not covered with the solder layer 12, the external connection pad 11 is exposed to a high temperature of 150 ° C. for a long time, and the external connection It has been proved that the reaction between the connection pad 11 and the connection Sn-containing solder proceeds, and that the connection interface between the connection Sn-containing solder and the external connection pad 11 becomes brittle.
【図１】本発明の実施の形態に係るセラミックス回路基
板を模式的に示した断面図である。FIG. 1 is a cross-sectional view schematically showing a ceramic circuit board according to an embodiment of the present invention.
【図２】従来のセラミックス回路基板を模式的に示した
断面図である。FIG. 2 is a cross-sectional view schematically showing a conventional ceramic circuit board.
１０ セラミックス回路基板（フリップチップ回路基
板） １１ 外部接続用パッド １２ 半田層 １３ 接続用半田ボール（接続用Ｓｎ含有半田）Reference Signs List 10 ceramic circuit board (flip chip circuit board) 11 pad for external connection 12 solder layer 13 solder ball for connection (Sn-containing solder for connection)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 伊東 拓二 大阪府大阪市中央区北浜４丁目５番33号 住友金属工業株式会社内 (56)参考文献 特開 平９−92685（ＪＰ，Ａ) 特開 平10−163241（ＪＰ，Ａ) 特開 平８−316366（ＪＰ，Ａ) 特開 平５−190552（ＪＰ，Ａ) 実開 平５−90954（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 H05K 3/24 H05K 3/34 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takuji Ito 4-5-33 Kitahama, Chuo-ku, Osaka-shi, Osaka Sumitomo Metal Industries, Ltd. (56) References JP-A-9-92685 (JP, A) JP-A-10-163241 (JP, A) JP-A-8-316366 (JP, A) JP-A-5-190552 (JP, A) JP-A-5-90954 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/60 H05K 3/24 H05K 3/34
Claims (2)
続が行われる形式のセラミックス回路基板において、該セラミックス回路基板がガラスセラミックス回路基板
であり、 ＣｕあるいはＡｇ−Ｐｄ合金により形成された 外部接続
用パッドが前記接続用Ｓｎ含有半田よりＳｎ含有量が少
なく、かつ融点の高い半田層により被覆されていること
を特徴とするセラミックス回路基板。1. A ceramic circuit board of a type in which connection to the outside is made via a connection Sn-containing solder, wherein the ceramic circuit board is a glass ceramic circuit board.
, And the ceramic circuit board, characterized in that it is covered by small Sn content than the external connection pads formed Sn-containing solder the connection by Cu or Ag-Pd alloy, and a high melting point solder layer .
６５重量％含有するＰｂ−Ｓｎ半田からなり、前記半田
層がＳｎを１〜１９重量％含有するＰｂ−Ｓｎ半田から
なることを特徴とする請求項１記載のセラミックス回路
基板。2. The method according to claim 2, wherein the connection-use Sn-containing solder has a Sn content of 59 to
2. The ceramic circuit board according to claim 1, wherein the ceramic circuit board is made of Pb-Sn solder containing 65% by weight, and the solder layer is made of Pb-Sn solder containing 1 to 19% by weight of Sn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4502897A JP3252743B2 (en) | 1997-02-28 | 1997-02-28 | Ceramic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4502897A JP3252743B2 (en) | 1997-02-28 | 1997-02-28 | Ceramic circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10242334A JPH10242334A (en) | 1998-09-11 |
| JP3252743B2 true JP3252743B2 (en) | 2002-02-04 |
Family
ID=12707889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4502897A Expired - Lifetime JP3252743B2 (en) | 1997-02-28 | 1997-02-28 | Ceramic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3252743B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040052050A (en) * | 2002-12-13 | 2004-06-19 | 엘지전자 주식회사 | bare IC mounting method |
| JP2008091874A (en) * | 2006-09-08 | 2008-04-17 | Alps Electric Co Ltd | Ceramic circuit substrate and method for manufacturing the same |
-
1997
- 1997-02-28 JP JP4502897A patent/JP3252743B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10242334A (en) | 1998-09-11 |
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