JPH075582Y2 - Audio transmission data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a demodulation device for audio transmission data, and more particularly to a demodulation device for audio transmission data such as a demodulation system of a digital I / O interface of a digital audio device.

[Conventional technology]

The demodulation system of the digital I / O interface of the digital audio equipment inputs audio transmission data (digital audio interface signal) based on the digital I / O format from the outside and demodulates the audio sample data contained in this audio transmission data. , To the D / A converter to form an analog audio signal.

An example of a conventional digital I / O interface demodulation system is shown in FIG.

The audio transmission data input to the digital input / output terminal D is first input to the clock reproduction unit 10 and the clock synchronized with the clock component included in the audio transmission data is reproduced.

Then, the audio transmission data is input to the signal demodulator 12 according to the clock reproduced by the clock reproducing unit 10, and the audio sample data is demodulated.

The audio sample data demodulated by the signal demodulator 12 is output to the D / A converter 14 and converted into an analog audio signal.

Here, if there is jitter in the output of the audio sample data from the signal demodulator 12, the audio signal output from the D / A converter 14 will be distorted, resulting in deterioration of sound quality.

For this reason, conventionally, as shown in FIG.
10 is a double self-synchronized reproduction clock circuit.

That is, the audio transmission data is first input to the frame synchronization signal detection circuit 16 to detect the frame synchronization signal and output as the frame synchronization detection signal.

The frame synchronization detection signal is input to the first PLL circuit 18, and the first clock that synchronizes with the clock component of the frame synchronization signal and follows the voice transmission data is reproduced.

Since the first clock reproduced by the first PLL circuit 18 contains the jitter following the voice transmission data,
The second clock that is input to the second PLL circuit 20 and absorbs the jitter is reproduced.

Since the signal demodulator 12 performs input of voice transmission data and demodulation and output of analog sample data according to the second clock, the jitter of the output data is reduced to some extent and the D / A
The waveform distortion in the converter 14 can be suppressed to some extent.

[Problems to be solved by the device]

However, in the above-mentioned conventional technique, when a large jitter occurs in the audio transmission data, the timing of the clock reproduced by the second PLL circuit 20 is not synchronized, and erroneous data is input to the signal demodulator 12. There is a risk that

Therefore, conventionally, the second PLL circuit 20 cannot be narrowed sufficiently, and the waveform distortion generated in the audio signal after D / A conversion cannot be sufficiently suppressed.

In view of the above problems of the prior art, the present invention has an object of providing a demodulator for audio transmission data capable of outputting accurate audio sample data with almost no jitter.

Another object of the present invention is a voice transmission data demodulating device for further reducing jitter.

Another object of the present invention is to demodulate audio transmission data, in which the jitter is extremely reduced even when the demodulation system is provided with a digital filter.

[Means for Solving the Problems]

The device for demodulating voice transmission data according to the present invention comprises a first PLL circuit for outputting a clock synchronized with the voice transmission data, and a VCX.
A narrow band second PLL circuit that outputs a clock synchronized with the clock output from the first PLL circuit including O, and voice transmission data is written according to the clock output from the first PLL circuit; A time base collector that reads audio transmission data according to a clock output from the second PLL circuit, and an audio sample from audio transmission data read from the time base collector according to a clock output from the second PLL circuit. And a demodulator for demodulating data.

Another audio transmission data demodulation device according to the present invention comprises a first PLL circuit for outputting a clock synchronized with the audio transmission data and an audio sample data from the audio transmission data according to a clock output from the first PLL circuit. A demodulator that performs demodulation and forms a clock that is synchronized with the output of audio sample data; and a narrowband second PLL circuit that includes a VCXO and that outputs a clock that is synchronized with the clock output from the demodulator, The audio transmission data is written according to the clock output from the demodulator,
And a time base collector for reading audio transmission data according to a clock output from the PLL circuit.

According to still another aspect of the present invention, there is provided a demodulator for audio transmission data, comprising: a first PLL circuit that outputs a clock synchronized with the audio transmission data; and audio sample data from the audio transmission data according to the clock output by the first PLL circuit. In addition to demodulating the audio sample data, a demodulator that forms a clock synchronized with the output of the audio sample data and a predetermined data conversion process are performed on the audio audio sample data according to the clock output from the demodulator. A narrowband second PLL circuit including a digital filter forming a clock synchronized with the output and a VCXO and outputting a clock synchronized with the clock output by the digital filter, and the digital filter according to the clock output by the digital filter The audio sample data output from the filter is written. And a time base collector for reading audio sample data according to a clock output from the second PLL circuit.

〔Example〕

Next, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing a demodulation system of a digital I / O interface according to the present invention.

Audio transmission data (digital audio interface signal) according to a predetermined transmission format (digital I / O format) is input to the digital input / output terminal D.

A clock reproducing section 30 is connected to the digital input / output terminal D, and a clock synchronized with the audio transmission data is reproduced.

The clock reproducing section 30 has a frame synchronization signal detection circuit 32 connected to the digital input / output terminal D, detects the frame synchronization signal in the audio transmission data, and outputs the frame synchronization detection signal.

The first PLL circuit 34 is connected to the output side of the frame synchronization signal detection circuit 32, and the first clock of a predetermined frequency synchronized with the frame synchronization detection signal is reproduced.

The frame synchronization signal detection circuit 32 and the first PLL circuit 34
Clock recovery circuit is formed.

A second PLL circuit 36 as a second clock recovery circuit is connected to the output side of the first PLL circuit 34.
A second clock is reproduced in synchronization with the clock output from the circuit 34.

The first PLL circuit 34 has a relatively wide band and forms a first clock that follows the jitter of the voice transmission data.

On the other hand, the second PLL circuit 36 is a VCXO using a crystal oscillator.
(Not shown) and has a relatively narrow band.

The second PLL circuit 36 forms a second clock in which the jitter is sufficiently absorbed from the first clock.

The output sides of the first clock and the second clock of the clock regenerator 30 are connected to the write clock input terminal and the read clock input terminal of the time base collector 38.

The data input terminal of the time base collector 38 is connected to the digital input / output terminal D, and the time base collector 38 outputs the audio transmission data bit by bit in the internal RA according to the first clock input to the write clock input terminal.
The audio transmission data written in the RAM is written bit by bit in accordance with the second clock input to the read clock input terminal and is output to the outside.

Since the audio transmission data is written to the time base collector 38 by the first clock that follows the audio transmission data, it can be accurately performed without causing a data error.

On the other hand, since the voice transmission data is read from the time base collector 38 by the second clock having almost no jitter, the voice transmission data having almost no jitter is output.

A signal demodulator 40 is connected to the output side of the time base collector 38 and the output side of the second clock of the clock reproducing section 30.

The signal demodulator 40 receives the audio transmission data output from the time base collector 38 according to the second clock and demodulates the audio sample data.

Since the output of the audio sample data from the signal demodulator 40 is performed according to the clock formed from the second clock, jitter hardly occurs.

A D / A converter 42 is connected to the output side of the signal demodulator 40 to convert the audio sample data into an analog audio signal.

Here, since the audio sample data output from the signal demodulator 40 has almost no jitter, waveform distortion hardly occurs in the audio signal after D / A conversion, and good sound quality can be obtained.

According to this embodiment, the time base collector 38 is provided in the preceding stage of the signal demodulator 40, and the constraint of the read clock with respect to the write clock of the time base collector 38 is minimized. A PLL having a narrow band response characteristic from the first clock is reproduced by reproducing the first clock that follows the jitter of the transmission data and accurately writing the audio transmission data in the time base collector 38 according to the first clock. The circuit 36 reproduces the second clock which has sufficiently absorbed the jitter, and according to the second clock, the voice transmission data is read from the time base collector 38 with almost no jitter and the signal demodulator 40 is accurately read.
The audio demodulator 40 can output accurate audio sample data with little jitter.

Therefore, waveform distortion does not occur in the audio signal after D / A conversion,
Good sound quality can be obtained.

Since a VCXO including a crystal oscillator can be used for the second PLL circuit 36, a circuit configuration with little spurious and high stability can be realized.

In the above-mentioned embodiment, the time base collector 38 is RA
Although the configuration includes M, the configuration may include a register.

Next, a second embodiment of this invention will be described with reference to FIG.

The second embodiment shows a case where the time base collector is provided in the front stage side of the signal demodulator in the first embodiment, whereas it is provided in the rear stage side of the signal demodulator.

A clock reproducing section 50 as a first clock reproducing circuit is connected to the digital input / output terminal D, and a clock synchronized with the audio transmission data is reproduced.

The clock reproduction unit 50 has a frame synchronization signal detection circuit 52 connected to the digital input / output terminal D, detects the frame synchronization signal in the audio transmission data, and outputs the frame synchronization detection signal.

The first PLL circuit 54 is connected to the output side of the frame synchronization signal detection circuit 52, and the first clock of a predetermined frequency synchronized with the frame synchronization detection signal is reproduced.

The first PLL circuit 54 has a relatively wide band and forms the first clock that follows the jitter of the voice transmission data.

A signal demodulator 56 is connected to the digital input / output terminal D and the first clock output side of the clock recovery unit 50.

The signal demodulator 56 receives the audio transmission data received from the outside according to the first clock, demodulates the audio sample data, and synchronizes with the output of the audio sample data (LRCK, WCK, BCK, etc.). To form.

Since the first clock follows the jitter of the voice transmission data received from the outside, the signal demodulator 56 can perform an accurate demodulation operation.

However, the audio sample data and the clock output from the signal demodulator 56 have jitter that is synchronized with each other, but that is caused by the jitter of the first clock and the jitter generated without the signal demodulator 56. .

Of the clocks output by the signal demodulator 56, for example, the clock
The LRCK is input to a second PLL circuit (including a frequency dividing circuit that divides the frequency of the clock LRCK) 58 as a second clock reproducing circuit, and the second clock having the same frequency as the clock BCK is reproduced.

The second PLL circuit 58 includes a VCXO (not shown) using a crystal oscillator, and has a relatively narrow band.

The second PLL circuit 59 forms a second clock with the same frequency as the clock BCK and with sufficient jitter absorbed.

The clock BCK output terminal of the signal demodulator 56 and the second PLL circuit 58
The output side of is connected to the write clock input terminal and the read clock input terminal of the time base collector 60.

The data input terminal of the time base collector 60 is a signal demodulator
The time base collector 60 is connected to the 56 data output terminals, and the audio sample data is written to the internal RAM bit by bit according to the clock BCK input to the write clock input terminal and is also input to the read clock input terminal. According to the second clock, the audio sample data written in the RAM is read bit by bit and output to the outside.

The writing of the audio sample data to the time base collector 60 is performed by the clock BCK synchronized with the audio sample data output performed by the signal demodulator 56, so that it is accurately performed without causing a data error.

On the other hand, since the audio sample data is read from the time base collector 60 by the second clock having almost no jitter, the audio sample data having almost no jitter is output.

A D / A converter 62 is connected to the output side of the time base collector 60 to convert audio sample data into an analog audio signal.

Here, since the audio sample data output from the time base collector 60 has little jitter, waveform distortion hardly occurs in the audio signal after D / A conversion, and good quality can be obtained.

According to this embodiment, the time base collector 60 is provided at the subsequent stage of the signal demodulator 56, and the restriction of the read clock with respect to the write clock of the time base collector 60 is minimized, so that the clock recovery unit 50 outputs. According to the first clock that follows the jitter of voice transmission data,
When an accurate demodulation operation is performed by the signal demodulator 56, the audio sample data output by the signal demodulator 56 will be affected by the jitter of the voice transmission data input from the outside or the jitter generated in the signal demodulator 56. However, while writing to the time base collector 60 in accordance with the clock BCK synchronized with the audio sample data output from the signal demodulator 56, the second PLL circuit 58 having a narrow band response characteristic from the clock LRCK provides sufficient jitter. It is possible to reproduce the absorbed second clock, read the audio sample data from the time base collector 38 according to the second clock with almost no jitter, and input it to the D / A converter 62 accurately.

Therefore, even if the jitter of the signal demodulator 56 is added to the jitter of the voice transmission data itself received from the outside, the D / A converter 6
Since the jitter is absorbed at the stage of being input to 2, D / A
Waveform distortion does not occur in the converted audio signal, and extremely good sound quality can be obtained.

In the second embodiment described above, the second PLL circuit 58 is
Although the second clock is reproduced from the clock LRCK output from the signal demodulator 56, the second clock may be reproduced from the clock WCK or BCK.

Next, a third embodiment of the present invention will be described with reference to FIG.

In the third embodiment, the demodulation system of the digital I / O interface includes a digital filter, and in the second embodiment, a time base collector is provided on the rear side of the signal demodulator, whereas on the rear side of the digital filter. It shows the case where it is provided.

The same components as those in FIG. 2 are designated by the same reference numerals.

Up to the signal demodulator 56, the configuration is exactly the same as in FIG.

A digital filter 70 is connected to the output side of the signal demodulator 56, and according to the clock output by the signal demodulator 56,
Audio sample data is input, audio sampling is performed, and audio sample data and clocks (LRCK, BCK, WCK, etc.) synchronized with this are output.

The output terminal of, for example, the clock WCK of the digital filter 70 has a second PLL circuit 72 as a second clock recovery circuit.
Clock BCK output from the digital filter 70, which is connected to (including a frequency divider circuit that divides the clock WCK)
A second clock with the same frequency as is regenerated.

The second PLL circuit 72 includes a VCXO (not shown) using a crystal oscillator, and has a relatively narrow band.

The second PLL circuit 72 forms a second clock in which the jitter is sufficiently absorbed from the clock WCK.

Digital filter 70 clock BCK output pin and second P
The output side of the LL circuit 72 is connected to the write clock input terminal and the read clock input terminal of the time base collector 74.

The data output terminal of the time base collector 74 is connected to the data output terminal of the digital filter 70. The time base collector 74 outputs audio sample data to the internal RAM bit by bit according to the clock BCK input to the write clock input terminal. RA according to the second clock input to the write and read clock input terminals
The audio sample data written in M is read bit by bit and output to the outside.

The writing of the audio sample data to the time base collector 74 is performed by the clock BCK synchronized with the output of the audio sample data from the digital filter 70, so that it is accurately performed without causing a data error.

On the other hand, since the audio sample data is read from the time base collector 74 by the second clock having almost no jitter, the audio sample data having almost no jitter is output.

A D / A converter 76 is connected to the output side of the time base collector 74 to convert audio sample data into an analog audio signal.

Here, since the audio sample data output from the time base collector 74 has almost no jitter, waveform distortion hardly occurs in the audio signal after D / A conversion, and extremely good sound quality can be obtained.

According to this embodiment, a time base collector 74 is provided after the digital filter 70, and the time base collector 74
By minimizing the restrictions on the read clock with respect to the write clock, the voice transmission data itself received from the outside contains jitter, and new jitter is added inside the signal demodulator 56 and inside the digital filter 70. Or, even if there is jitter in the audio sample data output from the digital filter, while accurately writing to the time base collector 74 in accordance with the clock BCK synchronized with this audio sample data,
Second PLL circuit with narrow band response from clock WCK
At 72, reproduce the second clock that has sufficiently absorbed the jitter,
In accordance with this second clock, the audio sample data can be read from the time base collector 74 and input to the D / A converter 76 accurately with almost no jitter.

Therefore, even if the demodulation system of voice transmission data has a complicated structure including a digital filter, all the jitter of audio sample data can be absorbed at the stage of being input to the D / A converter 76. Waveform distortion does not occur in the converted audio signal, and good sound quality is obtained.

Although the second PLL circuit 72 reproduces the second clock from the clock WCK output from the digital filter 70 in the third embodiment, the second clock is reproduced from the clocks LRCK and BCK. Good.

[Effect of device]

The demodulator for audio transmission data according to the present invention is provided with a time base collector in front of the demodulator to minimize the restrictions on the read clock with respect to the write clock of the time base collector. Accurately write the audio transmission data to the time base collector according to the clock reproduced by the PLL circuit of 1.
According to the clock reproduced by the narrow band second PLL circuit including the VCXO based on the output clock of the first PLL circuit, the voice transmission data can be read from the time base collector and input to the demodulator with almost no jitter, It is possible to perform accurate demodulation of audio sample data with little jitter.

Since the VCXO is used for the second PLL circuit, it has excellent jitter suppression performance, high stability against changes over time and environmental changes, and good demodulation of audio sample data can always be performed.

In addition, another demodulator for audio transmission data of this invention is provided with a time base collector after the demodulator, and accurately writes the audio sample data output by the demodulator to the time base collector according to the clock output by the demodulator. , A narrow band second PLL from the clock output by the demodulator
Since the time base collector reads the audio sample data with almost no jitter according to the clock reproduced by the circuit, it is better than the one that absorbs both the jitter of the voice transmission data input from the outside and the jitter generated in the demodulator. It is possible to output a small amount of audio sample data.

Even if the device has a digital filter, a demodulator for audio transmission data according to another aspect of the present invention is provided with a time base collector after the digital filter, and the audio sample output by the digital filter is output according to the clock output by the digital filter. Since the data is accurately written to the time base collector, and the time base collector reads the audio sample data with almost no jitter in accordance with the clock reproduced by the narrow band second PLL circuit from the clock output from the digital filter, It is possible to output audio sample data that absorbs both the jitter of voice transmission data input from the outside and the jitter generated in the demodulator and digital filter.

[Brief description of drawings]

FIG. 1 shows a digital I / O according to the first embodiment of the present invention.
2 is a block diagram of the demodulation system of the interface, FIG. 2 is a block diagram of the demodulation system of the digital I / O interface according to the second embodiment of the present invention, and FIG. 3 is a digital I according to the third embodiment of the present invention. FIG. 4 is a block diagram of the demodulation system of the / O interface, and FIG. 4 is a block diagram of the demodulation system of the conventional digital I / O interface. Description of main symbols 30,50: Clock recovery unit, 32,52: Frame synchronization signal detection circuit, 34,54: First PLL circuit, 36,58,72: Second PLL circuit, 3
8,60,74: Time base collector, 40,56: Signal demodulator, 7
0: Digital filter.

Claims (3)

[Scope of utility model registration request] 1. A narrow band second circuit which includes a first PLL circuit for outputting a clock synchronized with audio transmission data and a VCXO, and which outputs a clock synchronized with the clock output from the first PLL circuit. A PLL circuit, a time base collector in which voice transmission data is written according to a clock output from the first PLL circuit, and the voice transmission data is read according to a clock output from the second PLL circuit;
A demodulator for demodulating audio sample data from audio transmission data read from the time base collector according to a clock output from a PLL circuit, and a demodulator for audio transmission data. 2. A first PLL circuit that outputs a clock synchronized with audio transmission data, and demodulates the audio sample data from the audio transmission data in accordance with the clock output by the first PLL circuit, and also samples the audio sample data. A narrow band second PLL circuit including a demodulator that forms a clock synchronized with the output of the VCXO and that outputs a clock synchronized with the clock output from the demodulator, and a clock output from the demodulator A time base collector into which the audio transmission data is written, and which reads the audio transmission data according to the clock output from the second PLL circuit;
An apparatus for demodulating voice transmission data, comprising: 3. A first PLL circuit that outputs a clock synchronized with the audio transmission data, and demodulates audio sample data from the audio transmission data according to the clock output by the first PLL circuit, and audio sample data. A digital signal that forms a clock that is synchronized with the audio sample data output after conversion is performed on the audio audio sample data in accordance with a demodulator that forms a clock that is synchronized with the output of the A narrow band second PLL circuit which includes a filter and a VCXO and outputs a clock synchronized with the clock output from the digital filter; and audio sample data output from the digital filter according to the clock output from the digital filter. Written and output by the second PLL circuit And a time base collector for reading audio sample data according to a clock.