JPS63312785A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To simplify a structure by providing a phase compensation characteristic with respect to a video base band component to an analog LPF so as to facilitate the design of a digital filter constituting a video filter. CONSTITUTION:An output of an A/D converter 2 is extracted for a component only required for the detection of a video signal from the A/D conversion output including an FM audio signal by a digital BPF (band pass filter) 3 and fed to the FM detection circuit 4 of the next stage. Only the base band component of the video signal is extracted from the detection output of the FM detection circuit 4 at a phase linear noncyclic digital filter 50 and a down-sampling circuit 51 in a video filter 5. The digital video signal read from a buffer memory 6 is converted into an analog signal by a D/A converter 10 and the sampling clock component is eliminated by the LPF 11 and becomes the reproduced video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing circuit, and in particular to a video signal processing circuit that processes recorded information by digitizing a high frequency signal (hereinafter referred to as 1?, F signal) read from a recording medium. The present invention relates to a video signal processing circuit in a playback device.

BACKGROUND TECHNOLOGY Recording information reproduction bag ■For example, in a disc player that plays back a video disc on which a video signal has been subjected to FM modulation processing, the signal processing of the FM video signal read from the disc has conventionally been carried out in an analog way. It was common to do so.

However, when it comes to IG (integrated circuit) circuits, it is extremely advantageous to perform signal processing digitally rather than analogously, and it is also easier to increase the number of functions in the signal processing process. , and even higher image quality can be achieved.

Therefore, the present applicant has already proposed a video signal processing circuit that digitally processes the video'ARP signal read from the disc (Japanese Patent Application No. 6O-280711).
(See specification H).

In such a video signal processing circuit, a video filter is used to extract only the video baseband component from the detected output that has been digitized and then subjected to FM detection.

This video filter also performs downsampling, and for this reason, the video filter must have not only phase compensation characteristics (group delay characteristics) for the video baseband component, but also low-pass characteristics to remove aliasing components caused by downsampling. There is.

However, it is not easy to design one digital filter 51 so that both the phase compensation characteristic and the low-pass characteristic meet the standards. This is because in order to rotate the phase, the filter configuration must be designed in a cyclic form (IIR).
If you try to match the phase compensation characteristics to the standard, the cut-off frequency and frequency characteristics of the filter will be determined automatically, and if you try to improve one characteristic, it will inevitably affect the other. This is because characteristics must be sacrificed. Furthermore, since it is a cyclic filter with feedback, there is a drawback that the rounding error l'l due to the end of a finite word length is large. Therefore, it cannot necessarily be said that providing one digital filter with both phase compensation characteristics and low-pass characteristics is a good idea.

The present invention has been made in view of the above-mentioned points, and it is possible to improve the design of the digital filter constituting the video filter by providing a phase compensation characteristic to a circuit other than the video filter.
It is an object of the present invention to provide a video signal processing circuit that facilitates processing and simplifies the structure.

The video signal processing circuit according to the present invention includes a video filter that extracts only the video baseband component from the video detection output and downsamples it, and a video filter that converts the video baseband component into an analog signal and passes only the low frequency component of the signal. an analog low-pass filter that
The video filter is composed of a phase linear acyclic digital filter having low-pass characteristics that removes aliasing components caused by downsampling, and the analog low-pass filter has phase compensation characteristics for the video baseband component. .

Friend-Dust-1 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of a video signal processing circuit according to the present invention. In the figure, an FM video signal read from a recording medium such as a video disk passes through an analog LPF (low pass filter) 1 and then is digitized by an A/D converter 2. Analog LPF1 is A/D
This is provided to remove aliasing components in conversion. The output of A/D converter 2 is a digital BPF
(Bandpass filter) 3 extracts only the components necessary for video signal detection from the Δ/D conversion output that also includes the FM audio signal, and supplies the extracted components to the FM detection circuit 4 at the next stage. FM
As the detection circuit 4, for example,
9-262481 can be used. The detection output of the FM detection circuit 4 is sent to the video filter 5.
At , only the baseband component of the video signal is extracted.

The video baseband component that has passed through the video filter 5 is supplied to a buffer memory 6 and a signal separation circuit 7.

The signal separation circuit 7 separates the reproduced horizontal synchronizing signal (PB-H) and color burst signal (C) contained in the digital video A signal.
8) etc. are separated and extracted and supplied to the PLL circuit 8. PLL
The circuit 8 generates 4fsc (fsc
(color subcarrier frequency) and 4Nfsc (N is an integer of 2 or more, for example 3). The 4f'sc and 4Nfsc clocks generated by the PLL circuit 8 are used as clocks for digital signal processing,
The 4Nf'sc clock is used as the summing clock of the A/D converter 2 and the signal processing clock up to the foff filter 5, and the J3 clock is used at the output stage of the video filter 5.
The signal is then downsampled with a 4fsc clock.

The digital video signals inputted into the buffer memory 6 are sequentially written into the buffer memory 6 by a clock of 4 fsc which is phase independent of the reproduced video signal generated by the PLL circuit 8. Reading of data from this buffer memory 6 is performed using the 4 f
This is done using the reference clock of S (:). In this way, by sequentially reading out the f-times written in the buffer 7 memory 6 in order by the stable yJ quasi-clock, the jitter (ff: 'i axis) of the reproduced video signal is The digital video signal read from the buffer memory 6 is transferred to a D/A converter 10-
(-7 After being converted to analog, the sampling clock component is removed by the LPFll, resulting in a reproduced video output.

FIG. 2 is a block diagram showing a specific configuration of the video filter 5 in FIG. 1. In this figure, the video filter 5 operates at a clock frequency of 4Nfsc and the FM
Included in the detection output: A phase linear acyclic digital filter 50 that removes the η transmitted wave component and extracts only the video baseband component, and a downsampling circuit that downsamples the output of this digital filter 50 at a clock frequency of 4 fsc. It is composed of 51. In this way, by lowering the sampling frequency, it becomes possible to reduce the time margin and hardware requirements in subsequent circuits. Phase linear acyclic digital filter 50
has a low-pass characteristic that eliminates aliasing components caused by da-sin sampling in the next stage. The amplitude characteristics are shown in FIG.

As shown in FIG. 4, the phase-linear acyclic digital filter 50 includes delay circuits 5011 to 501n connected in cascade to each other and delay circuits 5011 to 501n that provide a delay of 1 cock.
A multiplier 5020 that multiplies the input signal of 011 and each output signal of the delay circuits 5011 to 501n by coefficients ko to ko, respectively.
~502n, and a q adder 503 that adds each power Q output,
The clock frequency of the delay circuits 501+ to 50in and the latch circuit 504 is set to 4Nfsc.

Furthermore, it is necessary to perform phase compensation on the video baseband component extracted by the video filter 5, but in the present invention, this phase compensation is performed using the analog LPF shown in FIG.
It is configured to be carried out in II. This analog LPF1
1 is absolutely necessary to remove the clock component in the analog video signal after D/Δ conversion, and is the desired group! ! By providing a time delay characteristic (phase compensation characteristic), it is possible to perform phase ()+Ii compensation in the cylinder. As the analog LPF 11, R1[ as shown in FIG.

Using the well-known passive filter by C (!1), the desired group delay characteristic can be easily achieved by only slightly changing each constant.
7. Be able to do it. The amplitude characteristics and delay characteristics of this analog LPF 11 are shown in FIGS. 6 (Δ) and (I3).

As you can see, (the complementary 10 characteristic is analog I-P F
11, the video filter 5 only needs to satisfy the requirement '1 of removing the carrier wave component of the video FM detection output and the aliasing component due to downlinking, so it is possible to achieve a simple structure with a low order. This can be realized using a phase-linear acyclic digital filter that is less affected by rounding errors.

As explained above, according to the video signal processing circuit according to the present invention, the analog LPF has a phase compensation characteristic for the video baseband component, so that the video filter can control the video FM detection output. The condition of removing the carrier wave component and the aliasing component due to downsampling is satisfied. Since only -1 is required, a single MA structure can be achieved with a low order. However, since the video filter can be configured with a phase linear acyclic digital filter, the right There is also little effect of rounding errors due to the performance of Kamitura.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the video signal embedding circuit according to the present invention, FIG. 2 is a block diagram showing the specific configuration of the video filter in FIG. Figure 4 is a block diagram showing an example of the configuration of the phase linear acyclic digital filter, and Figure 5 is an example of the configuration of the analog LPF in Figure 1. Circuit diagram showing 6th
The figure shows the amplitude characteristics (A) of the analog LPF shown in Figure 1 ().
and a diagram showing group delay characteristics (B). Explanation of main parts 4...FM detection circuit 5...Video filter 6...Buffer memory

Claims (1)

[Claims] When reproducing an FM-modulated video signal recorded on a recording medium, the video R read from the recording medium
A video signal processing circuit that digitizes and detects the F signal, which includes a video filter that extracts only the video baseband component from the video detection output and downsamples it, and a video filter that is obtained by converting the video baseband component into analog. an analog low-pass filter that passes only low-frequency components of the signal; the video filter is configured with a phase-linear acyclic digital filter having a low-pass characteristic that removes aliasing components caused by downsampling; A video signal processing circuit, wherein the analog low-pass filter has phase compensation characteristics for the video baseband component.