JPH0755618Y2 - Reference voltage setting circuit - Google Patents

Description

The present invention relates to a reference voltage setting circuit, and more particularly to a reference voltage setting circuit having a plurality of voltage setting circuits having a trimming circuit.

[Conventional technology]

Conventionally, when a reference voltage circuit of this type has two voltage setting circuits capable of setting a voltage with N = 4 bits, for example, as shown in FIG. 5, four first trimming circuits 1 _X1 to 1
And _X4, the first voltage dividing circuit 3 _X of N = 4 bits, and the first voltage setting circuit 100 and a buffer circuit 4 _X, 3 pieces of the second trimming circuit 1 _Y1 to 1 _Y3 and N = 4-bit operation unit 2 _D and N
The second voltage setting circuit 200 _D including the 4-bit second voltage dividing circuit 3 _Y and the buffer circuit 4 _Y is included.

As shown in FIG. 6, the trimming circuits 1 _X1 to 1 _X4 and 1 _Y1 to 1 _Y3 are each capable of cutting a fuse F _i , a trimming pad P _i , a current limiting resistor R _3i , and an N channel MOS.
FETQ _4i and pull-up resistor R _4i are connected in series between terminal T _2i and power supply terminal (power supply voltage V _DD ), and N-channel MOSFE
The connection point between TQ _4i and the resistor R _4i is used as the output terminal T _3i for the trimming signals X _i and Y _i , and the gate of the MOSFET Q _4i is pulled up to the power supply terminal (V _DD ) with the resistor R _2i for pulling up. a gate connected to a terminal T _1i, terminal T _1i, T _2i is respectively connected to the gate common pad P _C and common pad P _G.

Further, as shown in FIG. 7, the voltage dividing circuit 3 _X , 3 _Y of N = 4 bits receives two reference potentials V _A , V _B as input and 2 ^N between these reference potentials V _A , V _B. -1 (that is, 15) resistors R _{1 to} R ₁₅ having the same resistance value are connected in series and divided, and N-channel MOSFETs Q _{1 to} Q ₃₀ and buffer circuits G _{1 to} G ₄ having complementary outputs With the selection circuit composed of and, one of the potentials divided by resistors R _{1 to} R ₁₅ is selected according to the input signal (X _{1 to} X ₄ , Z _{1 to} Z ₄ ), and the divided output potential V _The configuration is such that _X and V _Y are obtained.

The divided output potentials V _X and V _Y at this time are the input signals (X _{1 to} X ₄ , Z ₁
~ Z ₄ ) have the relationship shown in Table 1.

The buffer circuits 4 _X and 4 _Y are forward amplifiers for driving the load.

Next, the trimming operation of this reference voltage setting circuit will be described.

The divided output potential V _X of the first voltage setting circuit 100 is trimmed as follows to set the voltage.

First, the gate common pad P _C is opened and the value V _OL of the divided output potential V _X is measured.Next, the gate common pad P _{C is set} to the power supply potential V _SS , that is, the ground potential, and the divided output potential V V is set.
Measure _X value V _OH Then, trimming circuits 1 _X1 to 1 _X4 are set so that the values V _OL and V _{OH of} these divided output potentials V _X fall within the defined voltage range V _XO ± V _XOF.
Determining the disconnection of fuse F _i . The disconnection of the fuses F _i of the trimming circuits 1 _X1 to 1 _X4 at this time is determined by the equation (1).

Since the second voltage setting circuit 200 _D is dependent on the trimming outputs X _{1 to} X ₄ of the first voltage setting circuit 100, the divided voltage output potential V _Y of the second voltage setting circuit 200 _D is the first Voltage setting circuit 10
After the trimming of 0 is completed, perform as follows.

First, the gate common pad P _C is opened and the divided output potential
Measure the V _Y value V _OL ′, and then
The value V _OH ′ of the divided output potential V _Y is measured as the state of _SS , and the values V _OL ′, V _OH ′ of these divided output potentials V _Y are trimmed so that they fall within the specified voltage range V _YO ± V _YOF. Determines the disconnection of fuse F _{i in} circuits 1 _Y1 to 1 _Y3 . Trimming circuit 1 at this time
The blow of the fuses F _i of _Y1 to 1 _Y3 is determined by the equation (2).

If the trimming outputs X _i and Y _i thus obtained are “1”,
The corresponding fuse F _i may be cut by applying a current pulse between the common pad P _G and the corresponding trimming pad P _i .

The second voltage setting circuit 200 _D is dependent on the trimming outputs X _{1 to} X ₄ of the first voltage setting circuit 100, but the second voltage dividing circuit
The relationship with the voltage division selection signals Z _{1 to} Z ₄ input to 3 _Y is as shown in equation (3).

In the equation (3), [+] indicates an exclusive OR, + indicates a normal OR, and • indicates a logical product (the same applies hereinafter).

For example, the trimming output of the first voltage setting circuit 100 is X ₄
If = 0, X ₃ = 1, X ₂ = 1, X ₁ = 0, from Table 1, V _X = 6/15
(V _A −V _B ), and V _Y can be set within the following range from Eq. (3).

_{2/15 (V A -V B) ≦} V Y ≦ 9/15 (V A -V B) ...... (4) [problem devised to be Solved] conventional reference voltage setting circuit described above, the first and second trimming signal X _i, by performing a predetermined operation on Y _i to generate a partial pressure selection signal Z ₁ to Z _4, a second voltage divider circuit by the partial pressure selection signal Z ₁ to Z ₄ Since the configuration is such that one of the potentials divided into 2 ^{N by} 3 _Y is selected, the number of trimming circuits increases and the chip area increases when the resolution is increased, limiting the number of trimming circuits. Then, there is a drawback that the resolution cannot be increased.

An object of the present invention is to provide a reference voltage setting circuit capable of increasing the resolution without increasing the trimming circuit and reducing the chip area if the resolution is the same.

[Means for Solving the Problems]

The reference voltage setting circuit according to the present invention comprises a fuse capable of being cut, and outputs N first (N is an integer of 2 or more) first trimming signals having different levels depending on whether or not the fuse is cut. Trimming circuit of the first
And a first divided voltage for dividing the second reference potential into 2 ^N pieces and selecting one of the divided potentials by the first trimming signal to output a first divided output potential. A first voltage setting circuit including a circuit and fuses that can be cut, and outputs M second trimming signals of different levels depending on whether or not the fuses are cut (M is 1 ≦ M <N Second trimming circuit, the first trimming signal, the second trimming signal, and difference information including information on a difference between the first divided output potential and the second divided output potential. Is input to perform a predetermined calculation and outputs a voltage division selection signal, and the first and second reference potentials are divided into 2 ^N pieces, and one of these divided potentials is divided into A second voltage output signal which is selected by a pressure selection signal and outputs the second divided output potential. And a second voltage setting circuit including a voltage divider.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The first voltage setting circuit 100 of this embodiment has the same configuration and function as the conventional reference voltage setting circuit shown in FIG.

The second voltage setting circuit 200 includes fuses F _i that can be cut, and outputs the _second trimming signals Y ₁ and Y ₂ having different levels depending on whether the fuses F _i are cut or not. The first trimming signals X _{1 to} X ₄ and the second trimming signals Y ₁ , Y 2 are provided with two second trimming circuits 1 _Y1 and 1 _Y2 having the same configuration as the above circuit and four adders 22. Adder circuit 21 _A that inputs ₂ and ₂ and performs the first operation, and four adders 2
4-bit difference information U including the output signals W _{1 to} W ₄ of the adder circuit 21 _A and the difference between the first divided output potential V _X and the second divided output potential V _{Y. 1st to} 2nd trimming signal X including the second addition circuit 21 _B which inputs _{1 to} U ₄ and performs the second calculation
_{1 to} X ₄ , Y ₁ and Y ₂ and difference information U _{1 to} U ₄ , a calculation unit 2 that performs a predetermined calculation and outputs divided voltage selection signals Z _{1 to} Z ₄ , and a first and second reference dividing the voltage V _a, between V _B 2 ^4, a second partial pressure through the buffer circuit 4 _Y selects one of these-divided potential by partial pressure selection signal Z ₁ to Z ₄ It has a configuration including a second voltage dividing circuit 3 _Y having the same configuration as the circuit of FIG. 7 for outputting the output potential V _Y.

In the first adder circuit 21 _A of the arithmetic unit 2, the operation represented by the equation (5) is performed.

In addition circuit 21 _B , the operation shown in equation (6) is performed.

The difference information U _{1 to} U ₄ is obtained by dividing the difference between the second divided output potential V _Y and the first divided output potential V _X by (V _A −V _B ) / (2 ⁴ −1) It is a binary code represented by two's complement of the digitized value.

Next, the trimming operation of this embodiment will be described.

The divided output potential V _X of the first voltage setting circuit 100 is trimmed by obtaining X _i by the equation (1) as in the conventional case.

Next, the divided output potential V _Y of the second voltage setting circuit 200 is trimmed as follows.

As in the conventional case, the value of the divided output potential V _Y can be set in two states, that is, the gate common pad P _C is opened and the power source potential V _SS.
Measure V _OL ′ and V _OH ′, and decide to blow fuse F _i of trimming circuit 1 _Y1 to 1 _Y2 so that it is within the specified voltage range V _YO ± V _OF . Fuse of trimming circuit 1 _Y1 to 1 _Y2 at this time
The cutting of F _i is determined by the equation (7).

Note that INT (S) is a function that converts S into an integer. If the trimming output Y _i thus obtained is “1”, the corresponding fuse F _{i is connected} to the common pad P _G and the corresponding trimming pad.
A current pulse is applied between it and P _i to disconnect it.

For example, if the trimming signals in the first voltage setting circuit 100 are X ₄ = 0, X ₃ = 1, X ₂ = 1, X ₁ = 0, then from Table 1 Therefore, if the difference information is U ₄ = 0, U ₃ = 0, U ₂ = 1 and U ₁ = 0, V _Y can be set within the range of the following equation (8).

In the conventional example, the number L of trimming circuits of the second voltage setting circuit is required to set the range of the formula (8), but in this embodiment, the number M of trimming circuits may be two. .

In the present technology, the area S _{T of the} trimming circuit shown in FIG. 6 is about 200 μm × 500 μm, and the area S _{A of the} adder is about
Since the layout area S ₂ of the circuit of the conventional example and the layout area S ₁ of the circuit of this embodiment can be realized by about 100 μm × 60 μm, they are expressed by the following equation (9).

From this, it can be understood that the present invention is smaller.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

The second embodiment differs from the first embodiment, changing the order of operations for generating a partial pressure selection signal Z ₁ to Z _4, a second trimming signal Y ₁ to Y ₂ and the difference information U ₁ ~ U ₄ and adder circuit
Calculated at 21 _C and the result and the first trimming signal X _{1 to} X ₄
A point which is adapted to calculate by adding circuit 21 _D with respect, since all others are the same, the result is the same as in the first embodiment.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

The third embodiment is different from the first and second embodiment, changing the order of operations to these embodiments, the first trimming signals X ₁ to X ₄ and difference information U ₁ ~U ₄ Is calculated by the adder circuit 21 _E and the result and the second trimming signal Y
_{1 to} Y ₂ is calculated by the adder circuit 21 _F , and all other things are the same, so the result is the same as in the first embodiment.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

The difference between the fourth embodiment and the first to third embodiments is that
The calculation unit 2 _C is changed from a ripple carry type adder circuit to a Walldcetree type adder circuit, which has the advantage of speeding up the operation speed, and since everything else is the same, the result is This is similar to the first embodiment.

Further, even if the number of the first and second voltage setting circuits is plural and the number of trimming bits N is other than 4, similarly, the divided output potential V _Y of the second voltage setting circuit is , The first and second trimming signals and the difference information can be set.

In addition, generally, the trimming of the second voltage setting circuit,
A trimming signal of M trimming circuit Y ₁ to Y _M (M bits), the difference information U ₁ ~U _N and, trimming signal of the N trimming circuit of the first voltage setting circuit X ₁ to X _N (N bit)
If it is decided by, the fuse cutting condition is (10)
It can be given by an expression.

[Effects of the Invention] As described above, the present invention provides the N-th circuit of the first voltage setting circuit.
A voltage division selection signal is generated from the bit trimming signal, the N bit difference information, and the M bit (M <N) trimming signal of the second voltage setting circuit, and the second voltage setting circuit is generated by this voltage division selection signal. With the configuration in which the divided voltage output of the voltage dividing circuit is selected, the trimming circuit of the second voltage setting circuit can be reduced if the resolution is the same, and therefore the number of pads is reduced and the arrangement around the chip is facilitated. The chip area can be reduced, and the resolution can be increased if the number of trimming circuits is the same, so that the reference voltage can be set accurately.

[Brief description of drawings]

1 to 4 are block diagrams showing first to fourth embodiments of the present invention, FIG. 5 is a block diagram showing an example of a conventional reference voltage setting circuit, and FIG. 6 is FIG. A circuit diagram showing a specific example of the trimming circuit in the reference voltage setting circuit shown in FIG. 5, and FIG. 7 is a specific example of the voltage dividing circuit in the reference voltage setting circuit shown in FIGS. 1 to 5. It is a circuit diagram showing. 1 _X1 to 1 _X4 , 1 _Y1 to 1 _Y3 ... Trimming circuit, 2,2 _A to 2 _D ... Arithmetic section, 3 _X , 3 _Y ... Voltage dividing circuit, 4 _X , 4 _Y ... Buffer circuit, 21 _A to 2
1 _H ... adder circuit, 22 ... adder, 100,200,200 _A ~200 _D ... voltage setting circuit, F _i ... fuse, G ₁ ~G ₄ ... buffer circuit, Q ₁ ~
Q ₃₀ , Q _4i … MOSFET, R _{1 to} R ₁₅ , R _{2i to} R _4i … Resistor.

Claims (1)

[Scope of utility model registration request] 1. N first trimming circuits (N is an integer of 2 or more) each of which has a disconnectable fuse and outputs a first trimming signal of a different level depending on whether the fuse is disconnected or not. , first the between the first and second reference potential pressure to ^the 2 ^N min, and outputs the first divided output voltage by selecting one of these-divided potential by the first trimming signal A first voltage setting circuit including a voltage dividing circuit and a fuse that can be cut, and outputs M second trimming signals of different levels depending on whether or not the fuse is cut (M is 1 ≦ A second trimming circuit of M <N), the first trimming signal, the second trimming signal, and information on the difference between the first divided output potential and the second divided output potential. Enter the difference information including Arithmetic unit for outputting a divided selection signal performs calculation, and the first, divided between a second reference potential to ^the 2 ^N, one of these-divided potential selected by the partial pressure selection signal And a second voltage setting circuit including a second voltage dividing circuit for outputting the second divided voltage output potential.