KR100209656B1 - High speed adder with pseudo carry - Google Patents

Abstract

In a carry lookahead adder having an input Cin, the binary input signal A and the B bit input are logically combined to generate a carry generation signal G and a transfer signal P, And generates a group signal Hg, Ig for obtaining a top virtual carry of each virtual carry lookahead (PCLA) block. The carry generation and transfer signal and the previous carry carry input are logically combined to generate a group carry signal (N = 1, 2, 3, ...) number of PCLA blocks consisting of at least one or more than one subcarriers for obtaining a lower virtual carry, a group signal Hg, Ig output from the Nro's PCLA block, And an upper virtual carry generating unit for obtaining the most significant virtual carry of each of the PCLA blocks and applying the result to the virtual carry input of the next stage PCLA block by logically combining the high- To implement In addition, high-speed computation of digital signal processor (DSP) is possible, and addition input bit can be changed easily, so it is scalable and can be configured as standard cell, so it does not need interface with standard cell. Implementation is facilitated.

Description

Fast adder using virtual carry

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Carry Look Ahead (CLA) adder, and more particularly to a fast adder using a virtual carry using a virtual carry will be.

The conventional adder is a carry select adder and basically uses two ripple carry adders as shown in FIG.

1, there are shown a 4-bit adder 11 for adding the lower 4 bits, a 4-bit adder 12 for setting the carry at the carry input terminal to '0' in advance and adding the upper 4 bits at the same time as the adder 11, A 4-bit adder 13 for setting the carry of the carry input in advance to '1' and adding the upper 4 bits at the same time as the adder 11, and a 4-bit adder 13 for adding the upper 4 bits to the adder 12 or the adder 11, And a carry output unit 15 for outputting a final carry according to the carry output of the adder 11. The multiplexer 14 selects the sum of the adder 13 and outputs the sum as a sum.

The carry output section 15 includes an AND gate for logically multiplying the carry generated in the adder 11 and the adder 13 and a Noah gate for logically combining the outputs of carry and end gates generated in the adder 12 do.

The carry output unit 15 corresponds to a gate type that satisfies - ((CIN C1) + C0) or - ((CIN + C0) C1).

Here, CIN is the carry input generated in the previous stage, for example, the adder 11, C0 is the adder 12, and C1 is the carry output generated in the adder 13.

The first figure thus configured is configured to add the carry input CI and the lower 4 bits A3: 0 and B3: 0 at the adder 11 to output the sum SUM3: 0 and at the same time to output the carry output to the multiplexer 14 To the carry output section 15.

At this time, the adder 12, which sets the carry input to '0' in advance, and the adder 13 which sets the carry input to '1' in advance are also connected to the adder 11 at the same time as the upper 4 bits (A7: 4, B7 : 4) are added, and the sum of each of them (S07: 4, S17: 4) is applied to the multiplexer 14.

The multiplexer 14 selects the addition result of the adder 13 when the carry generated by the adder 11 is 0 and outputs the addition result to the final sum SUN7:

The AND gate of the carry output unit 15 logically multiplies the carry generated in the adder 11 and the adder 13. [ That is, if the carry generated in the adder 11 is 0, the AND gate outputs 0 to the Noah gate unconditionally. If the carry is 0, the carry generated in the adder 13 is output to the Noah gate.

The Noah gate outputs 1 to the final carry (-C7) only when the carry generated by the adder 12 and the output of the AND gate are both 0, and outputs 0 to the final carry (-C7) otherwise.

FIG. 2 is a 32-bit carry select adder that extends the first diagram. The adder blocks 22, 25, 28, 31, and 34 except for the adder 21 for adding the lower 4 bits, And a ripple carry adder and multiplexer pre-set to '1'.

Therefore, each adder block 22, 25, 28, 31, 34 controls the multiplexer according to the carry output generated in the adder block of the previous stage, and outputs the final sum of the adder block, 26, 29, 32, 35).

Thus, based on FIG. 1, the addition bits can be extended to 48 bits, 64 bits,...

However, in the above conventional carry-select adder, two carry-adders are required for each carry for each adder block, considering both cases of '1' and '0' And a carry output for finally selecting a carry is required, which increases the total area of the adder.

Further, there is a problem that the operation speed is lowered by directly using the carry in the operation and performing serial serial operation from the least significant bit (LSB) to the most significant bit (MSB).

In addition, by using a cell for only the adder, an interface with a standard cell is required, and an option for the standard cell is required. Thus, the design is complicated and the implementation of the adder is not easy.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a high speed Thereby providing an adder.

According to another aspect of the present invention, there is provided a CLA adder including a pair of A and B bit inputs and a carry input, A generation and transmission signal generation means for generating a carry generation signal and a transmission signal in a logical combination of a carry signal and a carry signal output from the generation and transmission signal generation means, N (N = 1, 2, 3, ...) number of CLA blocks, each of which consists of at least one or more subcarriers of each CLA block by logically combining the carry generation and transfer signal with the previous carry input, A grouping signal outputted from the N CLA blocks and a first carry input are logically combined to obtain a highest carry of each of the CLA blocks, And an upper carry generating means for generating the upper carry generating means.

Another aspect of the present invention is to provide a CLA adder having a pair of A and B bit inputs and a carry input wherein the binary input signal A and B bit inputs are logically combined to generate and transmit a carry generation and transfer signal And generates a group signal for obtaining a top virtual carriage of each virtual carry lookahead (PCLA) block by logically combining the carry generation and transmission signals output from the generation and transmission signal generation means, N (N = 1, 2, 3, ...) number of PCLA blocks, each of which consists of at least one logical combination of the virtual carry inputs of the previous stage and the previous stage to obtain a lower virtual carry of each PCLA block, And the first virtual carry input is logically combined to obtain the uppermost virtual carry of each of the PCLA blocks, and then the upper virtual carry is applied to the virtual carry input of the next PCLA block Is the point which comprises a stage.

FIG. 1 is a block diagram of a conventional 4-bit carry select adder; FIG.

Figure 2 is a block diagram of a conventional 32 bit carry select adder;

FIG. 3 is a 4-bit carry lookahead (CLA) block diagram according to a first embodiment of the present invention; FIG.

FIG. 4 is a 16-bit carry lookahead (CLA) block diagram according to a first embodiment of the present invention.

FIG. 5 is a block diagram of a 64-bit carry lookahead (CLA) according to a first embodiment of the present invention; FIG.

6a to 6d are logic circuit diagrams for generating a virtual carry according to a second embodiment of the present invention.

FIG. 7 is a 4-bit virtual Carry Look Head (PCLA) block diagram according to a second embodiment of the present invention. FIG.

FIG. 8 is a 16-bit virtual carry lookahead (PCLA) block diagram according to a second embodiment of the present invention. FIG.

FIG. 9 is a block diagram of a 64-bit virtual carry lookahead (PCLA) block according to a second embodiment of the present invention; FIG.

FIG. 10 is a block diagram for obtaining a sum in an adder according to the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

38: Carry Look Head (CLA part) 41-45,55,85,95: 4-bit CLA part

51-54: 16-bit CLA unit 71, 81-84: 4-bit virtual carry lookahead (PCLA) unit

91-94: 16-bit PCLA section

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Example 1]

If the input of the adder is A and B and the carry is Cin, then the important Sum and Carry are

Respectively.

This is converted to a general equation for obtaining the i-th sum (Si) and carry (Ci) as follows.

to be.

In the above equations (3) and (4), Gi = Ai * Bi, Pi = Ai + Bi, Psi = Ai Bi. Here, Gi is a carry generation signal and Pi is a carry propagation signal.

That is, in order to obtain the i-th sum and carry of the adder, it is necessary to know the combination of the i-th inputs and the carry carried out from the previous stage.

In order to perform a high-speed operation in a high-bit adder, first, the carry of each stage is obtained and a sum is obtained. In the end, it is important to know the carry input of each stage, and the carry is first calculated and then the sum is calculated. In other words, how fast the carry is obtained is the key to the overall speed of the adder.

FIG. 3 is a block diagram of a CLA according to a first embodiment of the present invention. At this time, when the carry of each stage in the CLA composed of 4 bits of FIG. 3 is viewed,

In summary,

.

In each of the above carries, it is distinguished by a term with Cin and a term with no term.

In other words,

.

That is, in the 4-bit CLA block of FIG. 3, the last carry output C3 can be obtained by knowing Gg, Pg, and Cin. Therefore, C3 is not obtained but only Gg and Pg are obtained.

Also, it can be seen that the carry C0 to C3 at each stage can be obtained simultaneously when G0-G3, P0-P3, and carry input Cin, which are combinations of input bits, are input.

This shows that the combination of Gg and Pg of the blocks bounded by several bits can be used to determine the carry of each stage and the final stage.

That is, G and P for one bit, and G and P for the entire 4 bits as well as the carry output if the carry input is known, and the carry output of the group if the carry input is known.

This means that the CLA method is applied to 4-bit blocks as well. In addition, since the number of CLA blocks can be increased or decreased, it is possible to configure various bits of CLA even in the same structure.

FIG. 4 is a block diagram showing the 4-bit CLA of FIG. 3 expanded to a 16-bit CLA according to the present invention.

Referring to FIG. 4, in the first 4-bit CLA unit 41, the carry generation and transmission signals G3-G0 and P3-P0 generated by combining input bits are applied to Equation (9) and Equation (10) To the 4-bit CLA unit 45. The 4-bit CLA unit 45 outputs the group signals Gg0 and Pg0.

The second 4-bit CLA unit 42 applies the carry generation and transmission signals G7-G4 and P7-P4, which are combinations of input bits, to the above-mentioned Equations (9) and (10) to generate group signals Gg1 and Pg1 To the 4-bit CLA unit (45).

The third 4-bit CLA unit 43 applies the carry generation and transfer signals G11-G8 and P11-P8, which are combinations of the input bits, to the above-mentioned Equations 9 and 10 to generate the group signals Gg2 and Pg2 To the 4-bit CLA unit (45).

The fourth 4-bit CLA unit 44 applies the carry generation and transmission signals G15-G12 and P15-P12, which are combinations of the input bits, to the above-mentioned Equations 9 and 10 to generate the group signals Gg3 and Pg3 To the 4-bit CLA unit (45).

That is, when the carry generation and transmission signals G15-G0 and P15-P0, which are combinations of input bits, are simultaneously input to the first through fourth CLA units 41-44, the group signals Gg3-Gg0 , And Pg3-Pg0 are simultaneously calculated and output to the 4-bit CLA unit 45. [

The 4-bit CLA unit 45 applies the group signals Gg3-Gg0 and Pg3-Pg0 output from the first through fourth CLA units 41-44 to Equation 5 through Equation 11 to determine the carry output The carry output C7 is fed to the carry input of the second CLA unit 42 and the carry output C7 is fed to the carry input of the third CLA unit 43 and the carry output C11 is fed to the carry- To the carry input terminal of the fourth CLA unit 44.

Therefore, the first CLA unit 41 applies the carry generation and transmission signals G3-G0, P3-P0 and the carry input Cin, which are combinations of input bits, to the above Equations 4 to 7, C0).

The second CLA unit 42 applies the carry generation and transmission signals G7-G4 and P7-P4, which are combinations of input bits, and the carry input C3 output from the CLA unit 45 to Equation (4) to Equation (7) And obtains the bit carry output (C6-C4).

The third CLA unit 43 applies the carry generation and transmission signals G11-G8 and P11-P8, which are combinations of input bits, and the carry input C7 output from the CLA unit 45, to Equation (4) to Equation (7) The bit carry output C10-C8 is obtained.

The fourth CLA unit 44 applies the carry generation and transmission signals G15-G12 and P15-P12, which are combinations of input bits, and the carry input C11 output from the CLA unit 45 to Equation (4) to Equation (7) And obtains the bit carry output (C14-C12).

That is, in the 16-bit carry calculation process, the carry generation and transmission signals G15-G0 and P15-P0, which are combinations of input bits, and the carry input Cin are inputted in parallel to obtain group signals Gg3-Gg0 and Pg3-Pg0, The last carry C15, C11, C7, C3 of each CLA block is obtained by using the signals Gg3-Gg0 and Pg3-Pg0, and the last carry C15, C11, C7, C3 of each CLA block is used as the carry input And the sub-carry of each CLA block is obtained at the same time.

FIG. 5 is a block diagram illustrating the expansion of the 16-bit CLA of FIG. 4 into a 64-bit CLA according to the first embodiment of the present invention.

Referring to FIG. 5, the carry generation and transfer signals G63-G0 and P63-P0, which are combinations of input bits in the first to fourth 16-bit CLA units 51-54, are applied to Equations (9) and The group signals Gg3-Gg0 and Pg3-Pg0 for obtaining the most significant carry output of each 16-bit CLA block are simultaneously obtained and then output to the 4-bit CLA unit 55. [

The 4-bit CLA unit 55 applies the group signals Gg3-Gg0 and Pg3-Pg0 output from the first through fourth CLA units 51-54 to Equation (5) to Equation (11) The carry output C15 to the carry input of the second CLA unit 52 and the carry output C31 to the carry input of the third CLA unit 53 and the carry output C47 To the carry input of the fourth CLA unit 54.

Accordingly, the first 16-bit CLA unit 51 applies the carry generation and transfer signals G15-G0, P15-P0 and the carry input Cin, which are combinations of input bits, to Equation (4) to Equation (7) (C14-C0).

The second 16-bit CLA unit 52 outputs the carry generation and transmission signals G31-G16 and P31-P16, which are combinations of input bits, and the carry input C15 output from the 4-bit CLA unit 55, To obtain the lower 15-bit carry output (C30-C16).

The third 16-bit CLA unit 53 receives the carry generation and transfer signals G47-G32 and P47-P32, which are combinations of input bits, and the carry input C31 output from the 4-bit CLA unit 55, To obtain the lower 15-bit carry output (C46-C32).

The fourth 16-bit CLA unit 54 outputs the carry generation and transmission signals G63-G48 and P63-P48, which are combinations of input bits, and the carry input C47 output from the 4-bit CLA unit 55, To obtain the lower 15-bit carry output (C62-C48).

In other words, the 64-bit carry-look-look-up combination of the input bits G63-G0 and P63-P0 and the carry input Cin are input in parallel to obtain the group signals Gg3-Gg0 and Pg3-Pg0, -Gg0, and Pg3-Pg0, and the most significant carry is input to the carry input of the next-stage CLA block, and the sub-carry of each CLA block is simultaneously obtained.

[Example 2]

When ANDing the carry generation and transfer signals G and P, which are combinations of inputs,

.

That is, since P is eliminated, the term is reduced to half. Using this property and expressing C3 of the above equation (8) as a common factor P3,

to be. In other words, P3 is not calculated every time, but it only needs to be calculated once.

Here, Ci = Pi * Hi, which is summarized for H

.

Here, H is a virtual carry distinguished from the actual carry, and if the virtual carry is expanded bit by bit,

.

If we obtain its general formula,

Which is the same as C3 = Gg + Pg * Cin in Equation (11). That is, knowing the H and P of the front end and the present G, the current H can be known.

Here, Hg = G3 + G2 + G1 * P1 + G0 * P1 * P2.

On the other hand, if the virtual carry is expanded bit by bit when the virtual carry input Hin is not 0,

.

In Equation 23,

In other words,

.

Equation (20) to Equation (22) is a pseudo Carry-Look Ahead (PCLA) structure for obtaining a virtual carry by inputting carry generation and transmission signals Gi and Pi, which are combinations of input bits, Equation (26) is a CLA structure for receiving a group signal Hg, Ig for obtaining a final virtual carry of each PCLA block and obtaining a final virtual carry of each PCLA block.

FIG. 7 is a 4-bit PCLA block diagram according to the second embodiment of the present invention. When the carry generation and transmission signals G3-G0, P2-P0, and Pin and the virtual carry input Hin, To calculate the group signals Hg and Ig for obtaining the lower 3-bit virtual carry H2-H0 and the upper virtual carry H3.

That is, in the 4-bit PCLA block of FIG. 7, since the final virtual carry output H3 can be obtained by knowing Hg, Ig and the virtual carry input Hin, only Hg and Ig are obtained without obtaining H3.

It can be seen that the virtual carriers H3 to H0 at each stage can be obtained simultaneously when the carry generation and transmission signals G3-G0, P2-P0, and Pin, and the virtual carry input Hin, which are combinations of input bits, are inputted.

This shows that the combination of Hg and Ig and Hin of the blocks bounded by several bits can know the virtual carry of each stage and the final stage.

That is, G and P for one bit and G and P for the whole 4 bits as knowing the virtual carry output by knowing the virtual carry input, and knowing the virtual carry output for the group, have.

In addition, since the number of PCLA blocks can be increased or decreased, various bits of adder can be configured even in the same structure.

FIG. 8 is a block diagram illustrating the expansion of the 4-bit PCLA of FIG. 7 to a 16-bit PCLA according to a second embodiment of the present invention.

Referring to FIG. 8, the first 4-bit PCLA unit 81 applies carry generation and transfer signals G3-G0, P2-P0, and Pin, which are combinations of input bits, to Equation 24 and Equation 25, To the 4-bit CLA unit 85. The 4-bit CLA unit 85 outputs the group signals Hg0 and Ig0 to the 4-

The second 4-bit PCLA unit 82 applies the carry generation and transmission signals G7-G4 and P6-P3, which are a combination of input bits, to the above-mentioned equations (24) and (25) to generate group signals Hg1 and Ig1 To the 4-bit CLA unit (85).

The third 4-bit PCLA unit 83 applies the carry generation and transmission signals G11-G8 and P10-P7, which are combinations of input bits, to the equations (24) and (25) to obtain group signals Hg2 and Ig2 To the 4-bit CLA unit (85).

The fourth 4-bit PCLA unit 84 applies the carry generation and transmission signals G15-G12 and P14-P11, which are combinations of the input bits, to the expressions 24 and 25 to obtain the group signals Hg3 and Ig3 To the 4-bit CLA unit (85).

That is, if the carry generation and transfer signals G15-G0, P14-P0, and Pin, which are combinations of input bits, are simultaneously input to the first to fourth PCLA units 84-81, the top virtual carries H15, H11, H7 , H3-Hg0, Ig3-Ig0 for obtaining H3 are simultaneously calculated and output to the 4-bit CLA unit 85.

The 4-bit CLA unit 85 applies the group signals Hg3-Hg0 and Ig3-Ig0 output from the first to fourth PCL units 84-81 to Equation 20 to Equation 26 to calculate the lower 3 bits of the virtual carry The virtual carry H3 is input to the virtual carry input terminal of the second PCLA unit 82 and the virtual carry H7 is input to the virtual carry input terminal of the third PCLA unit 83 after the virtual carry H11, H7, H3, The virtual carry H11 is output to the carry input of the fourth PCLA unit 84. [

Accordingly, the first PCLA unit 81 applies the carry generation and transmission signals G3-G0, P2-P0, and Pin, which are combinations of input bits, and the virtual carry input Hin to Equation (20) (H0-H2).

The second PCLA unit 82 applies the carry generation and transmission signals G7-G4 and P6-P3, which are combinations of input bits, and the virtual carry input H3 outputted from the CLA unit 85 to the above equations (20) to (22) 3-bit virtual carry (H6-H4) is obtained.

The third PCLA unit 83 applies the carry generation and transmission signals G11-G8 and P10-P7, which are combinations of input bits, and the virtual carry input H7 outputted from the LA unit 85 to the above equations (20) to (22) 3-bit virtual carry (H10-H8) is obtained.

The fourth PCLA unit 84 applies the carry generation and transmission signals G15-G12 and P14-P11, which are combinations of input bits, and the virtual carry input H11 outputted from the CLA unit 85 to the above equations (20) to (22) 3-bit virtual carry (H14-H12) is obtained.

That is, in the 16-bit virtual carry calculation process, the carry generation and transfer signals G15-G0, P14-P0, Pin and the virtual carry input Hin, which are combinations of input bits, are input in parallel and group signals Hg3-Hg0 and Ig3-Ig0 And the most significant virtual carry of each PCLA block is obtained by using the group signals Hg3-Hg0 and Ig3-Ig0. The highest virtual carry of each PCLA block is input to the virtual carry input of the next stage PCLA block, It is a parallel operation in which the lower virtual carry is obtained simultaneously.

FIG. 9 is a block diagram showing the 16 bit PCLA of FIG. 8 expanded to a 64 bit PCLA according to a second embodiment of the present invention.

Referring to FIG. 9, the carry generation and transmission signals G63-G0, P62-P0, and Pin, which are combinations of input bits in the first to fourth 16-bit PCLA units 91-94, And simultaneously outputs the group signals Hg3-Hg0 and Ig3-Ig0 for obtaining the most significant virtual carry of each 16-bit PCLA block to the 4-bit CLA unit 95.

The 4-bit CLA unit 95 applies the group signals Hg3-Hg0 and Ig3-Ig0 output from the first to fourth PCL units 91-94 to the above equations (20) to (26) The virtual carry H15 is transferred to the virtual carry input terminal of the second PCLA unit 92 and the virtual carry H31 is transferred to the virtual carry input terminal of the third PCLA unit 93 after obtaining the virtual carry H47, H31, H15 and the upper virtual carry H63, Carry H47 outputs to the virtual carry input of the fourth PCLA unit 94. [ Accordingly, the first PCLA unit 91 applies the carry generation and transfer signals G15-G0, P14-P0, and Pin, which are combinations of input bits, and the virtual carry input Hin to Equation (20) (H14-H0).

The second PCLA unit 92 applies the carry generation and transmission signals G31-G16 and P30-P15, which are combinations of input bits, and the virtual carry input H15 output from the 4-bit CLA unit 95, to Equations 20 to 22 To obtain the lower 15-bit virtual carry (H30-H16).

The third PCLA unit 93 applies the carry carry generation and transfer signals G47-G32 and P46-P31, which are combinations of input bits, and the virtual carry input H31 output from the 4-bit CLA unit 95 to Equation (20) to Equation To obtain the lower 15-bit virtual carry (H46-H32).

The fourth PCLA unit 94 applies the carry generation and transmission signals G63-G48 and P62-P47, which are combinations of input bits, and the virtual carry input H47 output from the 4-bit CLA unit 95 to the above equations (20) to To obtain the lower 15-bit virtual carry (H62-H48).

In other words, in the 64-bit virtual carry calculation process, the carry generation and transfer signals G63-G0, P62-P0, Pin and the virtual carry input Hin, which are combinations of input bits, are input in parallel and group signals Hg3-Hg0 and Ig3-Ig0 And the most significant virtual carry of each PCLA block is obtained by using the group signals Hg3-Hg0 and Ig3-Ig0. The highest virtual carry of each PCLA block is input to the virtual carry input of the next stage PCLA block, It is a parallel operation in which the lower virtual carry is obtained simultaneously.

In the first embodiment, 10 inputs and 20 inputs (since P and G are combinations of A and B, respectively) are required for the fan-in as in Equation (9) If the virtual carry Hg is obtained instead of the actual carry, it is reduced to 7 inputs and 14 inputs to 4 fans as shown in equation (24). Accordingly, as the input is reduced, the speed of the operation is reduced, the value as the load is reduced, and the area is also reduced.

On the other hand, the sum of the arithmetic operation results is expressed by Equation (4)

to be. here,

When a general formula is obtained,

to be. Thus, summing the sum again,

.

This implementation may be implemented using an exclusive OR gate and may be implemented using a multiplexer as in FIG.

Here, if Si = Psi and Hi- ₁ = 1 when Hi- ₁ = 0, Si = Pi- ₁ PSi, the value of Hi _-1 is used as the selection signal.

Where Pi (Ai + Bi) is Psi (Ai Bi), it is better to use Pi to get the imaginary carry and Psi to get the sum.

As described above, according to the fast adder using the virtual carry according to the present invention, the carry generation and transmission signals are generated by logically combining the binary input signals A and B, and the generated carry generation and transmission signals are logically combined, A group signal for obtaining a final carry of a block is generated, a final carry of each CLA block is obtained by a combination of a group signal and an initial carry input, and simultaneously, carries of each end and a final stage are simultaneously obtained, By combining the carry and carry, the operation speed can be improved by three times or more, and a high-speed adder can be implemented, and a high-speed calculation of a digital signal processor (DSP) becomes possible.

In addition, since the addition input bits can be easily changed, the expansion is good and the standard cell can be configured. Therefore, it is not necessary to interface with the standard cell and the design and implementation are facilitated. In addition, since it is not necessary to consider both 0s and 1s for the carry for each block, the total area of the adder is reduced, which facilitates the construction of a large bit adder.

Claims (3)

An adder having a pair of A and B bit inputs and a carry input, comprising: a carry generating / transfer signal generating unit for generating a carry generation signal and a transfer signal by logically combining binary input signal A and B bit inputs; And generates a group signal for obtaining a top virtual carriage of each virtual carriear head block by logically combining the carry generation signals output from the generation / transmission signal generation unit, and outputs a carry signal, N virtual carrieur head blocks each including at least one or more than one virtual carry look-ahead head block for obtaining a sub-virtual carry of each virtual carry lookahead block, and a logical combination of a group signal output from the N virtual carry look- To obtain the uppermost virtual carry of each virtual carrier head block, and then to the virtual carry input of the next virtual carry lookahead block And a high-order virtual carry generator for applying the high-order virtual carry generator to the high-speed adder. The high-speed adder according to claim 1, wherein the group signals (Hg, Ig) of the virtual carry lookahead block are divided into sections having no virtual carry (Hin) and sections having a virtual carry. The high-speed adder according to claim 1, wherein the upper virtual carry generating means comprises a carry lookahead block.