JPH0750709B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device.

(Prior Art) Generally, the wiring used in an LSI is divided into a power supply main line for supplying electric power to an element, a power supply branch line connecting the power supply main line and the element, and a signal line transmitting a signal between the elements. To be And these wires are usually aluminum (hereinafter,
Although it is made of a material whose main component is (also simply referred to as Al), there is also a material in which a part of a very short signal line is replaced with single crystal silicon, refractory metal, refractory metal silicide, or the like.

On the other hand, in the memory, a part of the diffusion layer may be used as a wiring, or polycrystalline silicon (a part of which is a refractory metal silicide) may be multilayered, and a part thereof may be used as a wiring. There are also wirings that use new materials such as copper (Cu).

Further, recent logic LSIs such as gate arrays and CPUs are formed by using two or more metal wiring layers in order to increase the degree of integration. FIG. 10 schematically shows the difference between a signal line, a power supply main line, and a power supply branch line by using a CMOS inverter circuit. In FIG. 10, reference numerals 104a and 104b are main power lines,
Reference numeral 105 indicates a power supply branch line, and reference numerals 106a and 106b indicate signal lines. A DC voltage is applied to the power main lines 104a and 104b and a power branch line 105 to flow a DC current, or the elements 101 and 102 are turned ON / OFF.
A direct current pulse current flows such that the current turns on and off with turning off, and generally the current flows in one direction. On the other hand, in the signal lines 106a and 106b, especially in a CMOS LSI, a bidirectional pulse current flows by charging and discharging a capacitive load. And the metal used for the multilayer wiring is
Only aluminum or its alloys, especially in the layout when using multilayer wiring, especially the power main line 104a, 1
The 04b and the signal lines 106a and 106b were not distinguished.

(Problems to be Solved by the Invention) When a current is applied to the Al wiring of such a conventional semiconductor device,
A so-called electromigration occurs, in which Al atoms move due to the applied current and lead to disconnection. Since this electromigration depends on the current density, it becomes more remarkable when the wiring is miniaturized. In order to prevent this, the wiring width of the power supply main line or the like through which a large current flows is generally wide. However, with the progress of miniaturization, it is necessary to increase the thickness of wirings that originally have to be finer in terms of integration degree such as signal lines and power supply branch lines, and especially in devices such as logic LSIs whose area is determined by wiring. There was the problem of not getting smaller.

The capacitance Cs per unit wiring length is determined by the wiring width W and the film thickness between the wiring 113 and the substrate 111 as shown in FIG. 11A when the wiring width is wide. As the wiring width W becomes narrower due to miniaturization, wiring 113 is formed as shown in FIG. 11 (b).
The capacitance Cs2 between the side surface of the substrate and the substrate 111 becomes important. LS
Although it is desirable to increase the film thickness between the wiring and the substrate in order to reduce the capacitance in order to increase the speed of I, it is generally difficult because it is a method that goes against the miniaturization of the device. Therefore, the capacitance is reduced by reducing the width and film thickness of the normal wiring. In order to achieve high integration in this way, the minimum size that can be processed is used as the size of the wiring of the signal line. However, when Al is used as the material of the wiring, there is a problem that the wiring dimension cannot be set to the minimum processable method due to electromigration. In addition,
It is possible to improve the electromigration resistance by using a material other than Al as the wiring material, but a material having high electromigration resistance, for example, a refractory metal such as tungsten, a refractory metal silicide, or the like,
Generally, the resistance is several orders of magnitude higher than that of Al. Therefore, it is difficult to use it for a signal line that causes a signal propagation delay, and there is a problem that it can be used only for a very short wiring.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device which can be highly integrated and has high performance and high reliability.

[Structure of Invention]

(Means for Solving the Problems) A semiconductor device according to a first aspect of the present invention includes: a power supply main line for supplying electric power to an element; and a first wiring that is a wiring other than the power supply main line and in which a unidirectional current flows. A second wiring in which a current flows in the opposite direction, and the electromigration resistance of the material forming the first wiring is higher than the electromigration resistance of the material forming the second wiring.

A second aspect of the invention is a semiconductor device having a multi-layer wiring having a power supply main line for supplying electric power to an element and a signal line for transmitting a signal between the elements, wherein at least one wiring layer is a signal through which an alternating current flows. It is characterized by being composed only of lines.

Furthermore, a third aspect of the present invention is a semiconductor device having a multi-layer wiring, which has a power source main line for supplying electric power to an element and a signal line for transmitting a signal between the elements, wherein at least one wiring layer is formed only from the power source main line. It is characterized in that the wiring layer consisting only of the power supply main line is formed on the wiring layer consisting of the signal line.

(Operation) According to the semiconductor device of the first aspect of the invention configured as described above, the first wiring in which a current flows in one direction is more resistant to electromigration than the second wiring in which a current flows in both directions. A highly flexible material is used.

On the other hand, according to the experimental results, the resistance to electromigration of the current flowing in both directions, that is, the alternating current flows, is about two orders of magnitude longer in life than the current flowing in one direction, that is, the current flowing in the direct current. About 1
Digit larger.

As a result, the semiconductor device according to the first aspect of the present invention can be highly integrated and have high performance and high reliability.

According to the semiconductor device of the second aspect of the invention configured as described above, at least one wiring layer is composed of only signal lines. As a result, this wiring layer can be made thinner than other wiring layers, the capacitance of this wiring layer can be reduced, and a high-speed and high-performance semiconductor device can be obtained. Further, by using the above wiring layer as the first wiring layer, fine processing is facilitated and the interlayer film is facilitated to be planarized, so that high integration of the semiconductor device can be achieved.

Further, according to the semiconductor device of the third invention configured as described above, at least one wiring layer is composed of only the power supply main line, and the wiring layer composed of only the power supply main line is composed of the signal line. Formed on. As a result, noise from the outside that adversely affects the signal propagating through the signal line is completely shielded by the power supply main line and the signal line is protected, so even if the power supply voltage drops due to high integration, the noise margin is reduced. Can be prevented, a high frequency signal can be used as a signal propagating through a signal line, and a high-performance and highly reliable semiconductor device can be obtained.

(Embodiment) A first embodiment of the semiconductor device according to the first invention will be described with reference to the formation of the CMOS inverter shown in FIGS.

Element regions 4 and 5 are formed in the N well 2 and P well 3 regions formed on the single crystal silicon substrate 1, respectively (see FIG. 1A). This is done by the selective oxidation method using a silicon nitride film that is usually used.
This can be achieved by forming a thick silicon oxide film in addition to 4,5. Next, on the element regions 4 and 5, for example, 15 nm
A gate oxide film is formed, impurities are introduced to obtain a desired threshold voltage, a polycrystalline silicon film is deposited on the entire surface, and phosphorus is introduced to make the polycrystalline silicon layer a conductor.
Thereafter, as shown in FIG. 1B, the polycrystalline silicon film is patterned to form the gate electrode 6. Then, boron is introduced to a portion of the element region on the N well 2 where the gate electrode 6 is not formed, and arsenic is introduced to a portion of the element region on the P well 3 where the gate electrode 6 is not formed. A source 7 and a drain 8 of the P-channel transistor and a source 9 of the N-channel transistor,
The drain 10 is formed (see FIG. 1 (b)).

After that, the first silicon oxide film 17 (FIG. 2 (a),
(See (b)) is deposited to a thickness of 1 μm, and the connection holes 7a, 9a and 8a, 10a for the sources 7, 9 and the drains 8, 10 are opened (see FIG. 1 (c)). Then, a material having a high electromigration resistance, for example, tungsten is deposited to a thickness of 1 μm on the entire surface and patterned to form power supply branch lines 11 and 12 and a signal line 13 as shown in FIG. Then, the silicon oxide film 18 is formed on the entire surface (see FIGS. 2A and 2B).
To a thickness of 1 μm to form connection holes 11a, 12a and 13a for the power supply branch lines 11, 12 and the signal line 13 and a connection hole 6a for the gate electrode (see FIG. 1 (e)). Next, the first Al is sputtered on the entire surface by 1 μm and then patterned to form the power supply main lines 14 and 15 and the signal line 16 (see FIG. 1 (f)).

The cross section taken along the line AA shown in FIG. 1 (f) is shown in FIG. 2 (a), and the cross section taken along the line BB is shown in FIG. 2 (b).
Shown in. An equivalent circuit of the CMOS inverter shown in FIG. 1 (f) is shown in FIG. In FIG. 3, reference numerals 11, 12 and 13 are power supply branch lines 11 and 12 and a signal line 13, respectively.

On the other hand, a signal line is a wiring for transmitting a signal between elements (for example, a drain of a certain element and a gate electrode of another element),
Since it has a connection portion with a miniaturized transistor and the number of transistors is very large, it should basically have the same size as the transistor. A bidirectional current, that is, an alternating current, flows through the CMOS signal line.
According to the drawing), the electromigration resistance of the wiring through which the alternating current flows is about two orders of magnitude longer in terms of life and about one order of magnitude larger than that of the wiring through which the direct current flows. That is, the width of the wiring through which the alternating current flows can be made larger by one digit than that of the wiring through which the direct current flows. Incidentally, the experimental data shown in FIG. 7, the ambient temperature T _emp
Is 250 ℃, current density J is 2.0 × 10 ⁶ A / cm ² , AC frequency f
Shows the result when is 1 KHz.

As described above, according to this embodiment, high integration and high speed can be achieved by using Al having low resistance and easy microfabrication for the signal line 16 through which alternating current flows. In addition, since tungsten that does not easily cause electromigration is used for the power supply branch lines 11 and 12 and the signal line 13 through which a pulsed DC current flows, miniaturization is possible and reliability is high. Power supply branch lines 11 and 12 and signal line 1
3 can be shortened and the resistance of tungsten (A
The voltage drop due to (about one digit higher than l) can be almost ignored and does not hinder the speedup.

On the other hand, in the power supply main line, a large direct current flows as the LSI is highly integrated, and the problem of electromigration becomes more serious. However, since the power supply main line does not have to be directly connected to the element, it is not necessary to miniaturize the power supply main line by devising the layer separately from other wiring. In this embodiment, Al is used, but the material is not specified.

A second embodiment of the semiconductor device according to the first invention will be described with reference to FIGS. 4 to 6.

Element regions 4 and 5 are formed in the N well 2 and P well 3 regions formed on the single crystal silicon substrate 1, respectively (FIG. 4A). This is done by the selective oxidation method using a silicon nitride film which is usually used.
Alternatively, it can be achieved by forming a thick silicon oxide film. Next, a 15 nm gate oxide film is formed on the element regions 4 and 5, impurities are introduced to obtain a desired threshold voltage, a polycrystalline silicon film is deposited on the entire surface, and phosphorus is introduced. The polycrystalline silicon layer is used as a conductor. Thereafter, as shown in FIG. 4B, the polycrystalline silicon film is patterned to form the gate electrode 6. Then, boron is introduced into a portion of the N well 2 where the gate electrode 6 is not formed, and arsenic is introduced into a portion of the P well 3 where the gate electrode 6 is not formed. , The source 7 and drain 8 of the P-channel transistor, and the source 9 and drain 10 of the N-channel transistor are formed (see FIG. 4B).

After that, a silicon oxide film 17 (see FIGS. 5 (a) and 5 (b)) is deposited on the entire surface to a thickness of 1 μm, and connection holes 8a and 10a with the drains 8 and 10 are opened (see FIG. 4 (c)). Then, a material having a high electromigration resistance, for example, tungsten is deposited to a thickness of 1 μm on the entire surface and patterned to form a signal line 13 as shown in FIG. 4 (d). Then, a silicon oxide film 18 (see FIGS. 5A and 5B) having a thickness of 1 μm is deposited on the entire surface to form a connection hole 13a with the signal line 13 and a connection hole 6 with the gate electrode.
a is formed (see FIG. 4 (e)). Next, Al is sputtered on the entire surface by 1 μm and then patterned to form the signal line 16 (see FIG. 4F).

Next, a silicon oxide film (not shown) is deposited on the entire surface of about 1 μm, and connection holes 7a and 9a for connecting to the sources 7 and 9 are opened. Next, dungsten is deposited and only the openings are filled with tungsten to form vertical wirings 21 and 22 of tungsten (see FIGS. 4 (g) and 5 (a) (b)). Then on the entire surface
Power line 24,25 by patterning after depositing Al film 1 μm
Are formed (see FIG. 4 (h)).

A cross section taken along line AA shown in FIG. 4 (h) is shown in FIG. 5 (a).
FIG. 5B shows a cross section taken along line BB. The equivalent circuit of the semiconductor device shown in FIG. 4 (h) is as shown in FIG. References 21, 22 and 1 shown in bold
3 are the power supply branch lines 21 and 22 and the signal line 13, respectively.

As described above, the power supply branch lines 21 and 22 and the signal line 13 through which the DC pulse current flows uses tungsten with high electromigration resistance, and the signal line 16 through which AC flows uses Al with low resistance and easy microfabrication. As a result, the semiconductor device of this embodiment can obtain the same effects as those of the first embodiment.

Although tungsten is used as the material having high electromigration resistance in the first and second embodiments, the same effect can be obtained by using other refractory metal, refractory metal silicide, or copper. it can.

Further, although Al is used for the main power lines 14, 15, 24 and 25, other conductive materials may be used.

Although the embodiment of FIGS. 1 and 2 shows the example of the CMOS inverter, it can be applied to other circuits such as NAND and NOR.

An embodiment of the semiconductor device according to the second invention will be described with reference to FIG.

When an LSI using multi-layer wiring is realized, the insulating film under each wiring layer needs to be flattened, so that the lower wiring layer is generally more suitable for thinning and miniaturization. Therefore, as shown in FIG. 8, the wiring of the first layer is thinned to such an extent that signal delay due to the resistance of the wiring does not pose a problem, and the wiring of only the signal line is formed by using the wiring of the minimum size determined by the processing limit. Set to 83 and do not wire the main power line. The resistance of aluminum wiring is sufficiently lower than the ON resistance of the transistor, so even if the film is thinned, the resistance does not matter. The power supply main line uses the second and subsequent wiring layers 84. The wiring layer 84 is made thick enough to withstand the electromigration of direct current. Of course, a signal line may be wired in this wiring layer 84.

As described above, according to the present embodiment, the signal line and the power supply main line are separated in the layout, so that the wiring layer used for the signal line can be made thinner than the power supply main line. As a result, the capacitance of the signal line can be reduced, and a high-speed and high-performance semiconductor device can be realized. Further, by using a thin signal line for the first wiring layer, fine processing is facilitated and the interlayer film is also easily planarized. This leads to improvement in the integration degree and yield of semiconductor devices.

In general, the life of wiring (MTF) due to electromigration is expressed by MTF∝J ^-2 exp (-Ea / kT). Here, J is the current density, Ea is the activation energy, K is the Boltzmann constant, and T is the absolute temperature. From the above-mentioned experimental results shown in FIG. 7, it is understood that the electromigration life of the wiring through which the alternating current flows is extended at least 100 times as long as the life of the wiring through which the direct current flows. From the above equation, this means that in a wiring structure optimized (thinned) by the life of AC pulse, if the current density of DC current is set to 1/10 or less of the current density of AC current, the life will be the same. ing. Therefore, if the current flowing through the signal line is not only an AC component but a DC component is superimposed on the AC component, set the DC current component to about 1/10 or less of the AC current. It is possible to obtain the same effect as that of the above embodiment.

Further, when a material other than aluminum (or an alloy thereof) can be used as the metal used for the multilayer wiring, different materials may be used for the signal line and the power supply line. An example of such a case is shown in FIG. In FIG. 9, aluminum is used for the signal line 93 through which the alternating current flows, and tungsten is used for the power supply main line 94. Here, it is desirable that the material of the signal line 93 has a resistance as low as possible even if the resistance to electromigration is low. This reduces the wiring capacity and increases the speed.
This is to realize the LSI. On the other hand, it is desirable to use a material having high electromigration resistance for the power supply main line 94. This is because a large current can be passed through the device within a limited area, and a high-speed and highly reliable LSI is realized. It is desirable to use aluminum or copper as the material of the signal line and a metal generally called refractory metal such as tungsten as the material of the power supply line. By doing so, it is possible to obtain the same effect as the above embodiment.

If the signal line and the power main line are made of different materials and the power line is made of a material having higher electromigration resistance than the signal line, the power main line can be miniaturized to improve the degree of integration. be able to.

An embodiment of the semiconductor device according to the third invention will be described with reference to FIG. In the semiconductor device of this embodiment, after forming a wiring layer including a power supply branch line 122 for supplying power to a plurality of elements formed in a P well 121a and an N well 121b on a semiconductor substrate, the signal lines 123a, 124a, Wiring layer consisting of 125a
123, 124, and 125 are sequentially formed, and the wiring layer 126 including the power supply main lines 126a and 126b is formed on these laminated wiring layers. The power supply main line 126a to which the high potential V _DD is added and the power supply main line 126b to which the ground potential V _SS is added are insulated by the insulating film 126c. And these power mains 126
The a and 126b are spread over the entire surface without patterning, except for the areas that need not be covered with the power main line, such as through holes, bonding pad portions, and areas for monitoring signals inside the semiconductor device. And the power mains 12
6a, 126b and the power supply branch line 122 are electrically connected by power supply branch lines 127a, 127b made of, for example, tungsten embedded in the through holes. Also, the signal line 123a and the signal line 12
4a is electrically connected by a signal line 128 made of, for example, tungsten embedded in the through hole.
23a and the power supply branch line 122 are electrically connected by a signal line 129 made of, for example, tungsten embedded in the through hole. The power supply branch line 122 is formed of a refractory metal or a noble metal silicide.

In general, as the degree of integration increases, that is, as devices become finer, the power supply voltage tends to decrease due to the problem of device reliability. This reduces the logical amplitude of the signal propagating through the signal line. Further, as the performance of the element is improved, a high frequency signal is used as a signal propagating through the signal line. The decrease in the logic amplitude and the increase in the frequency of the signal described above reduce the margin against external noise.

However, as described above, in the embodiment of the semiconductor device of the third invention, the wiring layer 126 composed of the power main line is formed separately on the stacked wiring layers 123, 124 and 125 composed of the signal line,
Each of the signal lines 123a, 124a, 125a has a structure covered by power supply main lines 126a, 126b. This allows the signal line 12
External noise that adversely affects the signals propagating through 3a, 124a, and 125a is completely shielded by the power main lines 126a and 126b to protect the signal lines, so that the power supply voltage decreases with high integration. It is possible to prevent a decrease in noise margin, a high frequency signal used for a high performance element can be used as a signal for transmitting a signal line, and a high performance and highly reliable semiconductor device can be obtained.

Further, since the power supply main lines 126a and 126b are not patterned except for a predetermined region and are spread over the entire surface, the power supply main lines 126a and 126b are not patterned.
It is possible to increase the film thickness of 26b, which allows the semiconductor device of the third embodiment of the present invention to realize a power supply main line having extremely high electromigration resistance as compared with the conventional semiconductor device.

Further, when connecting the power source to the element, the power source main lines 126a and 126b may be connected to the element by power source branch lines 127a and 127b made of, for example, tungsten and embedded in the through-home as shown in FIG. As a result, in the layout of the semiconductor device, only the signal line and the through hole need be considered, and the layout is easier and the degree of freedom in design is increased as compared with the conventional semiconductor device in which the power main line and the signal line are in the same layer. The effect of doing is obtained.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a highly integrated semiconductor device with high integration and high performance.

[Brief description of drawings]

1 is a plan view of a first embodiment of a semiconductor device according to the first invention, FIG. 2 is a sectional view of the semiconductor device of the first embodiment shown in FIG. 1, and FIG. 3 is FIG. FIG. 4 is an equivalent circuit diagram of the semiconductor device of the first embodiment shown in FIG. 4, FIG. 4 is a plan view of the second embodiment of the semiconductor device according to the first invention, and FIG. 5 is a second embodiment shown in FIG. FIG. 6 is a cross-sectional view of an example semiconductor device, FIG. 6 is an equivalent circuit diagram of the semiconductor device of the second embodiment shown in FIG. 4, and FIG. 7 is electromigration resistance in the case of conducting an alternating current and a direct current in wiring. FIG. 8 is a sectional view showing an embodiment of a semiconductor device according to the second invention, FIG. 9 is a sectional view showing another embodiment of the semiconductor device according to the second invention, and FIG. The figure shows the circuit diagram of the CMOS inverter,
FIG. 11 is a diagram for explaining wiring and capacitance, and FIG. 12 is a sectional view showing an embodiment of a semiconductor device according to the third invention. 1 ... Single crystal silicon substrate, 2 ... N well, 3 ... P
Wells, 4, 5 ... Element area, 6 ... Gate electrode, 6a ...
Gate electrode connection hole, 7,9 …… source, 7a, 9a …… source connection hole, 8,10 …… drain, 8a, 10a …… drain connection hole,
11,12 …… Power supply branch line, 11a, 12a …… Power supply branch line connection hole, 13,1
6 …… Signal line, 13a …… Connection hole, 14,15 …… Main power line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhisa Hatanaka 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Toshiba Corporation Tamagawa Plant (56) References JP-A-64-39042 (JP, A)

Claims (7)

[Claims] 1. A power supply main line for supplying electric power to an element, a wiring other than the power supply main line, in which a current flows in one direction, and a second wiring in which current flows in both directions. A semiconductor device, wherein the electromigration resistance of the material forming the first wiring is higher than the electromigration resistance of the material forming the second wiring. 2. The semiconductor device according to claim 1, wherein the second wiring is made of a material having a resistance lower than that of the first wiring. 3. The semiconductor device according to claim 1, wherein the second wiring is made of a material containing aluminum as a main component. 4. The semiconductor device according to claim 1, wherein the first wiring is made of a material containing one of refractory metal and refractory metal silicide as a main component. . 5. A multi-layer wiring semiconductor device having a power supply main line for supplying electric power to an element and a signal line for transmitting a signal between the elements, wherein at least one wiring layer is composed of only the signal line. The semiconductor device is characterized in that the wiring layer formed only of signal lines for transmitting signals between elements has a lower resistivity than the other wiring layers. 6. A multilayered semiconductor device having a power supply main line for supplying electric power to an element and a signal line for transmitting a signal between the elements, wherein at least one wiring layer is composed of only the power supply main line. The wiring layer consisting only of the power supply main line is formed on the wiring layer consisting of the signal line, and the electromigration resistance of the material forming the power supply main line is higher than the electromigration resistance of the material forming the signal line. A semiconductor device characterized by high price. 7. The semiconductor device according to claim 6, wherein an entire surface of the wiring layer formed only of the power main line is covered by the power main line except a predetermined region.