JPH0748526B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an improvement in a method of manufacturing a semiconductor memory device having a capacitor for storing information, which is suitable as a dynamic random access memory.
To the extent that it is needed to form a gate transistor, and to form an information storage capacitor,
In addition, for the purpose of facilitating its manufacture and having good flatness, a step of bonding a first substrate and a semiconductor plate to be an active layer, and then exposing the semiconductor plate And selectively forming a recess on the exposed main surface, and then forming one electrode of the information storage capacitor on the exposed main surface of the semiconductor plate including the inside of the recess. Next, a step of forming an inter-element isolation insulating film that makes one electrode of the information storage capacitor independent, and then, a dielectric film and at least one electrode of the information storage capacitor of the dielectric film and the information storage capacitor. A step of sequentially forming the other electrode, a step of forming a planarizing film over the entire surface of the information storage capacitor including the other electrode, and
A step of adhering a second substrate on the flattening film, and then removing the first substrate to expose the semiconductor plate that is the active layer to one electrode of the information storage capacitor. Forming a transistor having an impurity region to contact, or instead of forming a recess filled with a portion of one electrode of the information storage capacitor, an electrode is formed on the semiconductor plate. A contact region is formed, the periphery thereof is covered with an insulating film, and the electrode contact region and one electrode of the information storage capacitor are in contact with each other.

[Industrial application field]

The present invention has a capacitor for information storage, and a dynamic random access memory (dynamic random access memory).
s memory: DRAM) and an improved method of manufacturing a semiconductor memory device.

At present, when the DRAM is highly integrated, the configuration of the information storage capacitor is a factor for improving the degree of integration. That is, the capacity is maintained at the same level as the conventional one, and
The area occupied by the cell must be reduced.

[Conventional technology]

In recent years, in DRAM, it has been a limit in terms of occupied area to form an information storage capacitor like a transfer gate transistor on a plane, so that the occupied area viewed on a plane can be reduced and the capacitance can be reduced. In order to maintain it, for example, the dielectric film can be thinned and a high-dielectric material can be used. In addition, while maintaining a small occupied area in plan view, a trench structure or a laminated structure can be formed. It is also practiced to increase the substantial area.

[Problems to be Solved by the Invention]

Regarding the above-mentioned conventional technique, with respect to, at present, the dielectric film thickness is about to fall below 100 (Å), and it is already reaching the physical limit. So far, there is no material superior to silicon dioxide (SiO ₂ ) film, there is a problem in cleaning in trench, uniform oxidation, filling, etc. Each has its own problems, such as the number reaching the limit.

The present invention has a planar memory cell occupying area that is required to form a transistor gate transistor, and an information storage capacitor that can be formed and is easy to manufacture. In addition, the flatness is to be good.

[Means for Solving the Problems]

In the method for manufacturing a semiconductor memory device according to the present invention, a step of bonding a first substrate (for example, glass substrate 1) and a semiconductor plate (for example, p-type single crystal silicon semiconductor plate 2) to be an active layer to each other , And then selectively etch the exposed main surface of the semiconductor plate to form a recess (eg, recess 2A)
And a step of forming one electrode (for example, one electrode film 4) of the information storage capacitor on the exposed main surface of the semiconductor plate including the inside of the recess, and then the information storage. Forming an inter-element isolation insulating film (for example, inter-element isolation insulating film 7) that makes one electrode of the storage capacitor independent, and then forming a dielectric film (for example, a dielectric film) on at least one electrode of the information storage capacitor. Film 8) and the other electrode (for example, the other electrode film 9) of the information storage capacitor in this order, and then a flattening film (for example, a flat film) is formed on the entire surface including the other electrode of the information storage capacitor. A step of forming a film 10), then a step of adhering a second substrate (for example, a silicon semiconductor substrate 11) on the planarization film, and then removing the first substrate to form the active layer. A semiconductor And exposing a plate to form a transistor having an impurity region (for example, n ⁺ type drain region 16) contacting one electrode of the information storage capacitor, or Among them, the steps relating to the formation of the recess (for example, the recess 2A) and the formation of one electrode (for example, one electrode film 4) of the information storage capacitor are performed by selectively removing impurities on the exposed main surface of the semiconductor plate. A step of forming an electrode contact region (for example, an n ⁺ type electrode contact region 4A) by introducing, and then a step of forming an insulating film (for example, an insulating film 21 made of silicon dioxide) over the entire surface of the electrode contact region except the surface. And then forming one electrode (for example, one electrode film 4) of the information storage capacitor that contacts the electrode contact region and extends on the insulating film. That.

[Action]

By adopting the above means, it is possible to obtain a semiconductor memory device in which an information storage capacitor exists directly below a transfer gate transistor, and therefore, the memory cell is
Since it occupies about one transfer gate transistor area in a plan view, it is significantly smaller than the conventional one, and the capacity of the information storage capacitor is sacrificed. There is no. However, the manufacturing process is slightly increased, but since the content is only a sufficiently matured technology, there is no difficulty in implementing it.

〔Example〕

FIGS. 1 to 19 are side sectional views of a main part of a semiconductor memory device in a process key point for explaining an embodiment of the present invention.
Hereinafter, a detailed description will be given with reference to these drawings.

See FIG. 1 1- (1) For example, a p-type single crystal silicon semiconductor plate 2 is attached to a glass substrate 1. As this sticking technique, for example, an oxide film is formed on the surfaces of the glass substrate 1 and the p-type single crystal silicon semiconductor plate 2, and the surfaces of the oxide films are made to face each other and adhered to each other. [Celsius] to 1000 [degC] can be applied for joining technology (if necessary, edited by Seijiro Furukawa, published by Sangyo Tosho Co., Ltd., "SOI Structure Forming Technology" No. 197)
See pages 200 to 200).

1- (2) By applying an appropriate polishing method, polishing for reducing the thickness of the silicon semiconductor plate 2 is performed, for example, 5000
Set to about [Å]. The thickness may be selected appropriately.

1- (3) For example, reactive ion etching
ng: RIE) method to apply silicon semiconductor plate 2
A through hole (not shown) serving as an alignment mark is formed at an appropriate position. This through hole is particularly effective for confirming the position of one electrode film 4 in the information storage capacitor formed later.

See FIG. 2 2- (1) By applying a resist process in photolithography technology, a photoresist film 3 having an opening on the exposed surface of the silicon semiconductor plate 2 is formed.

2- (2) By applying the RIE method using a chlorine-based gas such as CCl ₄ as an etching gas, the silicon semiconductor plate 2 is selectively etched using the photoresist film 3 as a mask to form the recess 2A. To form.

The depth of the recess 2A may be, for example, half the depth of the silicon semiconductor plate 2, that is, about 2500 [Å].

Refer to FIG. 3. 3- (1) Impurity-containing polycrystal having a thickness of, for example, about 2000 [Å] on the silicon semiconductor plate 2 by applying the chemical vapor deposition (CVD) method. One electrode film 4 of the information storage capacitor made of silicon is formed. With this thickness, the recess 2A is completely filled and the surface can be made substantially flat.

As the impurities in the electrode film 4 made of the impurity-containing polycrystalline silicon, for example, As is used, so that the conductivity type is n-type, and the impurity concentration is, for example, 4 ×.
It is preferably about 10 ¹⁵ [cm ⁻³ ] or more.

See Fig. 4 4- (1) By applying the CVD method, the thickness is, for example, about 1000.
A silicon nitride (Si ₃ N ₄ ) film 5 having a thickness of about [Å] is formed.

Since this Si ₃ N ₄ film 5 is used as an oxidation resistant mask, it is sufficient to select a thickness according to its purpose.
As the base, it is optional to form an extremely thin SiO ₂ film as usual.

See FIG. 5 5- (1) A photolithography film 6 covering a capacitor formation planned region is formed by applying a resist process in a normal photolithography technique.

See FIG. 6 6- (1) The Si ₃ N ₄ film 5 is patterned using the photoresist film 6 as a mask by applying the RIE method using a fluorine-based gas such as CF ₄ as an etching gas.

See Fig. 7 7- (1) By applying the local oxidation of silicon (LOCOS) method using the Si ₃ N ₄ film 5 as an oxidation resistant mask, the thickness is, for example, 2500 [Å] An insulating film for element isolation 7 made of SiO ₂ is formed.

See FIG. 8 8- (1) For example, the Si ₃ N ₄ film 5 used as the oxidation resistant mask is removed by applying a dipping method using phosphoric acid as an etchant.

8- (2) For example, by applying a thermal oxidation method, a thickness of 10
A dielectric film 8 of an information storage capacitor made of SiO _{2 of} about 0 [Å] is formed.

See FIG. 9 9- (1) By applying the CVD method, the other electrode film 9 is formed in the information storage capacitor made of polycrystalline silicon having a thickness of, for example, about 2000 [Å]. The electrode film 9 is
It is usually called a cell plate.

It is necessary that the electrode film 9 be made of polycrystalline silicon containing impurities from the beginning, or be made conductive by implanting impurity ions after forming the polycrystalline silicon film.

See FIG. 10 10- (1) A flattening film 10 made of SiO _{2 having} a thickness of, for example, about 4000 [Å] is formed by applying the CVD method. Since the flattening film 10 is formed to eliminate unevenness,
It is necessary to make the thickness suitable for the purpose. Further, the material is not limited to SiO ₂ , but may be, for example, a metal, and in that case, a vacuum deposition method or the like is applied.

10- (2) The flattening film 10 is polished so as to be close to a mirror surface by applying an appropriate polishing method.

See FIG. 11 11- (1) The silicon semiconductor plate 11 is bonded to the flattening film 10 by applying the bonding method. The substrate to be bonded is not limited to the silicon semiconductor substrate.

See FIG. 12 12- (1) The glass substrate 1 is removed by etching by applying a dipping method using hydrofluoric acid as an etchant.

As a result, the silicon semiconductor plate 2 having a flat surface appears. The technique applied here is not limited to the dipping method, and an appropriate technique such as a dry etching method and a polishing method can be adopted.

See Fig. 13 13- (1) By applying ordinary silicon selective thermal oxidation method,
On the surface of the silicon semiconductor plate 2, an element isolation insulating film 12 made of SiO ₂ having a thickness of, for example, about 2500 [Å] is formed. Incidentally, the active region generated by this substantially faces the information storage capacitor. After that, the silicon semiconductor plate 2
The element is built in, but in this case, the process 1-
The through hole for alignment formed in (3) will be useful.

13- (2) By removing the oxidation resistant mask and the like when the element isolation insulating film 12 is formed to expose the active region of the silicon semiconductor plate 2 and then applying the thermal oxidation method, For example 100
A gate insulating film 13 made of SiO _{2 of} about [Å] is formed.

See FIG. 14 14- (1) By applying the CVD method, a polycrystalline silicon film having a thickness of, for example, 2000 [Å] and a tungsten silicide film having a thickness of, for example, 2000 [Å] are laminated, Polycide (po
lycide) film is formed.

14- (2) By applying the RIE method, the polycide film is patterned to form the gate electrode 14 of the transfer gate transistor.

See FIG. 15 15- (1) By applying the ion implantation method, the dose amount is, for example, about 4 × 10 ¹⁵ [cm ⁻² ], and the acceleration energy is, for example,
As ions are implanted at about 70 [KeV] to form the n ⁺ type source region 15 and the n ⁺ type drain region 16.

The n ⁺ type drain region 16 is adapted to come into contact with the protruding portion of the electrode film 4 which is one of the electrodes of the information storage capacitor located therebelow.

See Fig. 16 16- (1) Si that covers the gate electrode 14 by applying the thermal oxidation method.
An insulating film 17 made of O ₂ is formed.

If an LDD (lightly doped drain) structure is adopted, in step 15- (1), a low impurity concentration shallow diffusion is performed to form an n ⁻ type source region and an n ⁻ type drain region. to, may sidewall film made of SiO ₂ is formed on both sides of the gate electrode 14, then forming the n ⁺ -type drain region in contact with n ⁺ -type source regions and the electrode film 4 by performing a deep diffusion of high impurity concentration .

See Fig. 17 17- (1) By applying the CVD method, an interlayer insulating film made of PSG (phosphosilicate glass) having a thickness of, for example, about 10000 [Å].
Forming 18.

17- (2) Interlayer insulating film 18
And the gate insulating film 13 is selectively etched to form the bit line contact window 18A.

See FIG. 18 18- (1) By applying the vacuum evaporation method, an aluminum (Al) film having a thickness of 0.8 [μm] is formed in contact with the n ⁺ type source region 15. Here, the selective CVD method may be applied to perform selective growth of W for planarization.

18- (2) The bit line 19 is formed by patterning the Al film by applying a normal photolithography technique.

See FIG. 19 19- (1) By applying the CVD method, the cover film 20 made of PSG having a thickness of, for example, about 1 [μm] is formed.

In the semiconductor memory device manufactured by adopting the above-described steps, the information storage capacitor is present immediately below the transfer gate transistor, so that the area occupied by the plane is particularly required. do not do.

In addition, although the element isolation insulating films 7 and 12 are separated from each other in the above-described embodiment, the heat treatment time for forming them is appropriately selected, or the thickness of the semiconductor plate 2 is appropriately selected. By doing so, the element isolation insulating films 7 and 12 can be bonded to each other, and when the structure is adopted, the breakdown voltage of the semiconductor memory device is increased.

20 to 35 are sectional side views of a main part of a semiconductor memory device in a process key point for explaining another embodiment of the present invention. Hereinafter, with reference to these drawings, FIG. explain.

See FIG. 20 20- (1) For example, a p-type single crystal silicon semiconductor plate 2 is attached to a substrate 1'made of, for example, silicon dioxide. To perform this attachment, for example, an oxide film is formed on the surface of the p-type single crystal silicon semiconductor plate 2, and the surface of the oxide film and the substrate 1'are brought into close contact with each other and brought into close contact with each other in an oxidizing atmosphere. 800 (° C) ~ 100
The heat treatment may be performed at 0 [° C].

20- (2) By applying an appropriate polishing method, polishing for reducing the thickness of the silicon semiconductor plate 2 is performed, for example, 5000
Set to about [Å].

20- (3) For example, reactive ion etching
ng: RIE) method to apply silicon semiconductor plate 2
A through hole (not shown) serving as an alignment mark is formed at an appropriate position. This through hole is particularly effective for confirming the position of one electrode film 4 in the information storage capacitor to be formed later, as described in the description of the above embodiment.

See FIG. 21 21- (1) By applying a resist process in the photolithography technique, a photoresist film 3 having an opening on the exposed surface of the silicon semiconductor plate 2 is formed.

21- (2) By applying the ion implantation method, the dose amount is, for example, 4 × 10 ¹⁵ [cm ⁻² ], and the acceleration energy is, for example, 70 [Ke.
V] is implanted with As ions to form the n ⁺ type electrode contact region 4A.

In this case, the depth of the n ⁺ -type electrode contact region 4A is, for example, half the depth of the silicon semiconductor plate 2, that is, 2500.
It may be about [Å], and since the activation annealing is not performed here, the n ⁺ type electrode contact region 4A which can be actually operated is formed in a later step.

See Fig. 22 22- (1) Photoresist film 3 used as a mask for ion implantation
Then, for example, by covering the surface of the n ⁺ type electrode contact region 4A with a silicon nitride film and applying the LOCOS method using the silicon nitride film as an oxidation resistant mask, a thickness of, for example, 500 (Å) An insulating film 21 made of silicon dioxide is formed. Incidentally, it is optional to interpose an extremely thin silicon dioxide film under the silicon nitride film which is an oxidation resistant mask. Further, the insulating film 21 can be replaced with a silicon dioxide film formed by the CVD method.

22- (2) By removing the silicon nitride film used as the oxidation resistant mask and applying the CVD method,
One electrode film 4 of the information storage capacitor made of impurity-containing polycrystalline silicon having a thickness of about 000 [Å] is formed.

As the impurities in the electrode film 4 made of the impurity-containing polycrystalline silicon, for example, As is used, so that the conductivity type is n-type, and the impurity concentration is, for example, 4 ×.
It is preferably about 10 ¹⁵ [cm ⁻³ ] or more.

See Fig. 23 23- (1) By applying the LOCOS method, for example, the thickness is 2500 [Å]
An insulating film for element isolation 7 made of SiO ₂ is formed.

See FIG. 24 24- (1) For example, by applying the thermal oxidation method, the dielectric film 8 of the information storage capacitor made of SiO ₂ having a thickness on the electrode film 4 of, for example, about 100 [Å]. To form. Needless to say, the dielectric film 8 is thin on the insulating film 7 for separating elements.

See FIG. 25 25- (1) By applying the CVD method, the other electrode film 9 is formed in the information storage capacitor made of polycrystalline silicon having a thickness of, for example, about 2000 [Å]. The electrode film 9 is
It is usually called a cell plate, and the electrode film 9 contains impurities during growth, or
It is the same as in the above-described embodiment that it is necessary to make the film conductive by implanting impurity ions after forming the polycrystalline silicon film.

See FIG. 26 26- (1) By applying the CVD method, the flattening film 10 made of SiO _{2 having} a thickness of, for example, about 4000 [Å] is formed. The material of the flattening film 10 is not limited to SiO ₂ as in the above embodiment, but may be metal, for example, in which case the vacuum deposition method or the like is applied.

26- (2) The flattening film 10 is polished so as to be close to a mirror surface by applying an appropriate polishing method.

See FIG. 27 27- (1) The silicon semiconductor substrate 11 is bonded to the flattening film 10 by applying the bonding method. The substrate to be bonded is not limited to the silicon semiconductor substrate.

See FIG. 28 28- (1) The substrate 1 ′ made of silicon dioxide is etched and removed by applying a dipping method using an HF-based etchant as an etchant.

As a result, the silicon semiconductor plate 2 having a flat surface appears. The technique applied here is not limited to the dipping method, and an appropriate technique such as a dry etching method and a polishing method can be adopted.

See Fig. 29. 29- (1) By applying the normal silicon selective thermal oxidation method,
On the surface of the silicon semiconductor plate 2, an element isolation insulating film 12 made of SiO ₂ having a thickness of, for example, about 2500 [Å] is formed. Incidentally, the active region generated by this substantially faces the information storage capacitor. After that, the silicon semiconductor plate 2
In this case, the device is built in, but in this case, process 20-
The through hole for alignment formed in (3) will be useful.

29- (2) By removing the oxidation resistant mask when the element isolation insulating film 12 is formed to expose the active region of the silicon semiconductor plate 2 and applying the thermal oxidation method, For example 100
A gate insulating film 13 made of SiO _{2 of} about [Å] is formed.

See FIG. 30. 30- (1) By applying the CVD method, a polycrystalline silicon film having a thickness of about 2000 [Å] and a tungsten silicide film having a thickness of about 2000 [Å] are laminated, Polycide (po
lycide) film is formed.

30- (2) By applying the RIE method, the polycide film is patterned to form the gate electrode 14 of the transfer gate transistor.

See FIG. 31 31- (1) By applying the ion implantation method, the dose amount is, for example, about 4 × 10 ¹⁵ [cm ⁻² ], and the acceleration energy is, for example,
As ions are implanted at about 70 [KeV] to form the n ⁺ type source region 15 and the n ⁺ type drain region 16.

The n ⁺ type drain region 16 is in contact with the n ⁺ type electrode contact region 4A which is integrated with the electrode film 4 which is one electrode of the information storage capacitor located below the n ⁺ type drain region 16.

See Fig. 32 32- (1) Si covering the gate electrode 14 by applying the thermal oxidation method
An insulating film 17 made of O ₂ is formed.

If the LDD structure is adopted, in step 31- (1), a low impurity concentration shallow diffusion is performed to form an n ⁻ type source region and an n ⁻ type drain region, and then the gate electrode 14 is formed. of the side wall film made of SiO ₂ is formed on both sides, then it is preferable to form the n ⁺ -type drain region in contact with n ⁺ -type source regions and n ⁺ -type electrode contact region 4A by performing a deep diffusion of high impurity concentration.

See FIG. 33 33- (1) By applying the CVD method, the interlayer insulating film 18 made of PSG having a thickness of, for example, about 10,000 [Å] is formed.

33- (2) Interlayer insulating film 18 is formed by ordinary photolithography technology.
And the gate insulating film 13 is selectively etched to form the bit line contact window 18A.

See FIG. 34 34- (1) By applying the vacuum evaporation method, an Al film having a thickness of 0.8 [μm], for example, which contacts the n ⁺ type source region 15 is formed. Here, the selective CVD method may be applied to perform selective growth of W for planarization.

34- (2) The bit line 19 is formed by patterning the Al film by applying a normal photolithography technique.

See FIG. 35 35- (1) By applying the CVD method, the cover film 20 made of PSG having a thickness of, for example, about 1 [μm] is formed.

In the semiconductor memory device manufactured by the steps described above, the electrode film 4 and the n ⁺ type source region 15 are close to each other because the insulating film 21 exists even if the semiconductor plate 2 is thin. There is no danger that they will pass each other and affect each other, or that a short circuit will occur.

Also, in this embodiment, the element isolation insulating films 7 and 12 are separated from each other, but it is easy to bond the element isolation insulating films 7 and 12 to each other. The withstand voltage of the storage device is increased.

〔The invention's effect〕

In the method for manufacturing a semiconductor memory device according to the present invention, the information storage capacitor is formed on the back surface side of the semiconductor layer which is the active layer, and the normal transistor is formed on the front surface side of the semiconductor layer. ing.

By adopting the above configuration, a semiconductor memory device in which the information storage capacitor exists directly below the transfer gate transistor can be obtained, and therefore the memory cell is
Since it occupies about one transfer gate transistor area in a plan view, it is significantly smaller than the conventional one, and the capacity of the information storage capacitor is sacrificed. There is no. However, the manufacturing process is slightly increased, but since the content is only a sufficiently matured technology, there is no difficulty in implementing it.

[Brief description of drawings]

1 to 19 are sectional side views of essential parts of a semiconductor memory device in process steps for explaining one embodiment of the present invention, and FIGS. 20 to 35 are other embodiments of the present invention. 3A and 3B respectively show side sectional views of a main part of a semiconductor memory device in process steps for explaining an example. In the figure, 1 is a glass substrate, 2 is a p-type single crystal silicon semiconductor plate, 2A is a recess, 3 is a photoresist film, 4 is one electrode film of an information storage capacitor, 4A is an electrode contact region, 5 is a Si ₃ N ₄ film which is an oxidation resistant mask, 6 is a photoresist film, 7 is an element isolation insulating film made of SiO ₂ ,
8 is a dielectric film made of SiO ₂ , 9 is the other electrode film of the information storage capacitor, 10 is a flattening film made of SiO ₂ , 11 is a silicon semiconductor substrate, 12 is an element isolation insulating film made of SiO ₂ ,
A gate insulating film made of SiO ₂ is 13, the gate electrode is made of a polycide 14, 15 n ⁺ -type source region, the n ⁺ -type drain region 16, 17 made of SiO ₂ insulating films, 18 of SiO ₂ Is an interlayer insulating film, 19 is a bit line, 20 is a cover film, and 21 is an insulating film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/108

Claims (2)

[Claims] 1. A step of laminating a first substrate and a semiconductor plate to be an active layer, and a step of selectively etching an exposed main surface of the semiconductor plate to form a recess. Next, a step of forming one electrode of the information storage capacitor on the exposed main surface of the semiconductor plate including the inside of the recess, and then isolation insulation between elements for making one electrode of the information storage capacitor independent A step of forming a film, a step of sequentially forming a dielectric film and the other electrode of the information storage capacitor on at least one electrode of the information storage capacitor, and then the other of the information storage capacitor Forming a flattening film over the entire surface including the electrodes, then adhering a second substrate on the flattening film, and then removing the first substrate to form the active layer. Semiconductor plate And forming a transistor having an impurity region in contact with one electrode of the information storage capacitor, the method for manufacturing a semiconductor memory device. 2. A step of bonding a first substrate and a semiconductor plate to be an active layer, and then selectively introducing impurities into the exposed main surface of the semiconductor plate to form an electrode contact region. And a step of forming an insulating film on the entire surface of the electrode contact region except the surface thereof, and then one electrode of the information storage capacitor which is in contact with the electrode contact region and extends on the insulating film. And a step of forming an inter-element isolation insulating film that makes one electrode of the information storage capacitor independent, and then a dielectric film and the dielectric film on at least one electrode of the information storage capacitor. A step of sequentially forming the other electrode of the information storage capacitor, a step of forming a flattening film over the entire surface including the other electrode of the information storage capacitor, and a step of forming the flattening film. A step of bonding a second substrate on the carrier film, and then removing the first substrate to expose the semiconductor plate which is the active layer and contact one electrode in the information storage capacitor. And a step of forming a transistor having an impurity region to perform the manufacturing of the semiconductor memory device.