JPH0748411B2 - Function trimming method for hybrid integrated circuit - Google Patents

Function trimming method for hybrid integrated circuit

Info

Publication number
JPH0748411B2
JPH0748411B2 JP63033462A JP3346288A JPH0748411B2 JP H0748411 B2 JPH0748411 B2 JP H0748411B2 JP 63033462 A JP63033462 A JP 63033462A JP 3346288 A JP3346288 A JP 3346288A JP H0748411 B2 JPH0748411 B2 JP H0748411B2
Authority
JP
Japan
Prior art keywords
trimming
circuit
chip resistor
chip
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63033462A
Other languages
Japanese (ja)
Other versions
JPH01194301A (en
Inventor
徳保 寺沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63033462A priority Critical patent/JPH0748411B2/en
Publication of JPH01194301A publication Critical patent/JPH01194301A/en
Publication of JPH0748411B2 publication Critical patent/JPH0748411B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は配線基板上に抵抗素子を含む各種回路部品を
実装して成る混成集積回路を対象に、その回路特性の調
整を行う抵抗の機能トリミング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is directed to a hybrid integrated circuit formed by mounting various circuit components including a resistance element on a wiring board, and the function of a resistor for adjusting the circuit characteristics thereof. Regarding trimming method.

〔従来の技術〕[Conventional technology]

この種の混成集積回路では、個々の素子の特性バラツキ
が原因で所望の電気的特性の得られないことがある。こ
の場合には混成集積回路を組立てた状態でその回路の電
気的特性を測定しながら抵抗素子の抵抗値を調整して回
路特性が所望値となるようにする機能トリミング方法が
一般に実施されている。
In this type of hybrid integrated circuit, desired electrical characteristics may not be obtained due to variations in characteristics of individual elements. In this case, a function trimming method is generally carried out in which the hybrid integrated circuit is assembled and the electrical characteristics of the circuit are measured while adjusting the resistance value of the resistance element so that the circuit characteristic becomes a desired value. .

かかる機能トリミング方法は、配線基板上に各種電子部
品を実装して混成集積回路を組立てた状態でサンドトリ
マ,レーザトリマ等のトリミング装置により、抵抗素子
を直接トリミングする方法で実施されている。
Such a function trimming method is carried out by directly trimming a resistance element by a trimming device such as a sand trimmer or a laser trimmer in a state where various electronic components are mounted on a wiring board and a hybrid integrated circuit is assembled.

次に配線基板として絶縁金属基板を用い,かつ抵抗素子
としてチップ抵抗体を基板上に実装して成る混成集積回
路を例に、従来実施されている機能トリミング方法を第
3図,第4図により説明する。図において、1は金属ベ
ース2に樹脂絶縁層3を被着した構造の絶縁金属基板、
4は基板面上に形成した銅箔等の導体パターン、5は基
板上の所定位置に搭載して導体パターン4にはんだ接合
したチップ抵抗体である。なおチップ抵抗体5は周知の
ようにセラミック材等の本体ベース51の上面に厚膜抵抗
52を被着してその両端に電極53を取付けて成るものであ
り、厚膜抵抗52を上に向けて基板1の上に搭載し、この
状態で導体パターン4と電極53との間がはんだ6でリフ
ローはんだ付けされている。
Next, referring to FIGS. 3 and 4, a conventional function trimming method will be described with reference to FIGS. 3 and 4 using a hybrid integrated circuit in which an insulating metal substrate is used as a wiring substrate and a chip resistor is mounted on the substrate as a resistance element. explain. In the figure, 1 is an insulating metal substrate having a structure in which a resin insulating layer 3 is attached to a metal base 2,
Reference numeral 4 is a conductor pattern such as a copper foil formed on the surface of the substrate, and 5 is a chip resistor mounted at a predetermined position on the substrate and soldered to the conductor pattern 4. As is well known, the chip resistor 5 is a thick film resistor on the upper surface of the main body base 51 such as a ceramic material.
52 is attached and electrodes 53 are attached to both ends thereof. The thick film resistor 52 is mounted on the substrate 1 with the upper side facing upward, and in this state, the conductor pattern 4 and the electrode 53 are soldered. 6 is reflow soldered.

かかるチップ抵抗体5に対する機能トリミングは次のよ
うにして行われる。すなわちチップ抵抗体5の側縁にト
リミング開始地点(第4図における鎖線A)を定め、こ
の地点に位置を合わせてサンドトリマ等のトリミング装
置7のノズル71を初期設定し、ここからサンドブラスト
を行いながらノズル71を矢印P方向に移動走査して厚膜
抵抗52を切削してその膜面に切込部54を形成する。なお
この場合のトリミング量は回路の電気的特性をモニタリ
ングしながら行い、混成集積回路の回路特性が所望値と
なるように抵抗値を調整する。
Functional trimming for the chip resistor 5 is performed as follows. That is, a trimming start point (chain line A in FIG. 4) is defined on the side edge of the chip resistor 5, the nozzle 71 of the trimming device 7 such as a sand trimmer is initialized by aligning with this point, and sand blasting is performed from here. The thick film resistor 52 is cut by moving and scanning the nozzle 71 in the direction of arrow P to form a notch 54 on the film surface. The trimming amount in this case is performed while monitoring the electrical characteristics of the circuit, and the resistance value is adjusted so that the circuit characteristics of the hybrid integrated circuit have desired values.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

ところで上記した従来の機能トリミング方法では次記の
ような不具合が発生する。すなわち配線基板がセラミッ
ク基板のように堅牢な材質のベース板上に導体パターン
を直接形成した片面のセラミック基板では問題となるこ
とがないが、絶縁金属基板,銅張積層基板,セラミック
基板上に樹脂絶縁層を介して複数層の導体パターンを形
成した多層配線基板のように材質的に強度の弱い絶縁層
を有する配線基板上に実装された抵抗素子に先記のよう
に機能トリミングを施すと、トリミング開始地点となる
チップ抵抗体5の側方部では基板側の絶縁層3がトリミ
ング作用を受けて一緒に切削されて該部分に符号Qで示
すように開溝が生じ、結果として配線基板の絶縁耐力が
損なわれるようになる。このような問題は図示例の絶縁
金属基板のみならず、樹脂配線基板のような銅張積層基
板に付いても同様であって基板自身の強度に欠損を与え
る他、特に両面配線基板,多層配線基板では導体パター
ン相互間に所要の絶縁耐力が確保できず致命的なダメー
ジとなる。
By the way, the above-described conventional function trimming method has the following problems. That is, a wiring board does not cause a problem in a single-sided ceramic board in which a conductor pattern is directly formed on a base plate made of a robust material such as a ceramic board, but an insulating metal board, a copper clad laminated board, or a resin on the ceramic board When a resistance element mounted on a wiring board having an insulating layer having a weak material strength, such as a multilayer wiring board in which a plurality of conductor patterns are formed through insulating layers, is functionally trimmed as described above, At the side portion of the chip resistor 5 which is the trimming start point, the insulating layer 3 on the substrate side is subjected to the trimming action and cut together, and an opening groove is formed at that portion as indicated by the symbol Q, resulting in the wiring substrate. The dielectric strength will be impaired. This problem applies not only to the insulating metal substrate shown in the figure but also to a copper clad laminated substrate such as a resin wiring substrate, which causes a loss in the strength of the substrate itself. On the board, the required dielectric strength cannot be ensured between the conductor patterns, resulting in fatal damage.

この発明は上記の点にかんがみ成されたものであり、そ
の目的は配線基板の種類に制約を受けず、配線基板に何
等の損傷ダメージを与えることなしに安全に機能トリミ
ングが実施できるようにした混成集積回路の機能トリミ
ング方法を提供することにある。
The present invention has been made in view of the above points, and its purpose is not to be restricted by the type of wiring board, and to enable functional trimming safely without damaging the wiring board. It is to provide a function trimming method for a hybrid integrated circuit.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記課題を解決するために、この発明の方法において
は、配線基板上における抵抗素子の実装箇所に複数個の
チップ抵抗体が横一列に連なったチップ抵抗アレイを搭
載してそのうちの1個を回路に接続し、かつ該チップ抵
抗アレイのうち回路に接続されたチップ抵抗体に並設す
る接続されないダミーのチップ抵抗体の領域上にトリミ
ング装置のトリミング開始地点を設定した上で回路に接
続されたチップ抵抗体に対するトリミングを行うように
したものである。
In order to solve the above-mentioned problems, in the method of the present invention, a chip resistor array in which a plurality of chip resistors are arranged in a row in a row is mounted at a mounting location of a resistor element on a wiring board, and one of them is used as a circuit. Connected to the circuit, and the trimming start point of the trimming device is set on the area of the dummy chip resistors that are not connected and are arranged in parallel with the chip resistors connected to the circuit of the chip resistor array, and then connected to the circuit. The trimming is performed on the chip resistor.

〔作用〕[Action]

上記方法のように、配線基板上に搭載したチップ抵抗ア
レイに対し回路に接続されてないダミー側のチップ抵抗
体の領域上にトリミング開始地点を設定してトリミング
を行うことにより、このダミー側のチップ抵抗体の本体
ベースがその背後に位置する配線基板に対して遮へい体
としての役目を果たし、配線基板の絶縁層をトリミング
作用から安全に保護することができる。
As in the above method, the trimming start point is set on the area of the chip resistor on the dummy side that is not connected to the circuit with respect to the chip resistor array mounted on the wiring board, and trimming is performed. The main body base of the chip resistor serves as a shield for the wiring substrate located behind it, and the insulating layer of the wiring substrate can be safely protected from the trimming action.

なお前記チップ抵抗アレイは、多数個取り方式で製作さ
れたチップ抵抗体を1個ずつ個片に切り離さずに、例え
ば2個分のチップ抵抗体を連ねたままブレークして得た
ものである。このため、チップ抵抗アレイとして、汎用
のチップ抵抗体を用いることができ、かつ同じチップ抵
抗体なので、どちらを回路に接続してもよく、向きが逆
になっても問題ないため、実装が容易である。
The chip resistor array is obtained by breaking, for example, two chip resistor bodies in series without cutting the chip resistor bodies manufactured by the multi-cavity manufacturing method into individual pieces. Therefore, a general-purpose chip resistor can be used as the chip resistor array, and since it is the same chip resistor, it does not matter which one is connected to the circuit and there is no problem if the orientation is reversed, so mounting is easy. Is.

〔実施例〕〔Example〕

第1図,第2図は本発明の実施例による機能トリミング
の作業状態図を示すものであり、第3図,第4図に対応
する同一部材には同じ符号が付してある。
FIGS. 1 and 2 show working state diagrams of functional trimming according to an embodiment of the present invention, and the same members corresponding to FIGS. 3 and 4 are designated by the same reference numerals.

すなわちこの発明により、チップ抵抗体として1個ずつ
個片にブレークせずに2個分のチップ抵抗体が横に連な
ったチップ抵抗アレイ50を配線基板1上における所定の
実装箇所に搭載し、ここで右側に並ぶチップ抵抗体はダ
ミーとして導体パターン4に接続せずに遊ばして置き、
左側のチップ抵抗体を導体パターン4にはんだ付け接合
して回路に組込む。
That is, according to the present invention, the chip resistor array 50 in which two chip resistors are horizontally arranged without being broken into individual pieces as chip resistors is mounted at a predetermined mounting location on the wiring board 1. The chip resistors lined up on the right side are left as dummy without being connected to the conductor pattern 4,
The chip resistor on the left side is soldered and bonded to the conductor pattern 4 and incorporated in the circuit.

かかる回路の組立状態で抵抗の機能トリミングを行うに
は、まずトリミング装置7の先端ノズル71のトリミング
開始地点を鎖線Aで示すように右側に並ぶダミー側チッ
プ抵抗体の面域上に設定し、ここからノズル71を矢印P
方向に移動走査して回路に接続された左側のチップ抵抗
体に対しその厚膜抵抗52を切削して必要な量だけトリミ
ングする。なおこのトリミング開始地点ではダミー側の
チップ抵抗体が同時にトリミング作用を受けることにな
るが、このトリミング分は混成集積回路の回路特性には
何等の影響を及ぼすことはない。しかもダミー側のチッ
プ抵抗体領域の本ベース51自身がその背後に位置する配
線基板1の絶縁層3に対する遮へい体としての役目を果
たすので、配線基板側の絶縁層3に損傷を与えることな
く安全に機能トリミングを遂行することができる。
In order to perform the function trimming of the resistance in the assembled state of the circuit, first, the trimming start point of the tip nozzle 71 of the trimming device 7 is set on the surface area of the dummy side chip resistors arranged on the right side as shown by the chain line A, From here, move the nozzle 71 to the arrow P
The thick film resistor 52 is cut from the left chip resistor connected to the circuit by scanning in the direction, and trimming is performed by a necessary amount. At the trimming start point, the chip resistors on the dummy side are simultaneously subjected to the trimming action, but this trimming has no effect on the circuit characteristics of the hybrid integrated circuit. In addition, since the main base 51 itself in the chip resistor area on the dummy side functions as a shield for the insulating layer 3 of the wiring board 1 located behind it, the insulating layer 3 on the wiring board side is not damaged and is safe. Functional trimming can be performed.

なお図示実施例は配線基板1として絶縁金属基板を採用
した例を示したが、これに限定されるものではなく配線
基板として樹脂,その他の絶縁材料の基板に導体パター
ンを形成した片面,両面,多層の銅張積層基板,さらに
は多層セラミック基板に付いても同様に実施できること
は勿論である。
Although the illustrated embodiment shows an example in which an insulating metal substrate is adopted as the wiring substrate 1, the present invention is not limited to this, and the wiring substrate is made of resin or another insulating material. Needless to say, the same can be applied to a multi-layered copper-clad laminated board and further to a multi-layered ceramic board.

〔発明の効果〕〔The invention's effect〕

以上述べたようにこの発明によれば、配線基板上におけ
る抵抗素子の実装箇所に複数個のチップ抵抗体が横一列
に連なったチップ抵抗アレイを搭載してそのうちの1個
を回路に接続し、かつ該チップ抵抗アレイのうち回路に
接続されたチップ抵抗体に並設する接続されないダミー
のチップ抵抗体の領域上にトリミング装置のトリミング
開始地点を設定した上で回路に接続されたチップ抵抗体
に対するトリミングを行うことにより、チップ抵抗アレ
イにおけるダミー側のチップ抵抗体がその背後に位置す
る配線基板に対する遮へい体の役目を果たし、混成集積
回路の回路組立後に実施する機能トリミング工程で配線
基板の絶縁層に損傷ダメージを与えることなく、したが
って配線基板の強度,絶縁耐力を損なうことなしに機能
トリミングを安全に遂行できる効果が得られる。また、
チップ抵抗アレイとして、ファンクショントリミング専
用の抵抗体でなく、汎用のチップ抵抗体を用いることが
でき、かつ同じチップ抵抗体を用いるので、どちらを回
路に接続してもよく、向きが逆になっても問題ないた
め、実装が容易である。そして、チップ抵抗アレイの向
きが逆になってもよいため、トリミング開始地点のダミ
ーのチップ抵抗体と回路に接続されたチップ抵抗体だけ
あればよいので、無駄なスペースが必要なく、スペース
ファクタが良い。
As described above, according to the present invention, a chip resistor array in which a plurality of chip resistors are arranged in a row in a row is mounted on a mounting portion of a resistance element on a wiring board, and one of them is connected to a circuit, And for the chip resistors connected to the circuit after setting the trimming start point of the trimming device on the area of the dummy chip resistors that are not connected and are arranged in parallel to the chip resistors connected to the circuit in the chip resistor array. By performing trimming, the chip resistor on the dummy side in the chip resistor array acts as a shield for the wiring board located behind it, and the insulating layer of the wiring board is used in the function trimming process performed after circuit assembly of the hybrid integrated circuit. The function trimming is safe without damaging the cable and thus without compromising the strength and dielectric strength of the wiring board. Execution can effect can be obtained. Also,
As the chip resistor array, a general-purpose chip resistor can be used instead of a resistor dedicated to function trimming, and since the same chip resistor is used, whichever may be connected to the circuit, the orientation will be reversed. Since there is no problem, it is easy to implement. Since the chip resistor array may be reversed in direction, only the dummy chip resistor at the trimming start point and the chip resistor connected to the circuit are needed, so that no wasted space is required and the space factor is reduced. good.

【図面の簡単な説明】[Brief description of drawings]

第1図,第2図は本発明の方法による機能トリミングの
作業状態を示した混成集積回路の要部側面図,および同
平面図、第3図,第4図はそれぞれ第1図,第2図に対
応する従来の機能トリミング作業状態図である。各図に
おいて、 1:配線基板、4:導体パターン、50:チップ抵抗アレイ、5
1:本体ベース、52:厚膜抵抗、53:電極、7:トリミング装
置、71:ノズル、A:トリミングのスタート位置、P:トリ
ミング走査方向。
1 and 2 are side views of a main part of a hybrid integrated circuit showing working states of functional trimming according to the method of the present invention, and plan views thereof, FIGS. 3 and 4 are FIGS. 1 and 2, respectively. It is a conventional function trimming work state diagram corresponding to the drawing. In each figure, 1: wiring board, 4: conductor pattern, 50: chip resistor array, 5
1: body base, 52: thick film resistor, 53: electrode, 7: trimming device, 71: nozzle, A: trimming start position, P: trimming scanning direction.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】配線基板上に抵抗素子を含む回路を構成し
た混成集積回路に対する機能トリミング方法であって、
配線基板上における前記抵抗素子の実装箇所に複数個の
チップ抵抗体が横一列に連なったチップ抵抗アレイを搭
載してそのうちの1個を回路に接続し、かつ該チップ抵
抗アレイのうち回路に接続されたチップ抵抗体に並設す
る接続されないダミーのチップ抵抗体の領域上にトリミ
ング装置のトリミング開始地点を設定した上で回路に接
続されたチップ抵抗体に対するトリミングを行うことを
特徴とする混成集積回路の機能トリミング方法。
1. A function trimming method for a hybrid integrated circuit in which a circuit including a resistance element is formed on a wiring board.
A chip resistor array in which a plurality of chip resistors are arranged in a row in a row is mounted at a mounting location of the resistor element on a wiring board, and one of them is connected to a circuit and connected to a circuit of the chip resistor array. Hybrid chip integration, wherein a trimming start point of a trimming device is set on an area of a dummy chip resistor which is not connected and is arranged in parallel with the chip resistor connected to the circuit, and trimming is performed on the chip resistor connected to the circuit. Circuit function trimming method.
JP63033462A 1987-10-23 1988-02-16 Function trimming method for hybrid integrated circuit Expired - Lifetime JPH0748411B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63033462A JPH0748411B2 (en) 1987-10-23 1988-02-16 Function trimming method for hybrid integrated circuit

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-267684 1987-10-23
JP26768487 1987-10-23
JP63033462A JPH0748411B2 (en) 1987-10-23 1988-02-16 Function trimming method for hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH01194301A JPH01194301A (en) 1989-08-04
JPH0748411B2 true JPH0748411B2 (en) 1995-05-24

Family

ID=26372163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63033462A Expired - Lifetime JPH0748411B2 (en) 1987-10-23 1988-02-16 Function trimming method for hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH0748411B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041074U (en) * 1983-08-26 1985-03-23 日本ビクター株式会社 Printed circuit board equipped with chip resistors

Also Published As

Publication number Publication date
JPH01194301A (en) 1989-08-04

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