JPH0746803B2 - Frame pulse protection circuit - Google Patents

Description

The present invention relates to a protection circuit for a frame pulse signal having a fixed cycle in a digital transmission system or the like.

(Prior Art) In a device in a digital transmission system, for example, a synchronous modem, a receiving side extracts a frame pulse of a constant cycle from a received signal, and based on this, a transmitting side and a receiving side operate in synchronization. There is. For this reason, a circuit that accurately takes out the frame pulse was required.

FIG. 2 shows an example of a conventional frame pulse protection circuit. In the figure, 1 is a digital phase synchronization circuit (hereinafter referred to as DPLL), 2 is a decoder, and 3 is a 2-input AND circuit. FIG. 3 is an operation waveform diagram of the circuit of FIG.

In the circuit, an input frame pulse A extracted from a received signal by a frame pulse extraction circuit (not shown)
Is input to DPLL1 at timing t1, for example. DPLL1
Supplies the first signal (output 1) to the decoder 2 at a predetermined timing, and outputs the second signal (output 2) B at the timing t1. The decoder 2 decodes the first signal and outputs the gate signal C (input frame pulse A
A pulse with a constant width on both sides of the rising edge of is output. The input frame pulse A and the gate signal C are input to the 2-input AND circuit 3, and a logical product of these is output and output as an extraction frame pulse D.

As described above, by passing only the extracted input frame pulse by the gate signal C, the pulse other than the regular frame position erroneously detected by noise or the like is removed and the frame pulse is protected.

(Problems to be Solved by the Invention) However, in the above circuit, when a regular input frame pulse is not detected due to noise or the like, the output frame pulse is also completely lost, and a frame pulse is started by a device such as start-stop synchronization. There is a problem that it is impossible to receive all data when it is used as a pulse.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above problems and provide a frame pulse protection circuit that can compensate an output frame pulse signal even when the input frame pulse signal is missing due to noise or the like.

(Means for Solving the Problem) In order to solve the above-mentioned problems, the present invention receives an input frame pulse signal of a constant cycle, synchronizes with the input frame pulse signal, and outputs the first signal at a predetermined timing. A self-propelled digital phase-locked circuit that outputs a second signal at the timing of the input frame pulse signal; a decoder that decodes the first signal and generates a gate signal that extracts the input frame pulse signal; Means for passing only the input frame pulse signal by the gate signal,
It is composed of means for generating a pseudo input frame pulse signal based on the second signal, and means for taking an OR of the passed input frame pulse signal and the pseudo input frame pulse signal as an output signal.

(Operation) According to the present invention, when the input frame pulse signal is correctly received and extracted, the input frame pulse signal passes through the gate means by the gate signal and is output, and the input frame pulse signal is lost. A pseudo input frame pulse signal generated based on the second signal output from the digital phase synchronization circuit is output to.

(Embodiment) FIG. 1 shows an embodiment of the frame pulse protection circuit of the present invention. In the figure, the same components as those of the conventional example are represented by the same reference numerals. That is, 1 is a digital phase synchronization circuit (DPL
L), 2 is a decoder, 3 and 4 are 2-input AND circuits, and 5 is a 2-input OR circuit. Here, even if the input pulse disappears, the DPLL1 maintains the state before the input pulse disappears due to self-running and continues to output a predetermined signal. FIG. 4 is an operation waveform diagram of the circuit of FIG.

In the above configuration, the input frame pulse A is input to DPLL1 at timing t1, for example. The DPLL1 supplies the first signal (output 1) to the decoder 2 at a predetermined timing, and outputs the second signal (output 2) B at the timing t1. The decoder 2 decodes the first signal,
The gate signal C is output. The input frame pulse A and the gate signal C are input to the 2-input AND circuit 3, the logical product of these is obtained, and the extraction frame pulse D is output.

The second signal B of the DPLL is a pulse signal of the same frequency that is generated at the same timing in synchronization with the input frame pulse A, for example, t1, and is ANDed with the gate signal C by the 2-input AND circuit 4 to generate a pseudo signal. A frame pulse E is created. The outputs of the two-input AND circuit 3 and the two-input AND circuit 4 are logically ORed by the two-input OR circuit 5 and output as an output frame pulse.

Therefore, even if the extracted frame pulse D is missing, the pseudo frame pulse E continues to be output, and the output frame pulse is not missing.

(Effect of the Invention) As described above, according to the present invention, when the input frame pulse signal is correctly received and extracted, the input frame pulse signal passes through the gate means by the gate signal and is output. When the frame pulse signal is missing, a pseudo input frame pulse signal created based on the second signal output from the digital phase synchronization circuit is output, so that false detection due to noise or the like can be removed and the frame pulse signal can be removed. Can be compensated for by a pseudo frame pulse. Therefore, even if there is a momentary interruption in the telephone line in a digital transmission system, etc., the stable operation of the device on the receiving side can be maintained, and the system runaway due to the momentary interruption. Can be prevented, and can be configured simply by adding a simple circuit to the conventional device, which can be provided at a small size and at low cost. And so on.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame pulse protection circuit of the present invention, FIG. 2 is a block diagram showing an example of a conventional frame pulse protection circuit, and FIG. 3 is an operation waveform diagram in the circuit of FIG. , FIG. 4 is an operation waveform diagram in the circuit of FIG. 1 ... Digital phase synchronization circuit, 2 ... Decoder, 3, 4 ...
… 2-input AND circuit, 5 …… 2-input OR circuit.

Claims (1)

[Claims] 1. An input frame pulse signal having a constant period is received, and in synchronization with the input frame pulse signal, a first signal is output at a predetermined timing and a second signal is output at the timing of the input frame pulse signal. A self-propelled digital phase synchronization circuit for outputting, a decoder for generating a gate signal for decoding the first signal and extracting an input frame pulse signal, a means for passing only the input frame pulse signal by the gate signal, A frame pulse protection circuit comprising: means for creating a pseudo input frame pulse signal based on the second signal; and means for using a logical sum of the passed input frame pulse signal and pseudo input frame pulse signal as an output signal.