JPH0746785B2 - PCM code decoder - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a PCM code decoder, and more specifically, a two-wire system which is a bidirectional transmission line by decoding an input PCM signal from a receiving line into an analog signal. A PCM code decoder (PCM) having a 2-line to 4-line conversion function, which supplies the signal to the transmission line and also encodes the analog signal from the 2-line type transmission line into a PCM signal and supplies it to the transmission line.
Codec).

[Background of the Invention]

The subscriber circuit of the exchange is configured to have functions such as power supply, overvoltage protection, call signal transmission, monitoring, PCM code decoding, 2-wire to 4-wire conversion, and testing.

In the configuration having these functions, the circuit for performing 2-line to 4-line conversion was conventionally configured separately from the PCM code decoder, but recently, with the progress of semiconductor integrated technology and signal processing circuit technology. Nowadays, it is being considered to configure it integrally with a PCM code decoding circuit (Electronics / May 5,1982, P.113).
~ 118). The electronic circuit sends the input signal from the receiving line only to the two-line type line for bidirectional transmission such as the subscriber line in order to realize the 2-line to 4-line converting function, and the signal from the receiver is transmitted to the transmitting line. You have to prevent it from being output intricately.
Therefore, in the conventionally proposed PCM code decoder, the circuit for canceling the sneak signal, that is, the balancing circuit is composed of a digital circuit, and is also integrated with the PCM code decoder. More specifically, the voice analog signal to be transmitted from the two-wire line is converted into a digital signal through a high-frequency noise elimination prefilter and an A / D converter, and band-limited by the digital filter, and then the PC.
It is sent to the transmission line as an M signal. The PCM signal received from the receiving line is band-limited by a digital filter, and is supplied to the 2-line type line as a voice analog signal via a D / A converter and a post filter. Then, the balanced circuit, a filter having a characteristic that approximates the transmission characteristics of the path of the sneak signal is provided between the A / D converter and the D / A converter, and the output of the filter is the A / D. It is configured to subtract from the output of the converter.

In the PCM code decoder as described above, since the amplification circuit is generally provided in the path of the sneak signal, the leak signal may be larger than the received signal.
In some cases, the coding level of the converter may be exceeded, or even if the coding level is below the maximum coding level, the sneak signal is superimposed on the signal from the two-wire line that should be transmitted. There is a problem that the dynamic range of the signal is insufficient and the S / N ratio is deteriorated.

Furthermore, if an encoder / decoder is to be implemented in an LSI, the combined amplitude of the sneak signal and the transmission signal exceeds the power supply voltage, and LS
May destroy I.

Also, in contrast to the first conventional method for realizing a balanced circuit with the all-digital circuit described above, the balanced circuit is composed of only analog circuits, and the input of the A / D converter and the output of the D / A converter are Although the second method of forming between the two may be considered, the balanced circuit needs to adapt to various loads, that is, impedances on the side of the two-wire line, and therefore includes a plurality of types of analog circuits having different transfer functions. , A circuit for selecting and controlling the optimum balanced circuit is required. By changing the coefficient of the multiplier in the digital circuit, it is possible to easily realize a plurality of balanced circuits without increasing the number of circuit devices. However, in an analog circuit, it is attempted to realize a plurality of balanced circuits having different transmission times. For example, it is necessary to switch between different resistors, capacitors, operational amplifiers, etc., which increases the scale of the circuit device, and there is a problem that an economical occupied area cannot be maintained when an LSI is used.

On the other hand, in addition to the above, as a third method, it has been proposed to use both an analog balanced circuit and a digital balanced circuit in combination (for example, The Bell System Technical Journal).
nal), Vol.60, No.7, P.1585-1619, September 1981).

However, the analog balanced circuit proposed above has one pole and a zero point so that it can correspond to the impedance of a two-wire four-wire interface unit (for example, a transformer) in addition to a plurality of two-wire subscriber line impedances. It is specified to use a transfer function with a fixed frequency characteristic that does not have, and therefore, a capacitor or inductor having a relatively large element value is required to realize such an analog balanced circuit. Similarly, realization in LSI is virtually impossible economically. Further, in the analog filter balanced circuit, when the absolute value of the element value changes,
Since the frequency gain characteristic and the phase characteristic of the loop-in signal fluctuate as they are, it becomes extremely difficult to suppress the loop-in signal with high performance by the digital balance circuit in the subsequent stage.

[Object of the Invention]

Therefore, it is an object of the present invention to realize a PCM code decoder having a balanced circuit in which the level of a loop-in signal is suppressed and the circuit configuration is simple so that it can be easily integrated into an LSI.

[Outline of Invention]

In order to achieve the above object, the present invention divides the balanced circuit into two parts in a PCM code decoder (PCM codec) having a 2-wire to 4-wire conversion function, and the first part is a D / A
It is composed of a digital circuit provided between the input side of the converter and the output side of the A / D converter, the second part of which is the D /
It is characterized by being constituted by an analog circuit which does not have a frequency characteristic provided between the output side of the A converter and the input side of the A / D converter, that is, the value does not change depending on the frequency.

According to the present invention, the degradation of the S / N characteristics of the A / D converter is reduced by stabilizing the level of the sneak signal in the portion configured by the analog circuit with good stability, and is configured by the digital circuit. In the portion, the sneak signal can be canceled with high accuracy by changing the transfer function of the digital filter according to the impedance on the side of the two-wire type transmission line.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a diagram showing the configuration of an embodiment of a PCM code decoder (codec) according to the present invention. In the figure, the part surrounded by a solid line ○ is a code decoding part having a balanced circuit, and the other part is an equivalent circuit from the analog input / output terminals 1 and 10 of this code decoder to the telephone. It is also shown in the figure. 4-line type receiving line (not shown)
The PCM signal from the
The band is limited by, and a part of the signal is converted into an analog signal by the D / A converter 8, smoothed by the post filter 9, and output as a decoded analog audio signal from the terminal 10. The voice analog signal to be transmitted is added to the A / D converter 3 via the terminal 1, the adder (arithmetic unit) 14, and the high-frequency noise elimination prefilter 2 to be converted into a digital signal.
Further, the signal is band-limited by the digital filter 4 via the adder 12 and then transmitted as a PCM signal from the terminal 5 to the transmission line (not shown) of the 4-wire type line.

The digital filter 11 and the analog gain amplifier circuit 13, together with the adder (arithmetic unit) 12 and the adder 14, respectively form a balanced circuit as described later in detail. The balanced circuits 11 and 13 are configured so that the analog signal from the terminal 10 is amplified by the amplifier 1
6, a circuit for removing a signal sneaking through the terminating circuit 17 and the amplifier 15, and constitutes a main part of the present invention.

The audio analog signal on the receiving side of terminal 10 is fed to an external amplifier 16
After passing through (amplification factor b), the termination circuit (impedance
Z _T) 17 in divided with two-wire side telephone line (impedance
Z _L ) 18. On the other hand, the analog audio signal on the transmission side passes from the signal source 19 through the line 18, is divided by the termination circuit 17, and is supplied to the input terminal 1 of the code decoder through the external amplifier 15 (amplification factor a). At this time, a part of the analog signal on the receiving side spills to the transmitting side. Therefore, _assuming that the signal voltages of the signal source 19 and the terminal 10 are V _s and V _r , respectively, the voltage at the terminal 1 is
V ₁ has a value represented by the following equation.

In the above equation, the wraparound signal component is the second term. Here, as an example, there are four typical impedances corresponding to the two-line telephone line in North America.

Z _L1 = 900 (Ω) …… (3) Will be specifically examined. However, s in the above equation is a symbol indicating a complex angular frequency. Termination impedance Z _T
Is set equal to Z _L0 , and the transfer function H _BN0 of the first balancing circuit 13 is _set to H _BN0 = k (real number). In this case, Z _L = Z _Li
The transfer function of each wraparound signal at terminal 1 for (i = 0,1,2,3) is And the transfer function H _1i of the _wraparound signal at the output of the adder 14 is Becomes Therefore, Therefore, H _1i can be set to 0, and the sneak signal after the output of the adder 14 can be completely canceled. Of these, the value of ab is uniquely determined by the level rule of the exchange system, but Z _L1 cannot be completely canceled because it has various frequency characteristics as described in (2) to (5) above. However, as an example, if k = 1 when ab = 2, then at least Z _Li = Z
_L0 can be completely canceled, and the sneak signal level can be effectively attenuated for other impedances. Figure 2 was obtained under the above conditions
It shows a comparison result between 5-1-i for H _0i and 5-2-i for H _1i (where i = 1, 2, 3). Even for all Z _Li (i = 1,2,3), there is a sneak signal suppression effect of at least 6 dB or more at the worst point of 3.4 kHz, and the dynamic range of the transmission signal can be expanded accordingly. The S / N characteristics can be improved.

FIG. 3 is a circuit showing one embodiment of the balance circuit 13 and the adder 14 in FIG. 1 when ab> 0. The terminal 4-8 is connected to the input terminal 1, the terminal 4-9 is connected to the output side of the post filter, and the terminal 4-14 is connected to the input side of the prefilter. Capacitor 4-6 (Capacitance value C ₄ ), Capacitor 4
-7 (capacitance value C ₅ ) and the operational amplifier 4-2 are known amplifiers. Make up. Similarly, the capacitor 4-3 (capacitance value C ₁ ), the capacitor 4-4 (capacitance value C ₂ ), the capacitor 4-5 (capacitance value C ₃ ) and the operational amplifier 4-1 are connected to the input voltage of the terminal 4-8. , An addition circuit with the output voltage of the amplifier 4-2,
Furthermore, the capacitor 4-11 (capacitance value C ₆ ) and the capacitor 4-
12 (capacitance value C ₇ ) and the operational amplifier 4-13 are amplifiers 4-1.
Output voltage inverting amplifier 4-0 Make up. That is, assuming that the input voltages of the terminals 4-8 and 4-9 are v ₈ and v ₉ , respectively, the output of the inverting amplifier 4-0
v ₁₄ is And C ₁ = C ₂ = C ₃ and C ₆ = C ₇ Becomes Therefore, Therefore, Therefore, equation (9) agrees with equation (7),
The circuit of FIG. 3 is the desired balancing circuit 13 and adder of FIG.
It is clear that 14 is realized. further,
By changing the ratio of C ₄ and C _{5 in} the circuit of Fig. 3,
It can be adapted to the value of the gain ab of various external circuits.

That is, k = 1 can be realized by setting C ₄ = C ₅ when ab = 2, and, for example, when ab = 1.5 and ab = 3, respectively. As a result, it is possible to obtain exactly the same effect as that shown in FIG. 2 on the impedances of the expressions (2) to (5).

Next, FIG. 4 shows an embodiment of the balancing circuit 13 and the adder 14 of FIG. 1 when ab <0. in this case,
Since the sneak signal of the terminal 4-8 is phase-inverted, it is not necessary to phase-invert the signal for canceling input from the terminal 4-9, and therefore the capacitors 4-6 and 4-
7 and the amplifier 4-2 can be omitted, and the output signal of the post filter can be directly input from the capacitor 4-4. Since the operation of this embodiment can be easily inferred from the first embodiment, its explanation is omitted.

In FIGS. 3 and 4, the inverting amplifier 4-0 shown by the broken line can be omitted by using the output voltage 4-10 of the amplifier 4-1 as the input signal to the pre-filter. As a result, the phase of the adder output signal with respect to the input signal from the terminal 4-8 will be inverted, but the effect of this is if necessary, such as the pre-filter, A / D converter, and digital filter. It suffices to carry out the phase inversion of the signal with, and the phase inversion can be performed by a method which is already widely and generally known.

Furthermore, in FIG. 3 and FIG.
If either C ₄ , C ₅ , or C ₂ is divided into a plurality of capacitors and a switch is provided for each capacitor (not shown), the gain (ab) of the external circuit or the two-wire type It is possible to switch the capacitance ratio (that is, the value of k) fixedly or automatically according to the impedance Z _Li of the line.

Next, the allowable voltage will be examined.

In the case of FIGS. 3 and 4, since the potential of the inverting input terminal of the operational amplifier 4-1 is fixed to the potential of the non-inverting input terminal (ground), it is input to the input terminal 4-8 (1 in FIG. 1). The allowable voltage of the signal is determined by the breakdown voltage of the capacitor 4-3, and when the code decoder is implemented by an LSI, it is not affected by the power supply voltage or the breakdown voltage of other circuit elements (for example, the operational amplifier 4-1). The capacitors in the circuits of FIGS. 3 and 4 may be replaced with resistance elements.

By the way, since the analog circuits of FIGS. 3 and 4 are configured by using only the relative accuracy of the capacitors or resistors, it is possible to realize the desired value of k in a relatively small area in the LSI sufficiently accurately. it can. However, the exact implementation of k is not the only object of the invention. That is, the above k value is a value for one of Z _Li (i = 0,1,2,3), and the wraparound signal suppression for the other three types of Z _Li is clear from FIG. This is because it is still insufficient. However, since the wrap-around signal can be stably attenuated by using the circuit of the present invention, the remaining wrap-around signal can be effectively eliminated by the balanced circuit of the digital filter 11 and the adder 12. That is, the digital filter
At 11, the transfer function of the above equation (7) is created and subtracted by the adder 12, so that the remaining components of the wraparound are eliminated. Since the structure of the digital filter is well known in the related art, detailed description thereof will be omitted. For the digital filter, use the equation (7) as 2
It can be approximated by a transfer function of the 3rd or 3rd order, and even if the line impedance Z _L of the 2-line side line changes, it can be adapted by changing the coefficient in the filter accordingly, and the wraparound component can be canceled with high accuracy. be able to.

〔The invention's effect〕

According to the present invention, since there is a stable analog balanced circuit in front of the A / D converter, the sneak signal component can be stably suppressed in advance, so that a signal exceeding the coding level of the A / D converter is generated. In addition, it has an effect of preventing the problem that the sneak signal is superposed on the transmission signal that should be A / D-converted and causes the S / N deterioration due to the lack of the dynamic range of the transmission signal. Furthermore, since the characteristics of the analog balanced circuit are stable, the digital balanced circuit after the A / D converter can set an optimum coefficient value according to the line, and cancels the sneak-in signal component with high accuracy. be able to. Further, as shown in FIGS. 3 and 4, an analog balanced circuit having no frequency characteristic can be formed by only a small number of capacitors or resistors and operational amplifiers, which has the effect of reducing the size of the analog circuit portion.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a 2-line to 4-line converter using a PCM code decoder having a balancing circuit according to the present invention, and FIGS. 3 and 4 are analog balancing circuits 13 and 14 of FIG. circuit diagram,
FIG. 2 is a diagram showing frequency characteristics of a transfer function of a wraparound signal. 0 ... PCM encoder / decoder, 1 ... Transmit side audio analog signal input terminal, 2 ... Pre-filter, 3 ... A / D converter, 4 ... Digital filter, 5 ... Transmit side PCM output terminal, 6 ... Receive side PCM
Input terminal, 7 ... Digital filter, 8 ... D / A converter,
9 ... Post filter, 10 ... Reception side audio analog signal output terminal, 11 ... Digital filter, 12 ... Digital adder, 13 ... Analog balance circuit, 14 ... Analog subtractor, 15 ...
Amplifier (amplification factor is a times), 16 ... Amplifier (amplification factor is b)
Fold), 17 ... terminating circuit, 18 ... telephone line line impedance (impedance Z _T), 19 ... transmission audio signal voltage source handset.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yu Kokubo 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-59-225626 (JP, A)

Claims (2)

[Claims] 1. A first conversion circuit for decoding a reception PCM signal and converting it into an analog reception signal, a second conversion circuit for encoding an analog signal to be transmitted and converting it into a transmission PCM signal, and an external circuit. In order to cancel the analog reception signal component that goes around to the second conversion circuit via the circuit, the first and second
In the PCM code decoder comprising a balance circuit provided between the conversion circuits, the balance circuit converts the analog signal flowing through the second conversion circuit from the analog signal
An analog balanced circuit for subtracting an analog signal that changes according to the analog signal flowing through the conversion circuit, and a digital signal that changes according to the digital signal flowing through the first conversion circuit from the digital signal flowing through the second conversion circuit. On the same LSI substrate as the first and second conversion circuits and the digital balance circuit, wherein the analog balance circuit has a circuit structure without frequency characteristics. PCM code decoder characterized by being formed in. 2. The PCM code decoder according to claim 1, wherein the first conversion circuit converts a first digital filter for limiting a band of a received digital signal, and an output of the filter into an analog signal. And a post filter connected to the converter, the second conversion circuit includes a pre-filter for filtering a transmission analog signal, and an output of the filter is a digital signal. An A / D converter for converting into an A / D converter, and a second digital filter connected to the converter, wherein the analog balancing circuit has a gain amplifier circuit having an output of the post filter as an input, Arithmetic means for subtracting the output of the gain amplifying circuit from the input of the pre-filter, wherein the digital balancing circuit receives the output of the first digital filter as input 3 digital filter,
A PCM code decoder comprising: an arithmetic means for subtracting the output of the third digital filter from the input of the second digital filter.