AU681169B2 - Line termination circuit - Google Patents

Description

P100/0O11 28/5/91 Regula~tion 3.2

AUSTRALIA

Patents Act 1990 990* t.

S S

S.

9 9 9

SSOV

ORIGINAL.

COMPLETE SPECIFICATFION STANDARD PATENT Invention Title: "LINE TERMINATION CIRCUIT" The following statemnent is a full description of this invention, including the best m-ethod of

S.

S S 9 9.95 9 9905 performing it known to us:- This invention relates to a method and arrangement for improving the performance of subscriber line circuits where an analog line interfaces with digital circuits, in a telephone exchange.

The invention will be described in the context of an interface between an analog subscriber line and a PCM circuit.

Background In a known arrangement, the analog line is connected to an IC called a Subscriber Line Interface Circuit (SLIC) which serves to match termination impedances and amplify the signals transmitted to or received from the line.

The SLIC in turn is connected to a digital CODEC IC referred to as a SLAC which converts the analog signals received from the line via the SLIC to digital signals and converts digital signals to analog signals for transmission to the line via the SLIC. Partial balancing of the line circuit impedance and cross-talk filtering is performed digitally in conjunction with the SLAC, Matching impedances are connected between the SLIC and the SLAC.

The arrangement is sensitive to the choice of the matching impedances as an incorrect choice of impedances may cause an imbalance in the filter coefficients in the SLAC.

A problem which we have found with the known arrangement is that a large matching impedance is required between the output of the SLAC and its Soociated input to the SLIC, and another large impedance is required between the SLIC input and output terminals connected to the SLAC. A particular disadvantage of this arrangement is that the connection lead from the SLAC output to the SLIC input picks up high frequency noise e.g. 256 kHz clock signals which results In an audible hissing noise in the voice frequency channel.

Summary of the Invention The purpose of this invention is to reduce the effect of the noise 4nal picked up on the SLIC input lead without requiring the recalculation of the coefficients in the SL.AC filter and the consequent re-programming.

The specification therefore discloses a line amplifier circuit having a first transfr function, the line amplifier circuit having a send line amplifier and a receive line amplifier, the interface including an impedance network connected between the

I

3 tine amplifier circuit and a converter/balancing circuit including a balancing arrangement, a codec and a filter arrangement, wherein the filter arrangement includes digital filter means having programmable coefficients selected to achieve directional isolation based on the impedance of the line and the impedance of the impedance network, wherein the impedance network includes three Impedances Z 2 and one end of each of the impedances being connected to a common point, wherein the output of the receive line amplifier is connected to the input of a receive path in the converter/balance circuit, the converter/balance circuit including a serd path connected to the input of the send line amplifier via Z 2 in series with Z3, the common point being connected to the output of the receive line amplifier, wherein the value of the impedances

Z

1

Z

2 and Z 3 are calculated from the relationships.

T*

_zI- 1- 7. z, Z3 "2e Z3i zv 1+z/z 1 e where Z 1 and Z 2 are high value impedances known to satisfy the operating conditions of the interface circuit in an hypothetical impedance network in which Z, is in the same position as 2 2 is in the same position as Z2', the equivalent of Z 3 in the hypothetical impedance network being zero.

Brief Description of the Drawings The invention will be described with reference to the accompanying drawing in which: Figure 1 is a diagram of a known subscriber interface arrangement; Figure 2 shows the equivalent circuit for the analog signal amplifiers between the line side of the SLIC and the matching impedance of the known arrangement; Figure 3 shows the arrangement of the relevant components of the SLAC in block form.

Figure 4 shows the equivalent circuit of Figure 2 modified in accordance with an embodiment of the invention; Figure 5 shows the SLIC and SLAC with the matching impedance modified in accordance with an embodiment of the invention; Description of the Invention Figure 1 shows an AMD SLAC AM7901 A/B or AM7905 A as an example of a SLAC, and an AMD AM795 XX or AM 79M5 XX SLIC as an example of a SLIC.

The output of the SLAC, Vout, is connected via impedance Z 2 to 5" impedance Z 1 The junction of Z, and Z 2 is connected to terminal RSN of the SLIC. The other end of Z, is connected to SLIC output VTX which is connected to the input of SLAC VIN Typical values of the impedances are: Z, 900 K 0, Z 2 390 K 0, 'The high value of Z1, Z2 and the length of the conductor from V t to RSN means that this conductor picks up noise which is imposed on RSN as an input signal. The effect of this is discussed with reference to Figure 2.

In Figure 2 terminal RSN of the SLIC is shown connected to the juncdion of Z, and Z 2 The input signal V 4 is applied to the other end of Z RSN is the input terminal of a current mode inverting amplifier 20, shown in its equivalent circuit form with a gain The output from the current mode amplifier 20 is applied to the analog line as It. The analog line is represented by its equivalent impedance ZL producing output voltage V 2 Signal V, on the line is applied via line impedance Z L to the input of amplifier 21 with a gain h whose output V 3 is connected to Z, and to terminal on the SLAC. RSN is a virtual earth, being the input to amplifier The analysis of Figure 2 is as follows: I, (V 4

/Z

2 V3/Z 1 -I uraaa~ 1V 2 1= V.

1

V

1

T

2

V

3

V

4

T

2 T22 I where T is a matrix transfer 'function with elements: zout

Z

V2Z _7 ZlKL -1 V3 1 -'1 22V 4 I V 1. 1 2L h., Th itrngadblncrgfntin fte LCwl nwb ecrbdwt reeec o iue3 Fiue3sos0eeatfncinlboksi0h LC Th SLChsatasi ahwt nutV, n h olwn lmns 32 aao0andvc I _I 6 33 analog to digital converter 34 summer 39 digital gain device digital filter The receive path has the following elements: 41 digital filter 42 digital loss device 43 summer digital to analog converter 46 analog loss device 47 summer o, In addition the SLAC includes the following filters and matching devices.

31 analog impedance scaling network Ale 44 digital Z filter 'I 35 summer 36 and 37 digital hybrid filter 38 filter controller Several of the blocks in the signal processing section of the SLAC are eo 0 U I user programmable. These must be loaded with the set of coefficients determined by the design specification, The relevant functions of the SLAC are outlined below: In the SLAC there are two feedback paths which modify the effective two-wire input impedance of the SLIC by providing programmable feedback from V1n to Vout. The analog impedance scaling network (AISN), 31 provides a programmable analog gain from to Vou. The Z filter 44 is a programmable digital filter connecting to Vou, These two paths provide two-wire impedance matching.

The SLAC also contains programmable filters 40 and 41 in the receive (from TSA) and transmit (To TSA) directions programmed for distortion correction and equalization and in addition can be used to correct distortion from the Z filter 44.

In addition the SLAC includes a programmable B filter 36, 37, used to adjust trans-hybrid balance. This filter provides a transfer function equal to that of the echo path but with the opposite sign, thus Jllowing echo cancellation by summing at 34, The transmit path of the SLAC has two programmable gain devices, an analog gain device 32 having a gain of OdB or 6.02dB, and a digital gain device K*2 39 with a gain adjustable from OdB to 12dB.

The receive path of the SLAC includes a digital loss device 42 programmable from OdB to 12dB, and an analog loss device 46 of OdB or 6dB.

The coefficients of these blocks are calculated with respect to the specific values of impedances Z, and Zz, therefore any change of these parameters will affect the system performance.

Consequently re-calculation and re-programming of the device will be needed. The present invention avoids this complex process while modifying the impedance arrangement of the SLIC.

Referring to Figure 4, the embodiment of the invention will now be described.

It is important that any alteration to the matching impedances does not disturb the balance of the SLAC filtering co-efficients as this would involve i, 8 complex calculations and reprogramming of the co-efficients.

As shown in Figure 4, a new impedance Z3 is added between RSN and the junction of Z 1 and Z'.

Voltage V 4 is applied to Z 2 and appears as V' at j the junction of Z1' and

Z

2 However, according to the invention Z 3 has been interposed between j and RSN, so that: Y2 V4=K V 3 +K V 4 1

+Y

2

Y

3

Y

1 2 where Y, Y2 and Y 3 are the admittances of Z 2 and ZI respectively According to the above expression K, 1 and K 2 1, therefore the °ii. same value of input current, l,n V/Z 3 could be generated using lower value of

Z

3

Z

3

Z

1

Z

3

Z

2 This feature is used to improve interference immunity of the device.

The new arrangement in Figure 4 is described as follows: where .1.4 e o -i i

ZII

ZOh+ZKj K Z Zji+ZaK( K' To ensure that the feed forward echo cancelling and digital impedance :filtering in the SLAC operate rorrectly it is necessary that T' =T so that the correct proportion of the SLAC output from is fed in to line and back to The matrix equation above is satisfied when 1 I zi I~ =Z where Z 3 Kismniu 1 la 1 amssbea teZ LCoupt To calculate mto ecie bv o impedanceZ 3 ndZ'te values can hol be arirredhose up to several tim-es, thus improving the immunity of the device to, clock noise and general interference. For comparison, using an identical set of SLAC coefficients and the same PCB layout, the system shown in Figure 5 has a clock noise level 20 times lower than that shown in Figure 1.

In the foregoing formulae, where the impedances are complex impedances, modulus values are used in the inequality formulae.

to

Claims (8)

1. A communication interface including a line amplifier circuit connected to a converter/balancing circuit by an impedance network, wherein the converter/balancing circuit includes a filter arrangement including digital filter means having programmable coefficients selected to achieve directional isolation based on the impedance of the line and the impedance of the impedance network, the line amplifier circuit including a send line amplifier and a receive line amplifier, the impedance network including three impedances Z 1 Z 2 and Z, one end of each of the impedances being connected to a common point; the output of the receive line amplifier being connected to the input of a receive path in the converter/balance circuit, the converter/balance circuit including a send path connected to the input of the send lirne amplifier via Z 2 in series with Z 3 the common point being connected to the output of the receive line amplifier via Z wherein the value of the impedances Z 2 and Z 3 are calculated from the 15 relationships: 4 5e Z I+Zt' 2 2 *Z *Y corresponds to 2* corresponds to Z' and Z r 0, and Zi "ICE here K, 1, and Y 1 Y 2 and Y are the admittances of Zt', and 2, respectively ;wherein the coefficients selected to achieve directional isolation basec on the hypothetical network also achieve directional isolation based on the impedance network.

2. A communication interface as claimed in claim 1, wherein the line amplifier circuit has a first transfer function, and the converter/balancing circuit includes a balancing arrangement and a codec.

3. An interface circuit as claimed in claim 1 or claim 2, woerein Z' is chosen to satisfy the inequality: Zmin Z, Z,; wherein Zmin is a minimum load permitted at the output of the receive line amplifier.

4. A communication interface circuit substantially as herein described with reference to the accompanying drawings.

5. A method of improving the noise immunity of a communication interface Including a line amplifier circuit connected to a converter/balancing circuit by an 15 impedance network, wherein the converter/balancing circuit includes a filter arrangement including digital filter means having programmable coefficients selected to achieve directional isolation based on the impedance of the line and the impedance of the impedance network, the line amplifier circuit including a send line amplifier and a receive line amplifier, the impedance network including 20 three impedances Z 2 and Z 3 one end of each of the impedances being connected to a common point; the output of the receive line amplifier being connected to the input of a receive path in the converter/balance circuit, the converter/balance circuit including a send path connected to the input of the send line amplifier via Z 2 in series with Z 3 the common point being connected to the output of the receive line amplifier via Z1'; wherein the value of the impedances Z 2 and Z 3 are calculated from the relationships: z22' 22 IL aK"A Zjr, 2 4S -I ~II 13 Z (ZZ, 1 1 +z/z, where Z, and Z 2 are high value impedances of an hypothetical network in which Z, corresponds to Z2 corresponds to Z 2 and Z 3 0, and Z;, Y, K I 1 3+Y where K, 1, and Y 1 Y2 and Y 3 are the admittances of Z 2 and Z 3 respectively ;wherein the coefficients selected to achieve directional isolation based on the hypothetical network also achieve directional isolation based on the impedance network.

6. A method of improving the noise immunity of a communication interface as S claimed in claim 4 wherein is chosen according to the inequality: Zmin Z' Z, 10 where Zmin is a minimum load permitted at the output of the receive line amplifier.

7, A method of improving the noise immunity of a communication interface substantially as herein descrited with reference to the accompanying drawings.

8 A communcation interface having its noise immunity improved by the method of anyone of claims 4 to 6. DATED THIS EIGHTEENTH DAY OF JUNE 1997 ALCATEL AUSTRALIA LIMITED ABSTRACT An impedance matching network includes impedances Z 1 Z 2 1 Z to reduce the effect of high frequency clock signal noise pick-up between a Subscriber Line Interface Circuit (SLIC), and its associated CODEC circuit (SLAC), the value of the impedances Z 2 1 Z being calculated by reference to a pair of hypothetical impedances Z, Z2 known to satisfy the operating conditions of the interface circuit such that: z, z 2 a a. .1 we Z 3 K Z S(Z, 1 Z Z the value of being less than Z 1 and greater than a minimum permitted load at the output of the receive line amplifier. see$ se e awe. -a