JPH0746482A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To adopt one signal output line to the device having a very small picture element by generating a vertical selection group selection pulse based on an output of each unit of a horizontal scanning circuit and other input pulse. CONSTITUTION:An H level is sequentially outputted to an output SRiA of each unit stage 11i of a horizontal scanning circuit 11 synchronously with a rising of an input clock PHI1A to the circuit 11 and latches an H level by one period of the clock PHI1A. Similarly, an H level is outputted to an output SRiB of each unit stage 12i of a horizontal scanning circuit 12 synchronously with the rising of the input clock PHI1B to the circuit 12 and latches the H level by one period of the clock PHI1B. Only when both the outputs SRiA, SRiB are at H level, an output of a 2-input AND circuit 13i goes to an H level, a switching FET 14i is selected and photoelectric conversion elements are sequentially scanned and its output is read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an XY address type solid-state image pickup device in which photoelectric conversion elements are arranged in a two-dimensional array.

[0002]

2. Description of the Related Art Conventionally, various types of solid-state image pickup devices are known. Among them, a plurality of photoelectric conversion elements arranged in a two-dimensional array and a plurality of photoelectric conversion elements arranged in the horizontal direction are known. A horizontal selection line group provided corresponding to the photoelectric conversion element,
A vertical scanning circuit for scanning in the vertical direction with respect to the photoelectric conversion element groups arranged in the horizontal direction through the horizontal selection line group;
An XY address type solid-state imaging device including a vertical selection line group provided corresponding to the photoelectric conversion elements arranged in the vertical direction and a horizontal scanning circuit provided corresponding to the vertical selection line group. There is. In this specification, a selection line selected by the horizontal scanning circuit is referred to as a vertical selection line, and a selection line selected by the vertical scanning circuit is referred to as a horizontal selection line.

Next, a conventional signal reading section of such an XY address type solid-state image pickup device will be described with reference to FIG. In FIG. 18, 101 is a horizontal scanning circuit, and each unit stage of the horizontal scanning circuit 101 is composed of a pulse shift unit consisting of two stages of clocked inverters, and two units of clocks Φ1 and Φ2 as shown in FIG. By inputting the phase clock and each inverted clock and applying the start pulse ΦST to the first stage unit, the high level pulse S is sequentially applied to each unit stage in synchronization with the rising edge of the clock Φ1.
R1, SR2, ... Are output. Each unit stage of the horizontal scanning circuit 101 is configured to correspond to two photoelectric conversion elements, and the output of each unit stage is CMO.
It is connected to the gates of two switching transistors 103 via an S-configured inverter circuit 102. The source of the switching transistor 103 is the signal line 104 of the photoelectric conversion element, and the drain is the signal output lines 105 and 106.
It is connected to the. Therefore, when a high level is output in the unit stage of the horizontal scanning circuit 101, two switching transistors are output through the two-stage inverter circuit 102.
103 is selected at the same time, signal output line 105 and signal output line
The signals of the two photoelectric conversion elements connected to the two switching transistors 103 are simultaneously read out via 106.

[0004]

As described above, the conventional X
The Y address type solid-state imaging device is provided with a unit stage of a horizontal scanning circuit so as to correspond to two photoelectric conversion elements so that it can correspond to a two-dimensional pixel array including fine photoelectric conversion elements, and the horizontal scanning circuit is arranged in the horizontal direction. 2 signals of the arranged photoelectric conversion elements
Two signal output lines are provided so that they can be read out one by one at the same time.
So-called two-line reading was performed.

However, in the 2-line read system, 2
Since it is necessary to provide two video signal processing systems having the same characteristics so as to correspond to the signal output line of the book, the circuit scale becomes large, and the signals of the two photoelectric conversion elements read at the same time are converted in time series. It is necessary to perform so-called synchronization, and it is easily affected by noise. For example, in two-line reading, the detection amplifier in the video signal processing system needs to have an amplifier having a band that is two to three times wider than the signal band, and as a result, the S / N deteriorates.

The present invention has been made in order to solve the above-mentioned problems in the conventional solid-state image pickup device of the two-line reading system, and it is possible to make the signal output line one line even in the case of having a minute photoelectric conversion element. It is an object of the present invention to provide a solid-state imaging device that does

[0007]

In order to solve the above problems, the present invention corresponds to a plurality of photoelectric conversion elements arranged in a two-dimensional array and the photoelectric conversion elements arranged in the horizontal direction. And a vertical scanning circuit for scanning the photoelectric conversion element group arranged in the horizontal direction through the horizontal selection line group in the vertical direction, and the vertical selection circuit arranged in the vertical direction. In a solid-state imaging device having a vertical selection line group provided corresponding to a photoelectric conversion element and a first horizontal scanning circuit provided corresponding to the vertical selection line group, the first horizontal scanning circuit comprises: Each unit scanning circuit unit is configured to correspond to a plurality of photoelectric conversion element rows of the photoelectric conversion element rows that respectively correspond to the vertical selection line group,
Further, by using the output of each unit scanning circuit unit of the first horizontal scanning circuit and the pulse input from other than the first horizontal scanning circuit as an input, a pulse for sequentially selecting the vertical selection line group is generated. A control circuit is provided.

In the solid-state image pickup device configured as described above, each unit scanning circuit unit of the first horizontal scanning circuit is made to correspond to the plurality of photoelectric conversion element arrays, and each unit scanning of the first horizontal scanning circuit is performed. Since a pulse for sequentially selecting the vertical selection line group is generated from the control circuit that receives the pulse input from the output of the circuit unit and the circuit other than the first horizontal scanning circuit, a single signal output line is generated. The signals of the photoelectric conversion elements are sequentially read, and the signal output line can be made into a single line even for a solid-state imaging device having a fine photoelectric conversion element.

[0009]

EXAMPLES Next, examples will be described. FIG. 1 is a schematic configuration diagram showing a signal reading unit of a first embodiment of a solid-state imaging device according to the present invention. In FIG. 1, 1 is a first horizontal scanning circuit, 2 is a second horizontal scanning circuit, which are arranged so as to be offset from each other by ½ unit stage, and each unit stage of each horizontal scanning circuit has two columns of photoelectric conversions. It corresponds to the element array. Reference numeral 3 is an input of the output of each unit stage of the first and second horizontal scanning circuits 1 and 2, and outputs a control signal for sequentially reading the signals of the photoelectric conversion elements 5 arranged in the horizontal direction.
It is a control circuit including an input AND circuit. Reference numeral 4 denotes a switch driven by a control signal from the control circuit 3. By sequentially driving the switch 4,
The signals of the photoelectric conversion element 5 are sequentially read out to the signal output line 6.

Next, a specific structure of the first embodiment shown in FIG. 1 will be described with reference to FIG. First horizontal scanning circuit 11
The unit stages (units) 11-1, 11-2, ... Consisting of are composed of a pulse shift unit having two stages of clocked inverters, and correspond to two photoelectric conversion elements arranged in the horizontal direction. Thus, the unit stages 11-1, 11-2, ... Are provided. The first horizontal scanning circuit 11 has a circuit configuration as shown in FIG. 3, and two-phase clocks Φ1, Φ2 and respective inverted clocks * Φ1, * Φ as shown in FIG.
By inputting 2 and applying the start pulse ΦST to the first-stage unit 11-1, in synchronization with the rising edge of the clock pulse Φ1, each unit stage 11-1, 11-2, ... Output signals SR1, SR2, ... Are output. Note that the horizontal scanning circuit shown in FIG. 3 can also be expressed as shown in FIG. 5 using symbols.

Reference numeral 12 is a second horizontal scanning circuit having the same structure as the first horizontal scanning circuit 11, and the first and second horizontal scanning circuits 11 and 12 are arranged so as to be offset from each other by ½ unit. Has been done. That is, the first and second horizontal scanning circuits 11 and 12
The first horizontal scanning circuit has the same structure and operating principle,
In 11 and the 2nd horizontal scanning circuit 12, the phase difference is provided in the clock which shifts a pulse.

13-1, 13-2, ... are 2-input AND circuits,
One of the inputs of the first and second AND circuits 11-1 and 11-2 is
Output SR1 of the first unit stage 12-1 of the second horizontal scanning circuit 12
The other input of the first AND circuit 13-1 connected to B is
Output SR1A of the first unit stage 11-1 of the first horizontal scanning circuit 11 corresponding to the first unit stage 12-1 of the second horizontal scanning circuit 12
Connect to. The other input of the second AND circuit 13-2 is connected to the output SR2A of the second unit stage 11-2 of the first horizontal scanning circuit 11. The third AND circuit 13-3 and the subsequent circuits are similarly connected. And each AND circuit 13-1,
The outputs of 13-2, ... are the signal lines 15-1, 15- of the photoelectric conversion element.
, And the signal output line 16 are connected to the respective gates of switching transistors 14-1, 14-2 ,. Two-input AND circuits 13-1, 13-2, ...
Fig. 6 shows a configuration example of. In FIG. 6, CONT1,
CONT2 is an input terminal, OUT is an output terminal, and _VH is High.
Level power supply, V _L indicates a low level power supply.

Next, the operation of the signal reading section of the first embodiment thus constructed will be described with reference to the timing chart shown in FIG. The outputs SR1A, SR2A, ... Of the unit stages 11-1, 11-2, ... Of the first horizontal scanning circuit 11
Is the clock Φ1 input to the first horizontal scanning circuit 11.
High level is output sequentially in synchronization with the rising edge of A,
The High level is held for one cycle of the clock Φ1A. Similarly, each unit stage 12-1, 12- of the second horizontal scanning circuit 12
2 ... Outputs SR1B, SR2B, ... Output high level in synchronization with the rising edge of the clock Φ1B input to the second horizontal scanning circuit 12,
High level is maintained for the period.

Therefore, at T0, the clock Φ1
High level is output to the output SR1A of the first unit stage of the first horizontal scanning circuit 11 in synchronization with the rising edge of A, and T2 is output.
High level output is held until. Further, at T1, a high level is output to the output SR1B of the first unit stage of the second horizontal scanning circuit 12 in synchronization with the rising of the clock Φ1B, and the high level is held until T3.
Since the clocks Φ1A and Φ1B have a phase difference, T1 to
During the period of T2, the outputs SR1A and SR1B of the first unit stage of the first and second horizontal scanning circuits 11 and 12 are both at the High level. The output of the two-input AND circuit becomes High level only when both inputs are at High level. Therefore, the second
The output OUT1 of the first 2-input AND circuit 13-1 connected to the output SR1B of the first unit of the horizontal scanning circuit 12 is High.
Becomes the level, and the output OU of the first 2-input AND circuit 13-1
The switching transistor 14-1 connected to T1 is selected.

At T2, the output SR1A of the first unit stage of the first horizontal scanning circuit 11 changes from High level to Low level in synchronization with the rising of the clock Φ1A, and the output SR2A of the second unit stage 11-2. Output from Low level to Hi
It becomes the gh level, and then the High level is held until T4. Output SR of the first stage unit stage 12-1 of the second horizontal scanning circuit 12
1B holds High level from T1 to T3,
During the period from T2 to T3, the first stage unit stage of the second horizontal scanning circuit 12
The output SR1B of 12-1 and the output SR2A of the second unit stage 11-2 of the first horizontal scanning circuit 11 are both at high level. Therefore, the inputs of the second AND circuit 13-2 connected to the output SR1B of the first unit stage 12-1 of the second horizontal scanning circuit 12 are both at the high level, and the output O of the second AND circuit 13-2 is 0.
The switching transistor 14-2 connected to UT2 is selected. After T3, the above operation is repeated, and the switching is sequentially connected to the outputs OUT3, OUT4, ... Of the third, fourth, ... AND circuits 13-3, 13-4 ,. The transistors 14-3, 14-4, ... Are selected. As a result, the signals S1 and S of the photoelectric conversion elements arranged in the horizontal direction are
2, ... Are sequentially read out to the signal output line 16.

As described above, each unit stage of the two horizontal scanning circuits having the same structure and operation principle is provided so as to correspond to the two photoelectric conversion elements, and the output of each unit stage of the two horizontal scanning circuits is provided. By time-sharing with the two 2-input AND circuits and selecting the switching transistor, the signal output line can be made into a single line even in a solid-state imaging device having a fine photoelectric conversion element.

In this embodiment, the signal reading section is provided with a control circuit for generating a pulse for sequentially selecting the vertical selection line groups from the outputs of the two horizontal scanning circuits, but n (n is n A control for generating a pulse for sequentially selecting a vertical selection line group from the output of each unit stage of the horizontal scanning circuit by using the horizontal scanning circuits of 2 or more) Obviously, configuring the circuit is also extremely easy.

Next, the second embodiment will be described. Figure 8
FIG. 7 is a circuit configuration diagram showing a signal reading unit of a second embodiment. In FIG. 8, reference numeral 21 denotes a horizontal scanning circuit, and the unit stages 21-1, 21-2, ... Constituting the horizontal scanning circuit 21 are pulse shift units having two clocked inverter stages as shown in FIG. The two-phase clocks of the clocks Φ1 and Φ2 as shown in FIG. 4 and the respective inverted clocks * Φ1 and * Φ2 are input to the horizontal scanning circuit 21,
By applying the start pulse ΦST to the initial stage unit 21-1 of the scanning circuit 21, the unit stages 21-1, 21-2, ... Of the horizontal scanning circuit 21 are sequentially arranged in synchronization with the rising edge of the clock Φ1. High-level output signals SR1, SR2
... is output. The horizontal scanning circuit
Outputs SR1, SR2 of 21 unit stages 21-1, 21-2, ...
... are provided so as to correspond to the respective unit stages 21-1, 21-2, ... Of the horizontal scanning circuit 21, and each pair of first and second two-input AND circuits 22-1, 22 are provided. -2; 22-3, 22-4; ... is input to one of the input terminals of the AND circuit 22-1,
Control pulses ΦCONT1 and ΦCONT2 are input to the other input terminals of 22-2; 22-3, 22-4; First and second AND circuits 22-1, 22-
2; 22-3, 22-4; ... outputs OUT1, OUT2, ...
Is a switching transistor 23-1, provided between the signal lines 24-1, 24-2, ... Of the photoelectric conversion element and the signal output line 25.
Input is made to each gate of 23-2, ....

Next, the operation of the signal reading section of the second embodiment having such a configuration will be described with reference to the timing chart shown in FIG. Outputs SR1, SR2, ... Of the unit stages 21-1, 21-2, ... Of the horizontal scanning circuit 21
Are sequentially set to the high level in synchronization with the rising of the clock Φ1, and the output of each unit stage is held at the high level for one cycle of the clock Φ1. 2-input AND
The circuit outputs only when both inputs are high level
High level. Therefore, at T0, the control pulse ΦCONT1 is set to the High level in synchronization with the output SR1 of the first unit stage of the horizontal scanning circuit 21 being set to the High level in synchronization with the rising edge of the clock Φ1. The inputs of the circuit 22-1 are both at high level, and the output OUT1 of the first AND circuit 22-1 is at high level. The control pulse ΦCONT1 is held at a high level for 1/2 cycle of the clock Φ1, that is, for a period of T0 to T1 from the rising of the clock Φ1,
The switching transistor 23-1 to which the output OUT1 of the first AND circuit 22-1 is connected is selected, and the signal S1 of the photoelectric conversion element connected to the signal line 24-1 is read out to the signal output line 25.

Next, at T1, the control pulse Φ
The control pulse ΦCONT2 rises in synchronization with the fall of CONT1. Control pulse ΦC
Even after ONT2 goes high, the horizontal scanning circuit 21
Since the output SR1 of the first unit stage 21-1 of the second AND circuit 22-2 is held at the High level, the output OUT2 of the second AND circuit 22-2 becomes Hi during the period when the control pulse ΦCONT2 is at the High level.
gh level, the switching transistor 23-2 is selected, and the signal S2 of the photoelectric conversion element connected to the signal line 24-2.
Is read. In the same manner, the signals S3, S4, ... Of the photoelectric conversion elements are sequentially read out to the signal output line 25.

As described above, in this embodiment, the period of time when the output of each unit stage of the horizontal scanning circuit is at High level is 1/2.
Time-sharing each, during the period when the output of each unit stage is High level,
Since the two switching transistors are sequentially selected, the signal output line can be made into a single line with a smaller number of transistors as compared with the first embodiment.

In this embodiment, a 2-input AND circuit is used as the control circuit, and the output of each unit stage of the horizontal scanning circuit is
Although a configuration is shown in which the high level period is time-divided by 1/2, an n (n is an integer greater than 2) input AND circuit is used, and the output of each unit stage of the horizontal scanning circuit is at the high level. Obviously, it is extremely easy to adopt a configuration in which the period is time-divided by 1 / n. Further, in the above-mentioned embodiment, the two-input AND circuit is used as the two-input gate, but a two-input NAND circuit may be used.

Further, in this embodiment, the output of each unit stage of the horizontal scanning circuit 21 is switched through the two-input AND circuits 22-1, 22-2, ... To the switching transistors 23-1, 23-2 ,. .., control pulses .PHI.CONT1 and .PHI.CONT input to a 2-input AND circuit
By controlling 2, the read mode different from the read mode shown in the timing chart of FIG. 9 can be realized.

For example, as shown in the timing chart of FIG. 10, by fixing the control pulse ΦCONT1 to a low level, the first AND circuits 22-1, 22-3,
Outputs OUT1, OUT3, ... Of the horizontal scanning circuit 2
Regardless of the output of each corresponding unit stage of 1, the switching transistor 23-1, 23-3, ... Which is always at the low level and is connected to the first AND circuit 22-1, 22-3 ,.・ Is not selected. On the other hand, the control pulse ΦCONT2 is High
By fixing the level to the level, the output of each unit stage of the horizontal scanning circuit 21 sequentially becomes High level, and the second AND
Outputs OUT2, OUT4, ... Of the circuits 22-2, 22-4 ,.
Become high level sequentially, and the second AND circuits 22-2, 22-
Switching transistors 23-2, 2 connected to 4, ...
Only 3-4, ... will be selected.

Similarly, as shown in the timing chart of FIG. 11, the control pulse ΦCONT2 is set to low level,
By fixing the control pulse ΦCONT1 to the high level, only the switching transistors 23-1, 23-3, ... Connected to the first AND circuits 22-1, 22-3 ,. become. Therefore, by switching the two control pulses ΦCONT1 and ΦCONT2 between the high level and the low level for each horizontal reading period, in the photoelectric conversion elements arranged in the horizontal direction, every other signal of the photoelectric conversion element is read out. Thinning scanning can be performed.

Furthermore, as shown in the timing chart of FIG. 12, control pulses ΦCONT1 and ΦCO
By pulse-driving NT2 only for a certain period, the signal of the photoelectric conversion element at an arbitrary position can be read, and block access or random access can be performed.

For example, the control pulses ΦCONT1 and ΦCONT2 are constantly fixed to the low level during the period of T0 to T1, so that the first and second AND circuits 22-1, 22- provided in the first unit stage 21-1 are provided. 2 outputs OUT1, O
UT2 is the output SR of the first unit stage 21-1 of the horizontal scanning circuit 21.
Regardless of 1, it is fixed at Low level. At T1, the output SR2 of the second unit stage 21-2 of the horizontal scanning circuit 21 becomes Hi.
Control pulse ΦC in synchronization with gh level
Turn ONT1 from low level to high level and clock Φ
By holding the High level for 1/2 cycle of 1, the switching transistor 23-3 connected to the output OUT3 of the first AND circuit 22-3 is selected. Then, in synchronization with the control pulse ΦCONT1 changing from the high level to the low level, the control pulse ΦCONT2 is changed.
By changing from low level to high level, the second A
The switching transistor 23-4 connected to the output OUT4 of the ND circuit 22-4 is selected. The above operation is performed until T2. After T2, control pulse ΦCONT1 again
And by fixing ΦCONT2 to low level,
Output OU of the first and second AND circuits 22-7, 22-8, ...
T7, OUT8, ... Are fixed to the low level regardless of the output of the corresponding unit stage of the horizontal scanning circuit 21.

Therefore, by pulse-driving the control pulses ΦCONT1 and ΦCONT2 during the period from T1 to T2, only the signals S3 to S6 of the photoelectric conversion element corresponding to the period from T1 to T2 can be read. Since the position of the photoelectric conversion element that reads the signal can be controlled by the control pulses ΦCONT1 and ΦCONT2, the signal of the photoelectric conversion element at an arbitrary position can be read.

Next, a third embodiment will be described. FIG. 13 is a circuit configuration diagram showing a signal reading unit of the third embodiment.
In FIG. 13, reference numeral 31 denotes a horizontal scanning circuit.
The unit stages 31-1, 31-2, ... Constituting the same are each composed of a pulse shift unit with two stages of clocked inverters as shown in FIG. The two-phase clocks of the clocks Φ1 and Φ2 as shown in FIG. 4 and the respective inverted clocks * Φ1 and * Φ2 are input, and the start pulse Φ is input to the first stage unit 31-1 of the scanning circuit 31.
By applying ST, each unit stage 31-1, 31-2, ... Of the horizontal scanning circuit 31 is synchronized with the rising edge of the clock Φ1.
Are output signals SR1 and S that are sequentially output at a high level.
R2, ... Is output.

Each unit stage 31-1, 31- of the horizontal scanning circuit 31
The outputs SR1, SR2, ... Of 2, ...
31-2, ... Inverter circuits 32-1 and 32-2 having a pair of first and second CMOS configurations provided so as to correspond to 32-1, 32-2; 32
-3, 32-4; ... are connected to the sources of P-channel type MOS transistors. The source of the N-channel MOS transistor of the inverter circuit is connected to the GND level, the drain of the P-channel MOS transistor and the drain of the N-channel MOS transistor are connected to each other, and the output of the inverter circuit of CMOS configuration is provided. Has become. Further, a P-channel type MOS transistor and an N-channel type MO transistor forming the first and second CMOS inverter circuits 32-1, 32-2; 32-3, 32-4;
The control pulses ΦCONT1 and ΦCONT2 are applied to the gates of the S-transistors, respectively.
And second CMOS inverter circuits 32-1 and 32-2;
32-3, 32-4; ... Outputs OUT1, OUT2, ...
Is a switching transistor 33- provided between the signal lines 34-1, 34-2, ... Of the photoelectric conversion element and the signal output line 35.
Inputs are connected to the gates 1, 33-2, ....

Next, the operation of the signal reading section of the third embodiment having such a configuration will be described with reference to the timing chart shown in FIG. Outputs SR1, SR2, ... Of the unit stages 31-1, 31-2, ... Of the horizontal scanning circuit 31
Becomes high level in synchronization with the rising edge of the clock Φ1, and is held at the high level for one cycle of the clock Φ1. At T0, the control pulse ΦCONT1 is changed from the high level to the low level in synchronization with the output SR1 of the first-stage unit stage 31-1 being in the high level in synchronization with the rising edge of the clock Φ1, whereby the first CMOS
Inverter circuit 32-1 having a P-channel type MOS transistor is turned ON, and an inverter circuit having a first CMOS configuration
High level is output to the output OUT1 of 32-1. The control pulse ΦCONT1 is for 1/2 cycle of the clock Φ1 from the rising of the clock Φ1, that is, T0 to
The switching transistor 33-1 connected to the output OUT1 of the inverter circuit 32-1 having the first CMOS configuration is held at the low level for the period of T1, and the photoelectric conversion element connected to the signal line 34-1 is selected. The signal S1 is read out to the signal output line 35.

Next, at T1, the control pulse Φ
In synchronization with the rising of CONT1, the control pulse ΦCONT2 changes from the high level to the low level, the P-channel type MOS transistor of the second CMOS inverter circuit 32-2 is turned on, and the second CMOS inverter circuit 32- The output OUT2 of 2 becomes High level.
Even after the control pulse ΦCONT2 falls, the output SR1 of the first unit stage 31-1 of the horizontal scanning circuit 31 remains Hi.
Since it is held at the gh level, the output of the inverter circuit 32-2 having the second CMOS configuration is held at the High level for the latter half cycle of one cycle of the clock Φ1 and the second CMOS
The switching transistor 33-2 connected to the configured inverter circuit 32-2 is selected, and the signal S2 of the photoelectric conversion element connected to the signal line 34-2 is read. Thereafter, in the same manner, the signals S3, S4, ... Of the photoelectric conversion elements are sequentially read out to the signal output line 35.

As described above, in this embodiment, since the control circuit is configured by providing two CMOS inverter circuits in each unit stage of the horizontal scanning circuit, the number of transistors is smaller than that in the second embodiment. In the solid-state imaging device having a fine photoelectric conversion element, the signal output line can be integrated into one line.

Further, this embodiment is similar to the second embodiment in that
Two CMOS inverter circuits 32-1, 32-2; 32-
Control pulse input to 3, 32-4;
By controlling T1 and ΦCONT2, a read mode different from the read mode shown in the timing chart of FIG. 14 can be realized. That is, the horizontal scanning circuit 31
Since the output of each unit stage of is connected to the switching transistor through the inverter circuit of CMOS configuration, by controlling the control pulses ΦCONT1 and ΦCONT2 input to the gate of the inverter circuit of CMOS configuration, the other read modes are can do.

For example, as shown in the timing chart of FIG. 15, by fixing the control pulse ΦCONT1 at the low level and the ΦCONT2 at the high level,
The first CMOS configuration inverter circuit 32-1, 32-3, ...
Is a P-channel type MOS transistor and is a second CMOS
In the configured inverter circuits 32-2, 32-4, ..., N-channel type MOS transistors are always turned on. Therefore, the output SR1, of each unit stage 31-1, 31-2, ... Of the horizontal scanning circuit 31
As SR2, ... sequentially become high level, only the outputs OUT1, OUT3, ... Of the first CMOS inverter circuits 32-1, 32-3 ,. C
Output O of MOS inverter circuits 32-2, 32-4, ...
UT2, OUT4, ... are always low level. As a result, the first CMOS inverter circuits 32-1 and 32
-3, ... Switching transistor 33-1 connected to
Only 33-3, ... are selected.

As shown in the timing chart of FIG. 16, the control pulse ΦCONT2 is set to low level,
By fixing ΦCONT1 to High level, the second
Only the switching transistors 33-2, 33-4, ... Connected to the outputs OUT2, OUT4, ... Of the CMOS inverter circuits 32-2, 32-4 ,. , Thinning-out scanning can be performed to read out the signal of the photoelectric conversion element every other.

Block control and random access are possible by pulse-driving the control pulses ΦCONT1 and ΦCONT2 only during the period corresponding to the portion to be read and fixing it at the High level during the other periods. The input of the CMOS inverter circuit is Hi
The output is always Low level at gh level. Therefore, for example, in the timing chart shown in FIG.
Control pulse ΦCONT1 and Φ for a period of 0 to T1
By fixing CONT2 to the high level, the inverter circuits 32-1 and 32-2 having the first and second CMOS configurations are provided regardless of the output SR1 of the first unit stage 31-1 of the horizontal scanning circuit 31.
Both outputs OUT1 and OUT2 are at low level,
The switching transistors 33-1 and 33-2 are not selected.
At T1, the control pulse ΦCONT1 is changed from the high level to the low level in synchronization with the rising of the clock Φ1, so that the output OUT3 of the inverter circuit 32-3 having the first CMOS configuration becomes the high level, and the switching transistor 33-3 is turned on. To be selected.

On the other hand, in synchronization with the control pulse ΦCONT1 changing from the low level to the high level at T2, the control pulse ΦCONT2 is changed from the high level to the low level, so that the inverter circuit 32-2 of the second CMOS structure is provided. The output OUT2 becomes High level, and the output O of the inverter circuit 32-2 having the second CMOS configuration is output.
The switching transistor 33-2 connected to UT2 is selected. After T3, by fixing the control pulses ΦCONT1 and ΦCONT2 to the high level again, the inverter circuits 32-7, 32-
The output of 8, ... becomes Low level and the switching transistors 33-7, 33-8, ... are not selected. Thereby, only the signal of the photoelectric conversion element at the position corresponding to the period of T1 to T3 can be read.

[0039]

As described above on the basis of the embodiments,
According to the present invention, the pulse for sequentially selecting the vertical selection line group is generated from the output of each unit of the first horizontal scanning circuit and the control circuit which receives the pulse input from other than the horizontal scanning circuit. Since it is configured as described above, even if the solid-state imaging device having a fine photoelectric conversion element is used,
It can be linearized.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a schematic configuration of a signal reading unit of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit configuration diagram showing a specific configuration of a signal reading unit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a first horizontal scanning circuit shown in FIG.

FIG. 4 is a timing chart for explaining the operation of the horizontal scanning circuit shown in FIG.

5 is a diagram showing the horizontal scanning circuit shown in FIG. 3 using symbols.

FIG. 6 is a circuit configuration diagram showing a configuration example of a 2-input AND circuit in FIG.

FIG. 7 is a timing chart for explaining the operation of the signal reading unit shown in FIG.

FIG. 8 is a circuit configuration diagram showing a signal reading unit of a second embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the signal reading unit of the second embodiment shown in FIG.

FIG. 10 is a timing chart for explaining another operation of the signal reading unit of the second embodiment shown in FIG.

FIG. 11 is a timing chart for explaining still another operation of the signal reading unit of the second embodiment shown in FIG.

FIG. 12 is a timing chart for explaining still another operation of the signal reading unit of the second embodiment shown in FIG.

FIG. 13 is a circuit configuration diagram showing a signal reading unit according to a third embodiment of the present invention.

FIG. 14 is a timing chart for explaining the operation of the signal reading unit of the third embodiment shown in FIG.

15 is a timing chart for explaining another operation of the signal reading unit of the third embodiment shown in FIG.

16 is a timing chart for explaining still another operation of the signal reading unit of the third embodiment shown in FIG.

FIG. 17 is a timing chart for explaining still another operation of the signal reading unit of the third embodiment shown in FIG.

FIG. 18 is a block configuration diagram showing a signal reading unit of a conventional solid-state imaging device.

19 is a timing chart for explaining the operation of the conventional signal reading unit shown in FIG.

[Explanation of symbols]

 1 1st horizontal scanning circuit 2 2nd horizontal scanning circuit 3 control circuit 4 switch 5 photoelectric conversion element 6 signal output line 11 1st horizontal scanning circuit 12 2nd horizontal scanning circuit 13-1, 13-2 ,. ..2-input AND circuits 14-1, 14-2, ... Switching transistors 15-1, 15-2, .. Signal line 16 Signal output line 21 Horizontal scanning circuits 22-1, 22-3, ..・ First two-input AND circuits 22-2, 22-4, ... Second two-input AND circuits 23-1, 23-2, ... Switching transistors 24-1, 24-2 ,. Signal line 25 Signal output line 31 Horizontal scanning circuit 32-1, 32-3, ... First inverter circuit 32-2, 32-4, ... Second inverter circuit 33-1, 33-2, ... Switching transistors 34-1, 34-2, ... Signal line 35 Signal output line

Claims (6)

[Claims] 1. A plurality of photoelectric conversion elements arranged in a two-dimensional array, a group of horizontal selection lines provided corresponding to the photoelectric conversion elements arranged in a horizontal direction, and a group of horizontal selection lines. And a vertical scanning circuit for performing vertical scanning on a photoelectric conversion element group arranged in a horizontal direction, a vertical selection line group provided corresponding to the photoelectric conversion element arranged in a vertical direction, and the vertical selection line group. In a solid-state imaging device having a first horizontal scanning circuit provided corresponding to a selection line group, the first horizontal scanning circuit includes a plurality of photoelectric conversion element columns corresponding to the vertical selection line group. Each unit scanning circuit unit is configured to correspond to the conversion element array, and further, an output of each unit scanning circuit unit of the first horizontal scanning circuit and a pulse input from other than the first horizontal scanning circuit Input the A solid-state imaging device comprising a control circuit for generating a pulse for sequentially selecting a selected line group. 2. The control circuit, when the photoelectric conversion element array corresponding to the vertical selection line is N (N is an integer of 2 or more), the control circuit includes one unit scanning circuit unit and one unit scanning circuit unit of the first horizontal scanning circuit.
/ N unit units are provided with second to Nth horizontal scanning circuits having a similar structure and are controlled by output pulses of the respective unit units of the first and second to Nth horizontal scanning circuits. 2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured to form a pulse for sequentially selecting the vertical selection line group. 3. The solid-state imaging device according to claim 1, wherein the control circuit is configured to be controlled by a control signal input from the outside. 4. The AN is provided corresponding to each unit scanning circuit unit of the first horizontal scanning circuit.
2. A D or NAND circuit.
Alternatively, the solid-state image pickup device according to item 3. 5. The solid-state imaging device according to claim 1, wherein the control circuit comprises an inverter circuit group provided corresponding to each unit scanning circuit unit of the first horizontal scanning circuit. . 6. A pulse for sequentially selecting the vertical selection line group is generated only in a specific period within the horizontal read period, and a pulse for sequentially selecting the vertical selection line group is not generated except for the specific period. 6. The control signal of the control circuit is set in the device, and the signal of the photoelectric conversion element at any position of the two-dimensional photoelectric conversion element array can be read out. The solid-state imaging device according to claim 1.