JPH0746135A - Ternary code transmission/reception circuit - Google Patents

Abstract

PURPOSE:To easily make an integrated circuit of a circuit regardless of a large number of codes to be transmitted in parallel and to prevent a device from being large-sized and expensive by using a three-state buffer circuit which sends three kinds of signals. CONSTITUTION:A three-state buffer circuit 3 which takes a binary code an to be transmitted as the input and goes to the open state in accordance with the input to the enable terminal and an adding circuit 1 which inputs a carry signal kn to the enable terminal of this buffer circuit 3 are included to constitute a transmission part. A comparing circuit 8 which compares a threshold between the intermediate value and the maximum value of a ternary code cn with the ternary code cn, a comparing circuit 7 which compares a threshold between the intermediate value and the minimum value of the ternary code cn with the ternary code cn, and an exclusive OR circuit 11 which decodes the ternary code cn based on comparison results of these comparing circuits are included to constitute a reception part. Thus, the ternary code can be transmitted with one transmission line, and a transformer which is required conventionally is unnecessary to easily make an integrated circuit of the circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary code transmission / reception circuit, and more particularly to a ternary code transmission / reception circuit for converting a binary code into a ternary code for transmission.

[0002]

2. Description of the Related Art In general, a ternary code such as a bipolar code or a class 4 partial response code does not include a DC component in its signal component, and a transmission line having a transformer coupling by utilizing the characteristics of spectrum distribution, or It is applied to narrow band transmission lines.

Further, since the code is originally a binary code converted into a ternary code, it has redundancy in the level direction, but the redundancy is utilized to detect code errors and to perform coding rules. It is common practice to perform a temporary disturbing violating operation and also transmit sub-information in addition to the main information. Here, a conventional ternary code transmission / reception circuit will be described with reference to the drawings.

FIG. 5 is a block diagram showing the configuration of an example of a conventional ternary code transmission / reception circuit. In the figure, there is no band limitation on the transmission path (for example, when connecting with a relatively short cable or the like in the same device), and it is intended to enable transmission of sub information in addition to the main information.

In the figure, main information an (binary code) is converted into a ternary code Cn by an encoding circuit 101, and a polarity reversing circuit 103 controls the polarity reversal, and then a transformer 104.
Is transmitted to the transmission line 105 via. However, the polarity inversion is performed when the pattern detection circuit 102 monitors the code sequence of the code processed inside the encoding circuit 101 and detects a predetermined pattern.

On the other hand, on the receiving side, the ternary code is received via the transformer 106, and the decoding circuit 107 decodes it to the original binary code (dn = an) and violates the code sequence of the ternary code. The pattern detection circuit 108 detects the operated predetermined pattern, and when the predetermined pattern is not detected, an alarm signal ALM is transmitted as a reception abnormality.

[0007]

The conventional ternary code transmission / reception circuit described above requires two transformers and a pair of cables or transmission lines between transmission and reception. Therefore, for example, when transmitting N codes in parallel between transmission and reception, N pairs of cables and 2N transformers are required.

In that case, the transformer is difficult to be integrated into a circuit and is generally expensive. Therefore, there is a drawback in that the larger the N, the larger the size of the device and the higher the price.

The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to easily integrate it into an integrated circuit even when the number of codes to be transmitted in parallel is large.
An object of the present invention is to provide a ternary code transmission / reception circuit that does not increase the size and cost of the device.

[0010]

A ternary code transmitting / receiving circuit according to the present invention transmits a ternary code in which predetermined information is added to a binary code to be transmitted, receives the transmitted ternary code, and decodes the ternary code. A ternary code transmission / reception circuit for converting the ternary code transmission / reception circuit having a three-state buffer circuit for transmitting three kinds of signals corresponding to the ternary code, and an intermediate value and a maximum value of the ternary code. A first comparison circuit having a predetermined threshold value between the three-valued code and the first comparison circuit, and a predetermined threshold value between the intermediate value and the minimum value of the three-valued code, And a ternary code receiving circuit having a decoding circuit for decoding the ternary code into the binary code and the predetermined information based on a result of the comparison. Characterize.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a ternary code transmission / reception circuit according to the present invention, and the same portions as those in FIG. 5 are designated by the same reference numerals. In the figure, a ternary code transmission / reception circuit according to an exemplary embodiment of the present invention includes a transmission unit, a transmission line, and a reception unit.

The transmitter receives a binary code an to be transmitted as an input, and becomes a open state (high impedance state) in response to the input to the enable terminal.
State buffer circuit) 3, an adder circuit 1 for inputting a carry signal kn to the enable terminal of the buffer circuit 3, and a delay circuit 2 for delaying its output signal bn by 2T (T is a unit time). And a total of three-level code Cn in which an open state is added in addition to the binary code an
Has the function of transmitting. Note that the code an takes a value of 0 or 1 for each unit time T, and an shows the code at the time n T.

Further, the receiving unit has a predetermined threshold value between the intermediate value and the maximum value of the ternary code Cn, and the threshold value and the ternary code Cn.
A comparison circuit 8 for comparing n with a predetermined threshold value between the intermediate value and the minimum value of the ternary code Cn and the ternary code Cn.
It includes a comparison circuit 7 for comparing n and an exclusive OR circuit 11 for decoding the ternary code Cn based on the comparison result of these comparison circuits, and has a polarity in addition to the binary code dn. The information ln is output. In addition, 5 and 6 are resistors for voltage division.

Furthermore, 4 in the figure is a transmission line, and 12
Is a ground line for matching the ground levels of the transmitter and the receiver.

In such a configuration, a binary code an having a logic level of 0 or 1 is added to one input terminal of the adder circuit 1 and the three-state buffer circuit 3.

The output signal bn of the adder circuit 1 is supplied to the delay circuit 2
And its output signal b (n-2) is applied to the other input terminal of the adder circuit 1. The carry signal kn obtained as a result of the operation in the adder circuit 1 is added to the control terminal of the 3-state buffer circuit, and when kn = 0, the input of the 3-state buffer circuit is passed as it is, and when kn = 1. Open the output.

The class 4 partial response coding law for explaining the relationship between the class 4 partial response coding law and each code in the transmitting section is as follows: bn = an * b (n-2) (1) cn = bn-b (n-2) is represented by (2).

However, in the equations (1) and (2), * indicates addition of modulo 2, bn is a precoded code, and cn is a class 4 partial response code.

From the relationship of the equations (1) and (2), cn is + a
Since n or -an, if ann = 0, then cn = 0, a
When n = 1, cn = + 1 or −1, and decoding from cn is 0 if cn = 0 and 1 if cn = + 1 or −1.
Is decrypted.

On the other hand, the relationship between the symbols in FIG. 1 is as shown in FIG. In the figure, Cn represents the logic of a three-state buffer circuit, and the voltage level appearing on the transmission line 4 is determined by the power supply voltage Vcc and the voltage division ratio of the resistors 5 and 6. The relationship between the logic of Cn and the voltage level on the transmission line is set as shown in FIG.

Here, FIG. 4 is a time chart showing a method of decoding and polarity detection in the receiving section. In the figure, V9 by the reference voltage source 9 of the level comparison circuit 7 is set between the 0 level and Vcc / 2. Further, V10 by the reference voltage source 10 of the level comparison circuit 8 is set to the middle of Vcc / 2 and Vcc. Vcc is the power supply voltage of the circuit.

In the figure, the waveform of an matches the waveform of dn, and it can be seen that dn reproduces an from the ternary waveform. Further, the waveform of kn and the waveform of ln match, and ln indicates the polarity (negative polarity) of the ternary class 4 partial response code.

Although the waveform on the transmission line in FIG. 4 obviously includes the DC component and is different from the waveform of the class 4 partial response code, the transmission line 4 can also transmit the DC component, and the purpose of the present embodiment is. Since the main information and the polarity information of the class 4 partial response code are transmitted at the same time by using one transmission line, the circuit of FIG. 1 achieves that purpose. That is, it is possible to transmit and receive a ternary code to which sub information (polarity information) is added in addition to the binary code an which is originally to be transmitted.

Transmission of sub-information such as status information by violating a class 4 partial response code is described in Japanese Examined Patent Publication No. 1-31744, but as an application example of the present invention, the code of FIG. bn
, A carry pattern kn is operated when the pattern is detected, polarity inversion control is performed, and the reception side detects the presence or absence of a violation operation on the transmission side from the code sequence of dn and ln. Then, the sub information can be obtained.

With the above configuration, it is possible to transmit a ternary code using one transmission line (excluding the ground line between the transmitter and the receiver), and the transformer which has been conventionally required is not required. It is easy to integrate the circuit into an integrated circuit, downsizing,
The price can be reduced. In particular, in the case of transmitting N codes in parallel, the conventional ternary code transmission circuit required 2N transformers and 2N transmission lines, but no transformer is required, and N transmission lines are required. And can be transmitted by one ground line.

[0027]

As described above, according to the present invention, it is possible to transmit a ternary code by using one transmission line, and further, the transformer which has been conventionally required is not required, and the circuit can be easily integrated. Therefore, there is an effect that downsizing and cost reduction can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a ternary code transmission / reception circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between respective symbols in FIG.

FIG. 3 is a diagram showing a relationship between a value of a ternary code and a voltage level of a transmission line 4.

FIG. 4 is a time chart showing the operation of the ternary code transmission / reception circuit of FIG.

FIG. 5 is a block diagram showing a configuration of a conventional ternary code transmission / reception circuit.

[Explanation of symbols]

 1 Adder circuit 2 Delay circuit 3 3 State buffer circuit 4 Transmission line 5 and 6 Resistor 7 and 8 Level comparison circuit 9 and 10 Reference voltage source 11 Exclusive OR circuit

Claims (2)

[Claims] 1. A ternary code receiving circuit for decoding a ternary code consisting of a binary code sent from a transmitting side and predetermined information added to the binary code, the intermediate value and the maximum value of the ternary code. A first comparison circuit having a predetermined threshold value between the three-valued code and the threshold value, and a predetermined threshold value between an intermediate value and a minimum value of the three-valued code. A second comparison circuit that compares a threshold value with the ternary code; and a decoding circuit that decodes the ternary code into the binary code and the predetermined information based on the comparison result. Ternary code receiving circuit. 2. A ternary code transmission / reception circuit for transmitting a ternary code in which predetermined information is added to a binary code to be transmitted, and receiving and decoding the ternary code thus transmitted, said ternary code A ternary code transmission circuit having a three-state buffer circuit for transmitting three types of signals corresponding to codes, and a threshold value and the ternary value having a predetermined threshold value between an intermediate value and a maximum value of the ternary code. A first comparison circuit for comparing a code and a second comparison circuit having a predetermined threshold value between an intermediate value and a minimum value of the ternary code and comparing the threshold value and the ternary code; Based on these comparison results, the ternary code is converted into the ternary code.
A ternary code receiving circuit having a value code and a decoding circuit for decoding the predetermined information, and a ternary code transmitting / receiving circuit.