JPH10327065A - Level conversion circuit and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the level of output signal in the case that a reception side is the low power consumption by controlling a tri-state buffer by control signals and turning the level of the output signals to a desired value. SOLUTION: A control circuit 6 generates first control signals Ai (i)=1 (n) } so as to turn the output of the (n-1) or (n) pieces of buffers 4-i among the plural tri-state buffers 4-i to a high impedance state corresponding to the level of second control signals Cj (j)=1-(m)} and outputs them to the buffers 4-i. The buffers 4-i output signals based on a power supply voltage Vi corresponding to the level of the high impedance state and input signals IN to a first signal line 8 by the level of the signals Ai. The signal line 8 outputs the output signals based on the power supply voltage connected to one selected tri-state buffer in the high impedance state when all the buffers 4-i lave high impedance and not in the high impedance state when the (n-1) pieces of the buffers 4-i are the high impedance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit and an electronic device such as a communication device equipped with the level conversion circuit.

[0002]

2. Description of the Related Art Electronic devices such as communication devices are equipped with various packages (hereinafter, referred to as PKG), and transmit and receive signals between the packages. When a transmission PKG that operates at a lower voltage than a conventional transmission PKG is newly developed, it is necessary to match the operating voltage of the connected receiving PKG with the interface voltage. In this case, the transmission package is provided with an interface circuit for converting to a voltage for the reception package.

Further, even if the receiving PKG is newly operated at a low voltage, an interface circuit for converting the output level of the transmitting PKG into a voltage for the receiving PKG is provided on the receiving PKG side.

[0004] Communication devices are designed based on ITU recommendations, but there is a strong demand for reduction in power consumption, reduction in size of devices, and improvement in reliability. Even if a new PKG is developed and the internal operation is driven at a lower voltage than before, the interface voltage is fixed at the existing voltage, and the interface circuit uses the interface between the existing voltage and the low voltage. I have.

[0005]

However, even if the internal operation of the PKG is realized with a lower voltage drive than before, the voltage of the interface is fixed at the existing voltage, so that the power consumption at the interface becomes large. As a result, PK
It cannot be ignored that the power consumption as G increases.

[0006] In addition, an increase in power consumption as a device raises concerns about reliability as an electronic device such as a communication device. Furthermore, a newly developed low-voltage transmission PK
In G, since the operation voltage is fixedly converted to the operation voltage of the reception PKG, if the operation voltage of the reception PKG is different, an interface circuit corresponding to the voltage is required for the transmission PKG, and there is a problem that the development cost is increased. .

In view of the above, the present invention provides a level conversion circuit that can easily convert a received PKG to a voltage for a received PKG no matter what voltage the received PKG operates, and an electronic device having the level conversion circuit. It is intended to be.

[0008]

FIG. 1 is a diagram illustrating the principle of the present invention. As shown in this figure, the level conversion circuit 2 of the present invention has an output terminal commonly connected to the first signal line 8, inputs a power supply voltage Vi, an input signal IN, and a first control signal Ai. The power supply voltage V is set in a high impedance state based on the control signal Ai or in accordance with the level of the input signal IN.
n (n ≧ 2) tristate buffers 4-i (i = 1 to n) that output a signal based on i (for example, if the input signal is at a high level, Vi), and a second control signal Cj
(J = 1 to m) is input, and depending on the level value of the second control signal Cj, the (n-1) or n tristate buffers 4-i are output from the plurality of tristate buffers 4-i.
and a control circuit 6 for outputting a first control signal so that the output of i becomes a high impedance state.

Since the present invention is constructed as described above, the control circuit 6 is composed of, for example, a combinational circuit, and a plurality of tristate buffers are provided in accordance with the level of the second control signal Cj (j = 1 to m). The first control signal Ai (i = 1 to 1) so that the outputs of (n-1) or n tristate buffers 4-i in 4-i are in a high impedance state.
n) and outputs it to the tri-state buffer 4-i.

The tri-state buffer 4-i is set to a high impedance state according to the level of the first control signal Ai.
A signal based on the power supply voltage Vi is output to the first signal line 8 according to the level of the input signal IN.

The first signal line 8 is in a high impedance state if all the tri-state buffers 4-i are high impedance, or a high impedance state if the (n-1) tri-state buffers 4-i are high impedance. And outputs an output signal based on the power supply voltage connected to the selected one tristate buffer.
In the latter case, the level of the input signal IN is converted to a signal based on the selected power supply voltage.

An electronic device is connected to a first PKG on which the level conversion circuit 2 is mounted and a control signal Cj from a PKG on the receiving side.
(J = 1 to m) may be provided. This makes it possible to output an output signal from the first PKG with the operating voltage of the second PKG on the receiving side.

The first PKG includes a first resistor having one terminal connected to a second signal line for inputting a second control signal from the second PKG and the other terminal connected to a second power supply voltage. A configuration may be provided.

Thus, if the second PKG is not mounted, the level of the second control signal becomes equal to the second power supply voltage, and all the outputs of the tristate buffers 4-i (i = 1 to n) are set to high impedance. It is possible to do.

The third PKG preceding the first PKG is configured to output a third control signal indicating mounting / non-mounting information. If the third control signal indicates that the third PKG is not mounted, If the tristate buffer 4-i (i
= 1 to n) may be controlled so as to make all outputs have high impedance.

The first PKG has one terminal connected to the third PKG.
KG connected to a fourth signal line for inputting a third control signal, and the other terminal connected to a third power supply voltage.
A configuration including a resistor may be employed.

Thus, when the third PKG is not mounted, the level of the third control signal becomes equal to the third power supply voltage, and all the outputs of the tri-state buffers 4-i (i = 1 to n) are set to high impedance. It becomes possible to.

[0018] Further, a fourth PKG having a conversion circuit for generating a control signal Cj (j = 1 to m) from this ID is constructed by outputting an identification number (hereinafter, referred to as ID) from the receiving PKG. It may be mounted on a device. Thereby, it becomes possible to centrally manage all the operating voltages of the receiving PKG by the fourth PKG.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 2 is a configuration diagram of a level conversion circuit according to a first embodiment of the present invention.

As shown in FIG.
Represents n (n ≧ 2) tri-state buffers 12-i
(I = 1 to n) and a combinational circuit 14. The tristate buffer 12-i (i = 1 to n) enters a high impedance state when the control signal Ai input to the control terminal c is at a low level, and is input to the input terminal i when the control signal Ai is at a high level. When the input signal IN is at a high level, the power supply voltage Vi input to the terminal v is output, and when the input signal IN is at a low level (for example, ground), a low level (ground) is output.

Each of the tri-state buffers 12-i receives a power supply voltage Vi at a terminal v, a control signal Ai from the combinational circuit 14 at a terminal c, and an input signal IN at a terminal i.
A ground is connected to a terminal (not shown).

The output terminal o of the tristate buffer 12-i is connected to the output signal line 16, and the output signal OUT is output from the output signal line 16. Power supply voltage Vi
(I = 1 to n) are different voltages, for example, 5 V, 3.3 V, etc., and are generated from -48 V by on-board power as a power supply circuit.

The combinational circuit 14 receives a digital control signal Cj (j = 1 to m) and, based on the combination of the values of the control signal Cj, sets all the control signals Ai from the terminal Oi to a low level, that is, tristates. All the buffers 12-i are in a high impedance state, or the control signal Aio is at a high level, and the control signals Ak (k ≠ i0) excluding the control signal Ai0
At the low level, that is, the tristate buffer 12-
This is a combinational circuit that sets the tri-state buffers 12-k to high impedance except for i, where 2 ^m ≧ n.

The operating voltage of the combinational circuit 14 is not particularly limited, but is, for example, a low voltage from the viewpoint of low power consumption. The input signal IN is a P signal on which a level conversion circuit is mounted.
It is a digital signal output from KG or the like, and the high-level voltage is the operating voltage of the PKG.

The control signal Ai is output from the terminal oi of the combinational circuit 14 to the terminal v of the tristate buffer 12-i. FIG. 3 shows the combination circuit 14 shown in FIG.
FIG. 3 is a circuit diagram showing an example of the embodiment.

This combinational circuit is an example where m = 2 and n = 3, and has two inverters 20 and 22 and three AND gates 24, 26 and 28. The control signal C1 is input to the input terminal of the inverter 20.
The control signal C2 is input to the input terminal of the inverter 22. The control signal C1 is input to one input terminal of the AND gate 24, and the output signal of the inverter 22 is input to the other input terminal.

One input terminal of the AND gate 26 has:
The output signal of the inverter 20 is input, and the control signal C2 of the inverter 22 is input to the other input terminal. The control signal C1 is input to one input terminal of the AND gate 28, and the inverter 22 is input to the other input terminal.
Is input.

FIG. 4 is a diagram showing the truth values of the combinational circuit of FIG. As shown in this figure, when C1 = low level (hereinafter also referred to as 0) and C2 = 0, o1 = 0 and o2 =
0, o3 = 0, C1 = high level (hereinafter also referred to as 1), when C2 = 0, o1 = 1, o2 = 0, o3 = 0,
When C1 = 0 and C2 = 1, o1 = 0, o2 = 1, o3 =
0, C1 = 1, C2 = 0, o1 = 1, o2 = 0, o
3 = 0.

Hereinafter, the operation of the level conversion circuit according to the first embodiment will be described with reference to these drawings. A control signal Cj (j = 1 to m) instructing an output voltage is externally input to the combination circuit 14 in the level conversion circuit 10. For example, when the combination circuit 14 has the configuration shown in FIG. 3, when the receiving side operates at the voltage V1, the control signals C1 = 1 and C2 = 0 are applied to the combination circuit 14 in order to convert the high level of the input signal IN to the voltage V1. Input terminal.

The combination circuit 14 outputs 0 or oi0 from all output terminals oi according to the combination of the values of the control signal Cj.
From the terminal ok (k ≠ i0) excluding the terminal oi0.

For example, if the combinational circuit 14 has the configuration shown in FIG. 3 and the control signals C1 = 1 and C2 = 0, the output of the inverter 20 is 0, the output of the inverter 22 is 1 and the output of the AND gate 24 is 1 , AND gate 26 outputs 0, A
The output of the ND gate 28 becomes 0, and as shown in the truth values of FIG. 4, o1 = 1, o2 = 0, and o3 = 0.

The control signal Ai from the terminal oi of the combination circuit 14 is input to the terminal c of the tristate buffer 12-i. On the other hand, the input signal IN is input to the terminal i of the tristate buffer 12-i.

Terminal o of tristate buffer 12-i
Is in a high-impedance state when disconnected from the power supply voltage Vi and the ground when the control signal Ai = 0,
If the control signal Ai = 1, the voltage of the terminal o is equal to the input signal I
When N is at a high level, it becomes equal to the power supply voltage vi and when it is at a low level, it becomes equal to the ground voltage.

When the control signals Ai are all 0, all the tristate buffers 12-i are in a high impedance state, and the output signal OUT is in a high impedance state. When only the control signal Aio is 1, the output signal OU
T is the power supply voltage V when the input signal IN is at a high level.
If i0 is low level, it is equal to the ground voltage.

For example, in the case where the combinational circuit 14 has the configuration shown in FIG. 3, if the control signals A1 = 1 and A0 = 0, the output signal OUT becomes the power supply voltage V1 when the voltage of the input signal IN is at a high level. , At the low level, it becomes equal to the ground voltage, and the voltage of the input signal IN is converted to the power supply voltage V1.

According to the first embodiment described above, the power supply voltage Vi is applied to each of the tristate buffers 12-i.
(I = 1 to n) and a control signal Cj (j = 1 to m)
Is selected, any one of the power supply voltages Vio is selected. Therefore, an arbitrary power supply voltage Vio is selected from the power supply voltages Vi.
Can be selected.

Therefore, for example, if the receiving side operates at low voltage, it can output to the receiving side at the low voltage,
No interface circuit is required on the receiving side, and low power consumption can be maintained.

Further, even when the transmitting side transmits the same function to the receiving side of a different voltage, the voltage can be converted to an arbitrary voltage by designating the control signal Cj. Therefore, the transmitting side develops for each voltage of the receiving side. This eliminates the need and reduces development costs.

Second Embodiment FIG. 5 is a block diagram of an electronic device according to a second embodiment of the present invention. The electronic device shown in FIG. 1 includes a transmission PKG 30, a back wire board (hereinafter, referred to as BWB) 40, and a reception PKG.
The communication device includes a KG 50, for example, a communication device.

The transmission PKG 30 is a transmission-side PKG that transmits the output signal OUT to the reception PKG 50, and has the level conversion circuit 10 configured in the same manner as in FIG. The level conversion circuit 10 has a tri-state buffer 12-i and a combination circuit 14.

The BWB 40 has a transmission PKG 30 and a reception PK
P on which a wiring pattern is formed to connect to G50
KG, and the transmission PKG 30 and the reception PKG 50 are:
Each is connected by a connector.

The receiving PKG 50 is a PKG that receives an output signal from the transmitting PKG 30 and processes the signal.
2 and send PKG3 to specify its own operating voltage
0 to the control signal Cj (j = 1 to m) via the BWB 40.
Is output.

The control signal Cj is, for example, the reception PKG
The signal is output to the BWB 40 through a wiring pattern connected to either the power supply voltage or the ground in 50 and an output pin.

The operation of the electronic device according to the second embodiment shown in FIG. 5 will be described below. In the receiving PKG 50, although not shown, a wiring pattern is formed, and in order to specify an operating voltage,
It outputs a control signal Cj (j = 1 to m). For example, if the operating voltage of the reception PKG 50 is V1 and the combinational circuit 14 has the same configuration as that of FIG. 3, the reception PKG 50 transmits the control signals C1 = 1 and C0 = 0 through the BWB 40 and transmits the transmission PKG.
30 to the combinational circuit 14.

The combination circuit 14 controls the control signal Cj (j = 1
To m), the control signal Ai is output from the terminal oi to the terminal v of the tri-state buffer 12-i. If the control signal Ai = 0, the tristate buffer 12-i outputs
If high impedance state, Ai = 1, input signal I
A voltage equal to the power supply voltage Vi or the ground voltage is output to the output signal line 16 according to the level of N. Thus, for example, if the control signals C1 = 1 and C0 = 0, the voltage of the output signal OUT becomes V1.

Output signal O output from output signal line 16
The UT receives the received PK via the connector and the BWB 40.
The data is input to the buffer 52 of G50. The buffer 52
The level of the input signal is determined by the power supply voltage, which is the operating voltage supplied from the terminal v, and output from the terminal o.

The level conversion circuit 10 causes the buffer 52
Although the high level of the input signal is converted to be equal to the operating voltage of the receiving PKG 50, the level of the input signal becomes unstable due to noise or the like. Not output to electronic circuit.

According to the second embodiment described above, the control signal Cj is set from the receiving PKG 50 so as to transmit at its own operating voltage, and the level conversion circuit 1 of the transmitting PKG 30 is set.
Since the voltage is converted to the voltage by 0, the receiving PKG 50 does not require an interface.

Third Embodiment FIG. 6 is a configuration diagram of an electronic device according to a third embodiment of the present invention. The electronic device shown in this figure comprises transmitting PKG 60, and B
A WB 40 is provided, for example, a communication device.

The transmission PKG 60 is a PKG for transmitting the output signal OUT to the reception PKG. The transmission PKG 60 includes a tri-state buffer 12-i (i = 1 to n), a combinational circuit 14, and a level conversion circuit 62 including resistors 64-j (j = 1 to m).

The tri-state buffer 12-i (i = 1)
To n) and the combinational circuit 14 have the same configuration as that in FIG. The resistors 64-j (j = 1 to m) are pull-down resistors, one terminal is connected to a signal line for inputting a control signal Cj, and the other terminal is connected to ground (0 V). The resistance value is, for example, several KΩ in order to reduce power consumption.

The BWB 40 is the same as that in FIG. The BWB 40 has connector pins for connecting to the transmission PKG 60 and the reception PKG, but in the present embodiment, the reception PKG is not mounted.

The operation of the electronic device according to the third embodiment shown in FIG. 6 will be described below. (A) When receiving PKG is not mounted If receiving PKG is not mounted, control signal C is received from receiving PKG.
j (j = 1 to m) is not output, and the signal line for transmitting the control signal Cj in the BWB 40 to the transmission PKG 60 is in a high impedance state.

Transmission PKG6 receiving this control signal Cj
The 0 pin is pulled down to the ground voltage by the resistor 64-j, and the control signals Cj (j = 1 to m) are all 0.
Becomes Since the control signals Cj are all 0, the combinational circuit 14 outputs the control signal Ai of 0 from all the terminals oi to the terminal c of the tri-state buffer 12-i.

Since the control signal Ai input from the terminal c is 0, the trust state buffer 12-i enters a high impedance state, and the output signal line 16 enters a high impedance state.

(B) When the receiving PKG is mounted When the receiving PKG is mounted, Cj = 0 or 1 is set to the receiving PK.
G, the control signal Cj of the transmitting PKG 60
Is equal to the level from the reception PKG, and operates in the same manner as the second embodiment.

According to the third embodiment described above, the second
In addition to the same effects as in the embodiment, if the receiving PKG is not mounted, the output signal line 16 is set to a high impedance state.
Is unstable and the operation of the combinational circuit 14 becomes unstable, so that noise generated in the output signal line 16 can be suppressed.

Fourth Embodiment FIG. 7 is a block diagram of an electronic device according to a fourth embodiment of the present invention. The electronic device shown in this figure includes a transmission PKG 70, a BWB
40, a receiving PKG 50, and a BWB 80, for example, a communication device.

The transmission PKG 70 is a PKG that transmits the output signal OUT to the reception PKG 50. Send PKG70
Is a tristate buffer 12-i (i = 1 to n),
A level conversion circuit 72 including a combination circuit 74 and a resistor 76 is provided.

The tri-state buffer 12-i (i = 1)
To n) and the combinational circuit 14 have the same configuration as that in FIG. The resistor 76 is a pull-down resistor, and one terminal is connected to the control signal I via the BWB 80 by the preceding PKG.
The other terminal is connected to a signal line for inputting NS, and the other terminal is connected to ground (0 V). The resistance value is, for example, several KΩ in order to reduce power consumption.

The BWB 40 and the receiving PKG 50 are the same as those in FIG. The BWB 80 is a PKG on which a wiring pattern is formed to connect the upstream PKG and the transmission PKG 80, and the upstream PKG and the transmission PKG 60 are connected by a connector. PKG is not implemented yet.

When the preceding PKG is mounted, the BWB8
The control signal INS is output at a high level to the transmission PKG 70 via the “0”. FIG. 8 is a circuit diagram showing an example of the combinational circuit in FIG.

This combination circuit is an example where m = 2 and n = 3, and has two inverters 90 and 92 and three three-input AND gates 94, 96 and 98. The control signal C <b> 1 is input to the input terminal of the inverter 90. The control signal C2 is input to the input terminal of the inverter 92. The control signal C1 is input to one input terminal of the AND gate 94, the output signal of the inverter 92 is input to the other input terminal, and the control signal INS is input to the other input terminal. .

One input terminal of the AND gate 96 has
The output signal of the inverter 90 is input, the control signal C2 is input to the other input terminal, and the control signal INS is input to the other input terminal.

One input terminal of the AND gate 98 has
The control signal C1 is input, the control signal C2 is input to the other input terminal, and the control signal INS is input to the other input terminal.

FIG. 9 is a diagram showing truth values of the combinational circuit of FIG. As shown in this figure, when INS = 0, o1
= 0, o2 = 0, o3 = 0, INS = 1, C1 = 0, C
When 2 = 0, o1 = 0, o2 = 0, o3 = 0, INS =
When 1, C1 = 1 and C2 = 0, o1 = 1, o2 = 0, o
When 3 = 0, INS = 1, C1 = 0, C2 = 1, o1 =
0, o2 = 1, o3 = 0, INS = 1, C1 = 1, C2
When = 0, o1 = 1, o2 = 0, and o3 = 0.

The operation of the electronic device according to the fourth embodiment shown in FIG. 7 will be described below. (A) When the preceding stage PKG is not mounted If the preceding stage PKG is not mounted, the signal line for transmitting the control signal INS output via the BWB 80 to the transmitting PKG 70 is in a high impedance state. The pin of the transmission PKG 70 that receives the control signal INS is connected to the resistor 7
6, the control signal INS is pulled down to the ground voltage, and the control signal INS becomes 0.

Since the control signal INS is 0, the combination circuit 74 outputs Ai = 0 from all the terminals oi to the terminal c of the tri-state buffer 12-i. The tri-state buffer 12-i receives the control signal Ai input from the terminal c.
= 0, the output signal line 16 is in a high impedance state, and the output signal line 16 is in a high impedance state.

(B) When the preceding stage PKG is mounted When the preceding stage PKG is mounted, the control signal INS = 1, and the combination circuit 74 operates in the same manner as the combination circuit 14 in FIG. The signal Ai is output to the terminal v of the tri-state buffer 12-i.

The tristate buffer 12-i outputs a high impedance state, a power supply voltage Vi, or a ground voltage to the output signal line 16 according to a control signal Ai input to the terminal v.

The output signal OUT from the output signal line 16 is
The signal is input to the buffer 52 of the reception PKG 50 via the BWB 40, the level is determined, and the processing is performed. According to the fourth embodiment described above, the same effects as those of the second embodiment can be obtained. In addition, if the preceding stage PKG of the transmission PKG 70 is not mounted, the output signal line 16 is set to the high impedance state. Level becomes unstable,
Noise generated in the output signal line 16 can be suppressed.

Fifth Embodiment FIG. 10 is a block diagram of an electronic device according to a fifth embodiment of the present invention. The electronic device shown in FIG.
B90, reception PKG100, and supervisory control PKG110
, For example, a communication device.

The transmission PKG 30 is the same as that in FIG. The BWB 90 includes a transmitting PKG 30 and a receiving PKG 10
0, and for transmitting and receiving signals between the supervisory control PKG 110 and are connected by a connector.

The receiving PKG 100 receives and processes the output signal OUT from the transmitting PKG 30 in the buffer 52, and receives ID1 to ID1 assigned to its own PKG.
The IDk is output to the conversion circuit 112 of the monitoring control PKG 110 via the BWB 90.

The monitoring control PKG 110 monitors the entire apparatus such as an alarm of an electronic apparatus such as a communication apparatus.
It has a conversion circuit 112. This monitoring control PKG110
Is an ID indicating a PKG number for each PKG 30, 110, etc.
The PKG is centrally managed based on the ID.

The conversion circuit 112 calculates k of the reception PKG 100
Combination circuit 1 for inputting bit ID signals ID1 to IDk and designating the operating voltage of reception PKG 100
4 is a circuit that outputs control signals C1 to Cm to be input to the PKG 4 and is provided for each receiving PKG 100.

FIG. 11 is a circuit diagram showing an example of the conversion circuit 112 in FIG. This conversion circuit 112 calculates k =
4, m = 3, ID of receiving PKG 100 is ID1 = 0, I
D2 = 0, ID3 = 1, ID4 = 0, receiving PKG100
Is an example in which the operating voltages of C1 = 1, C2 = 0, and C3 = 0, and two inverters 90 and 92 and three 3
It has input AND gates 94, 96, 98.

The control signal C 1 is input to the input terminal of the inverter 90. The control signal C2 is input to the input terminal of the inverter 92. AND gate 94
The control signal C1 is input to one input terminal, the output signal of the inverter 92 is input to the other input terminal, and the control signal INS is input to the other input terminal.

One input terminal of the AND gate 96 has:
The output signal of the inverter 90 is input, the control signal C2 is input to the other input terminal, and the control signal INS is input to the other input terminal.

One input terminal of the AND gate 98 has:
The control signal C1 is input, the control signal C2 is input to the other input terminal, and the control signal INS is input to the other input terminal.

FIG. 12 is a diagram showing truth values of the conversion circuit of FIG. As shown in this figure, ID1 = 0, ID2
= 0, ID3 = 1, ID4 = 0, C1 = 1, C2
= 0, C3 = 0.

The operation of the electronic device according to the fifth embodiment shown in FIG. 10 will be described below. The receiving PKG 100 transmits ID1 to IDk assigned to its own PKG via the BWB 90,
It is input to the conversion circuit 112 of the monitoring control PKG110. The conversion circuit 112 receives the PKG 100 from ID1 to IDk.
It generates control signals C1 to Cm for designating the middle operation voltage, and outputs them to the combinational circuit 14 in the transmission PKG 30 via the BWB 90.

For example, if the ID of the receiving PKG 100 is the ID
1 = 0, ID2 = 0, ID3 = 1, ID4 = 0,
If the operating voltage of the receiving PKG 100 is V1, for example, the conversion circuit 112 shown in FIG. 10 converts ID1 to ID4 into C1 = 1, C2 = 0, and C3 = 0.

Combination circuit 14 receives control signals C1 to Cm, operates in the same manner as in FIG. 2, and outputs control signal Ai from terminal oi. Tri-state buffer 12-i
Outputs a high impedance state or a voltage Vi from the control signal Ai input to the terminal v to the output signal line 16.
Thereby, the output signal O output from the output signal line 16 is output.
The UT is the operating voltage of the receiving PKG 100.

The receiving PKG 100 inputs the output signal OUT to the buffer 52, determines the level, and performs processing. According to the fifth embodiment described above, in addition to the same effects as the second embodiment, the control circuit Cj (j = 1 to m) is generated by the conversion circuit 112 in the monitoring control PKG 110 from the ID of the reception PKG 100. Monitoring, PKG
At 110, the operating voltage can be centrally managed.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, the following are provided. (A) The control signal Ai to be output to the terminal v of the tri-state buffer 12-i is generated by the combination circuits 14 and 74. However, the operating voltage of the reception PKGs 50 and 100 is input to a control circuit corresponding to the combination circuit. Then, the control circuit may perform A / D conversion on the control signal Ai.

(B) The conversion circuit 112 in FIG.
Although it is configured to input only ID1 to IDk, the reception PK
A control signal INS indicating whether the G100 or the preceding PKG of the transmission PKG 30 is not mounted may be input, and if not mounted, the output signal line 16 may be in a high impedance state.

[0088]

As described above, according to the first to sixth aspects of the present invention, the tri-state buffer is controlled by the control signal to set the level of the output signal to a desired value. The output can be easily adjusted to the voltage on the signal receiving side. Therefore, there is no need to provide a voltage interface on the receiving side, and this can be maintained when the receiving side consumes low power.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a level conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a combination circuit in FIG. 2;

FIG. 4 is a diagram showing truth values of the combinational circuit of FIG. 3;

FIG. 5 is a configuration diagram of an electronic device according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of an electronic device according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of an electronic device according to a fourth embodiment of the present invention.

8 is a circuit diagram of the combinational circuit in FIG.

FIG. 9 is a diagram illustrating truth values of the combinational circuit of FIG. 8;

FIG. 10 is a configuration diagram of an electronic device according to a fifth embodiment of the present invention.

FIG. 11 is a circuit diagram of a conversion circuit in FIG. 10;

FIG. 12 is a diagram illustrating truth values of the conversion circuit of FIG. 11;

[Explanation of symbols]

 2-level conversion circuit 4-i tristate buffer 6 control circuit 8 output signal line Cj control signal Ai control signal IN input signal

Claims (6)

[Claims] An output terminal is commonly connected to a first signal line,
A power supply voltage, an input signal, and a first control signal are input, and a signal based on the power supply voltage is output based on the first control signal in a high impedance state or according to the level of the input signal. 2) tristate buffers and a second control signal, and according to the level value of the second control signal, (n-1) or n tristate buffers in the tristate buffer And a control circuit that outputs the first control signal so that an output is in a high impedance state. 2. An output terminal is commonly connected to a first signal line,
A power supply voltage, an input signal, and a first control signal are input, and a signal based on the power supply voltage is output based on the first control signal in a high impedance state or according to the level of the input signal. 2) tristate buffers and a second control signal are input, and (n-
1) a first package having a control circuit that outputs the first control signal so that the outputs of the n or n tri-state buffers are in a high impedance state; and A second package for receiving an output signal and outputting the second control signal indicating a level of the output signal. 3. The first package has one terminal connected to a second signal line for inputting the second control signal from the second package, and the other terminal connected to a second power supply voltage. The electronic device according to claim 2, further comprising a resistor. 4. A first package for outputting a first control signal indicating mounting / non-mounting information of its own package, an output terminal commonly connected to a first signal line, a power supply voltage, an input signal, and a second control signal. Receiving a signal and outputting a signal based on the power supply voltage according to the level of the input signal in a high impedance state based on the second control signal.
(N ≧ 2) tristate buffers, a third control signal and a fourth control signal based on the first control signal are input, and the fourth control signal indicates that the first package is not mounted. And outputting the second control signal such that all outputs of the n tri-state buffers are in a high impedance state. When the fourth control signal indicates that the first package is mounted, the second control signal is output. A control circuit for outputting the second control signal such that outputs of the (n-1) or n tristate buffers in the tristate buffer enter a high impedance state in accordance with a level value of the three control signals; An electronic device, comprising: a second package having the following. 5. The second package has one terminal connected to a fourth signal line for inputting the first control signal from the first package, and the other terminal connected to a second power supply voltage. The electronic device according to claim 4, further comprising a resistor. 6. An output terminal commonly connected to the first signal line,
A power supply voltage, an input signal, and a first control signal are input, and a signal based on the power supply voltage is output based on the first control signal in a high impedance state or according to the level of the input signal. 2) tristate buffers and a second control signal are input, and (n-
1) a first package having a control circuit that outputs the first control signal so that the outputs of the n or n tri-state buffers are in a high impedance state; and A second package that receives an output signal and outputs an identification number for identifying its own package; and inputs the identification number and outputs the second control signal that indicates a power supply voltage for the second package. And a third package having a conversion circuit.