JPH0746119A - Clock signal and synchronous reset signal generating circuit - Google Patents

Abstract

PURPOSE:To provide the clock signal and synchronous reset signal generating circuit which eliminates the probability of the block in an LSI to which a clock signal and a reset signal are given takes a malfunction at the time of reset release. CONSTITUTION:A synchronous counter 10 divides the frequency of a system clock signal SCLK once to output a clock signal CLK having the two-fold period. A reset signal CREST for synchronous counter outputted from a reset signal generating circuit 11 only for a while after the change of a reset signal REST is changed from the low level to the high level. The reset signal generating circuit 11 delays the reset signal REST so that it is changed at the time of the stop of the clock signal CLK, and this delay signal is outputted as an internal reset signal RSET'. Since the other blocks in the LSI use the clock signal CLK and the internal reset signal REST' as the clock signal and the reset signal respectively, they are free from the malfunction due to a wrong clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal / synchronous reset signal generation circuit used in a sequential logic circuit or the like.

[0002]

2. Description of the Related Art As a clock signal generation circuit for dividing a system clock to arbitrarily obtain a synchronous clock signal, there is a conventional one using a counter 1 as shown in FIG. The counter 1 used here has a suitable b inside it.
It has a register of it length and clears the register when the "H" reset signal REST input from the outside is input as shown in FIG. 12 (b), and when "L" is input to the RST terminal, CLK It is a counter that increments the register value when the value of the system clock signal SCLK shown in FIG. 12 (a) input to the terminal changes from "L" to "H", and outputs the bit value at the appropriate position of the internal register to OUT.
Output from the terminal as shown in FIG.

With this, the signal obtained by dividing the system clock signal SCLK by the desired number of times is obtained from the counter 1, but when the reset signal REST is "H", the output of the counter 1 does not change because the counter 1 does not move, and therefore, The output of the counter 1 cannot be supplied as a clock signal to a block whose clock signal needs to be changed even at the time of reset. Therefore, using the selector 2, the reset signal REST
Is "H", the system clock signal SCLK is supplied to the other blocks as the clock signal CLK, and the output of the selector 2 shown in FIG. FIG. 12 shows a time chart in the case of dividing the system clock signal SCLK once to generate the clock signal CLK output.

[0004]

By the way, in the above-mentioned conventional example, there is a problem that malfunction may occur depending on the timing of inputting the reset signal REST. FIG. 13 shows a time chart when the system clock signal SCLK is divided twice and the clock signal CLK is generated through the selector 2.
Since the reset signal REST is “H” in the areas (a), (b) and (c) of FIG. 13D as shown in FIG. 13B, the selector 2 is shown in FIG. In the part where the system clock signal SCLK is selected and output as the clock signal CLK, the reset signal REST is "
Since it is L ″, the selector 2 selects the output of the counter 1 and outputs it as the clock signal CLK.
Here, in the part (a) where the reset signal REST changes from "L" to "H" and the part (c) where "H" changes to "L", the reset is performed when the system clock signal SCLK is "H". The signal REST changes, and as a result, the clock signal CLK output from the selector 2 appears as a signal having a time "H" shorter than the system clock signal SCLK. Next, consider the case where the circuit of the conventional example is used as a clock signal generation block of an LSI forming a certain logic procedure circuit.

FIG. 14 shows how the clock signal generation circuit shown in FIG. 11 supplies a clock signal to another block in the same LSI. Clock generation circuit C
G is supplied with the system clock signal SCLK and the reset signal REST and outputs the clock signal CLK. This clock signal CLK is input to the CLK terminal of the block B inside the LSI, but the clock signal CLK of the clock generation circuit CG
Since there is a delay time between the block B and the block B, the clock signal CLK is transmitted to the CL of the block B via the delay element D1.
It shall be input to the K terminal. Similarly, the reset signal REST is also input to the RST terminal of the block B via the delay element D2.

FIG. 15 shows a time chart when the delay time of the delay element D1 is larger than the delay time of the delay element D2. In this example, the delay time of the delay element D1 is shown in FIG.
One cycle of the system clock signal SCLK shown in (a) is used, and the delay time of the delay element D2 is set to the system clock signal SC.
It is the half cycle of LK. In such a case, block B
Comparing the clock signal CLK 'shown in FIG. 15 (e) and the reset signal REST' shown in FIG.
The reset signal REST 'of the delay element D2 is input earlier, and an incorrect clock signal (e) is input after the reset signal REST' becomes "L".
The original clock signal used by the block B after the reset is released is the portion (f), and the input of the clock signal (e) causes a malfunction. Further, the period during which the clock signal (e) is "H" depends on the timing at which the reset signal REST changes and cannot be predicted in advance. Therefore, it is not possible to know in advance whether or not a malfunction will occur in the above example. Figure 15
(B) and (c) respectively show the reset signal REST input to the clock generation circuit CG and the clock signal CLK output.

The present invention has been made in view of the above points, and an object of the present invention is to eliminate the possibility that a block in an LSI that provides a clock signal and a reset signal malfunctions when reset is released. A synchronous reset signal generation circuit is provided.

[0008]

In order to achieve the above-mentioned object, a clock signal / synchronous reset signal generation circuit according to a first aspect of the present invention divides a system clock signal input from the outside of an LSI to an arbitrary cycle. And a synchronous counter for generating an output of the clock signal, an internal reset signal is generated by appropriately delaying a reset signal input from the outside of the LSI, and the generation of the clock signal is stopped when the output of the reset signal changes. And a reset signal generation circuit for generating a reset signal for the synchronous counter for the purpose.

The clock signal / synchronous reset signal generating circuit according to a second aspect is the clock signal / synchronous reset signal generating circuit according to the first aspect, wherein
It is characterized by comprising an initialization circuit for adding a signal which is in a reset state for a predetermined period after a predetermined time after the reset signal is released and outputting the signal to the reset signal generation circuit.

[0010]

According to the structure of the present invention, the LS is irrespective of the input timing of the reset signal input from the outside of the LSI.
An internal reset signal that changes when the clock signal is stopped can be given to the other blocks in I, and the possibility that the block may malfunction when reset is released can be eliminated.

[0011]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, ten synchronous counters output a clock signal CLK obtained by dividing a system clock signal SCLK input from the outside of the LSI into a desired cycle. . On the other hand, 11 reset signal generation circuits are reset signals REST from outside the LSI.
Is input to the reset signal input terminal RSTIN, and the reset signal CREST for the synchronous counter and the internal reset signal REST 'are output.

The clock signal CLK and the internal reset signal REST 'are given to other blocks in the LSI.

FIG. 2 shows a time chart of the above embodiment. In the illustrated example, the system clock signal SCLK shown in FIG. 2A is divided by the synchronous counter 10 once, and the clock signal CLK having a doubled cycle is shown. Is output as shown in FIG. As shown in FIG. 2C, the synchronous counter reset signal CREST changes from “L” to “H” only for a while after the reset signal REST shown in FIG. 2B changes. As a result, when the clock signal CLK is stopped,
The reset signal REST is delayed appropriately so as to change, and is output as the internal reset signal REST ′ shown in FIG. Other blocks in the LSI are clock signals
Since CLK and the internal reset signal REST 'are used as the clock signal and the reset signal, the malfunction due to the incorrect clock signal as in the conventional example does not occur.

FIG. 3 shows a specific example of the above embodiment,
The synchronous counter 10 is composed of a counter having a register of 1 bit length inside, and the synchronous counter 10 sets the value of the register to 0 when the reset signal CREST for the synchronous counter of "H" is input to the RST terminal. When the rising edge of the system clock signal SCLK shown in FIG. 4A arrives at the CLK terminal, the value of the register is incremented. When a rising edge is further input while the register value is "1", the register value becomes "0". O
The value of this register is output to the UT terminal, which causes the synchronous counter 10 to receive the input system clock signal SC.
The clock signal CL shown in FIG. 4 (e) having a cycle twice that of LK.
Works to convert to K.

The reset signal generating circuit 11 is a counter C.
1 and C2, comparators CMP1 and CMP2, flip-flops F1 to F4, an OR gate OR, and a not gate NT. It is a counter that increments the value of the register when the value of the register is 0, the RST terminal is "L" and the value of the register is 4 or less, and outputs the value of the register of 3 bit width as it is. The comparators CMP1 and CMP2 output "H" when the input data is 1 or more and 4 or less, and output "L" otherwise. And these counters C
1 and C2 and the comparators CMP1 and CMP2, the reset signal RE shown in FIG.
As shown in FIG. 4 (c), "H" is input only from one cycle to five cycles after the system clock signal SCLK from the time ST changes from "L" to "H", and is input to the input terminal b. From the time when the reset signal REST changes from "H" to "L", only one cycle to five cycles after the system clock signal SCLK.
"H" is input as shown in (d). The result of the logical sum operation of both input signals is the reset signal for the synchronous counter
It becomes CREST. Further, the flip-flops F1 to F4 delay the reset signal REST by the time of four cycles of the system clock signal SCLK, and then the internal reset signal RES shown in FIG.
Output as T '. In the above specific example, the clock signal CLK having the required characteristics can be easily obtained by changing the setting of the synchronous counter 10, the setting of the counters C1 and C2 in the reset signal generating circuit 11, and the number of stages of the shift register for the internal reset signal. The internal reset signal REST 'can be obtained.

In the configuration shown in FIG. 3, the counter C1 of the reset signal generating circuit 11 is a counter that is reset when the RST terminal becomes "L" and increments when it becomes "H", and the counter C2 is the counter C2. RST terminal is "
It is a counter that is reset when it becomes H ”and is incremented when it becomes“ L. ”At power-on reset, the register values of the counters C1 and C2 are as shown in Fig. 5. In the figure, (a) shows An example of the reset signal REST at the time of power-on is shown, which is a signal that changes only from "H" to "L". (B) shows the register value of the counter C1 and (c) shows the register value of the counter C2. ing.
As shown in the figure, when the reset signal REST is "H", the counter C2 is reset and operates normally.
Since the counter C1 has not been reset, as shown in FIG. 5, the registration value becomes indefinite, and there is a possibility that a normal synchronization counter reset signal cannot be output. Therefore, if this circuit is applied to a circuit in which the reset signal REST applied from the outside changes only from "H" to "L" at the time of power-on reset, the counter C1 cannot be correctly initialized, which causes a malfunction. When the clock signal / synchronous reset signal generating circuit of the present invention is applied to such a circuit, for example, the configuration shown in the block diagram of FIG. 6 may be adopted.

In a different embodiment shown in FIG. 6, an initialization circuit 21 is added to the clock signal / synchronous reset signal generation circuit shown in FIG. The initialization circuit 21 is shown in FIG.
A reset signal REST as shown in (a) is input, and after a certain time after the reset signal REST changes from "H" to "L" as shown in FIG. This circuit supplies the reset signal generation circuit 11 with an initialization signal RTEST "to which a signal that changes to" L "after outputting" H "for a predetermined time is added. FIG. 7C shows the counter C1.
7D, the register value of the counter C2 is shown in FIG. In this way, reset signal REST is "L"
After resetting the counter C1 by setting the reset signal REST to "H" for a predetermined period, the counters C1 and C2 can be normally reset.

A specific circuit of the above-described embodiment will be described with reference to FIG. The clock signal / synchronous reset signal generation circuit shown in the figure has a 1-bit length register inside, a synchronous counter 10 that divides the system clock SCLK by 2 and outputs a clock signal CLK, and a reset signal generation circuit. 11 and an initialization circuit 21 connected to the preceding stage of the reset signal generation circuit 11. A function of supplying the system clock signal SCLK to the synchronous counter 10, the reset signal generation circuit 11 and the initialization circuit 21 and inputting the reset signal REST to the initialization circuit 21 to normally initialize the reset signal generation circuit 11. Initialization signal with
It is converted into REST '' and supplied to the reset signal generation circuit 11.

In the initialization circuit 21, C3 is a counter having a 4-bit length register, and the reset signal REST is "H".
In the case of, the data is reset, and when the reset signal REST is "L" and the data is 14 or less, the data is incremented, and the value held in the 4-bit length register is directly output as the data DATA. In CMP3, 4-bit length data DATA input from the counter C3 is 0.
A comparator that outputs "L" if 6 or less or 15 or more and "H" otherwise, in which S1 inputs the reset signal REST and the output of the comparator CMP3, and the reset signal REST Is "H", reset signal REST ("H")
Is output, and when the reset signal REST is "L", the comparator C
It is a selector that outputs the output of MP3. FIG. 9 shows a time chart of the initialization circuit 21 configured as described above. As shown in FIG. 9B, the reset signal REST is "
If it is H ”, the data DA output from the counter C3
TA (FIG. 9 (c)) is reset to 0, and as shown in FIG. 9 (d), the reset signal REST which is “H” is output as it is as the initialization signal REST ″. . Since the data DATA is 0 when the reset signal REST changes from "H" to "L", the comparator C which is "L"
The output of MP3 is output as the initialization signal REST ″. Since the RST terminal of the counter C3 is in the "L" state, the data DATA of the counter C3 is incremented and the comparator CMP3 is "L" while the data DATA is 1 to 6.
The comparator CMP3 outputs "H" while the data DATA is 7 to 14. Then the data DATA
Is not further incremented when it reaches 15, and the comparator CMP3 outputs "initialization signal REST".
The L "state is output.

FIG. 10 shows a time chart at the time of power-on reset of the clock signal / synchronous reset signal generation circuit shown in FIG. In the figure, (a) is a system clock signal SCLK, (b) is a reset signal REST given from the outside, (c) is an output of the comparator CMP1, (d) is an output of the comparator CMP2, and (e) is a clock signal. CLK, (f)
Is the internal reset signal REST ', (g) is the initialization signal REST''
Is. As shown in the figure, the counter C1 is reset for the first time in the part (g) where the initialization signal REST '' is "L", and in the part (h) in the period when the initialization signal REST "is" H ". The register is incremented and the normal comparator C
The output (c) of MP1 is obtained. Further, since the counter C2 is also reset again at the portion (h) of the initialization signal REST ″, the normal output (d) of the comparator CMP2 is obtained.
As a result, the clock signal CLK rises and falls during the rising and falling portions of (i) of the internal reset signal REST '.
Since it is L ″, the other blocks of the LSI are normally reset at the portion (i) of the internal reset signal REST ′.

As described above, by adding the initialization circuit 21 to the clock signal / synchronous reset signal generation circuit shown in FIG. 3, the reset signal input from the outside of the LSI changes from "H" to "L". Even if the circuit is just
It is possible to correctly initialize the clock signal / synchronous reset signal generation circuit and prevent malfunction. The initialization circuit is not limited to the circuit of the embodiment.

[0023]

According to the present invention, a synchronous counter for dividing a system clock signal input from the outside of the LSI to generate a clock signal output of an arbitrary cycle, and an appropriate delay for a reset signal input from the outside of the LSI. And a reset signal generating circuit for generating an internal reset signal and generating a reset signal for a synchronous counter for stopping the generation of the clock signal when the output of the internal reset signal changes. Irrespective of the timing of inputting the reset signal, an internal reset signal that changes when the clock signal is stopped can be given to other blocks in the LSI.
There is an effect that it is possible to eliminate the possibility that other blocks of the LSI may malfunction when reset is released.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the above operation.

FIG. 3 is a specific circuit diagram of the above.

FIG. 4 is a time chart for explaining the operation of the above specific circuit.

FIG. 5 is a time chart for explaining a malfunction of the specific circuit of the above.

FIG. 6 is a circuit block diagram showing a different embodiment of the present invention.

FIG. 7 is a time chart for explaining the operation of a different embodiment of the present invention.

FIG. 8 is a detailed circuit diagram of a different embodiment of the present invention.

FIG. 9 is a time chart of an initialization circuit according to another embodiment of the present invention.

FIG. 10 is a time chart for explaining the operation of another embodiment of the present invention.

FIG. 11 is a circuit block diagram of a conventional example.

FIG. 12 is a time chart for explaining the above operation.

FIG. 13 is a time chart for explaining a malfunction described above.

FIG. 14 is a block diagram when the same is incorporated in an LSI.

FIG. 15 is a time chart for explaining the above operation.

[Explanation of symbols]

 10 Synchronous counter 11 Reset signal generation circuit 21 Initialization circuit SCLK System clock signal CLK Clock signal REST Reset signal REST 'Internal reset signal REST' 'Initialization signal CREST Reset signal for synchronous counter

Claims (2)

[Claims] 1. A synchronous counter for dividing a system clock signal input from the outside of the LSI to generate a clock signal output of an arbitrary cycle, and an internal reset by appropriately delaying a reset signal input from the outside of the LSI. And a reset signal generation circuit for generating a reset signal for a synchronous counter for generating a signal and stopping the generation of the clock signal when the output of the internal reset signal changes. Reset signal generation circuit. 2. An initializing circuit for adding to the reset signal generating circuit a signal which is in a reset state for a predetermined period of time after the reset signal is released, and which is output to the reset signal generating circuit. The clock signal / synchronous reset signal generation circuit according to claim 1.