KR100903384B1 - Semiconductor memory device and operation method thereof - Google Patents

Abstract

The present invention provides a first output enable signal generating means for generating a first output enable signal by comparing a value counted from a DLL clock with a value counted from an external clock until a read command is input, and responding to cascading information. And a final output enable signal generating means for outputting any one of a plurality of output enable signals shifted from said first output enable signal and said first output enable signal as a final output enable signal. Provide a device.

Domain Crossing, Output Enable Signal, Cascading Latency

Description

Semiconductor memory device and its driving method {SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to an output enable signal generator of a semiconductor memory device.

In general, a synchronous semiconductor memory device such as DDR SDRAM (Double Data Rate Synchronous DRAM) receives data from an external clock CLK_EXT or outputs data externally. However, the semiconductor memory device generally processes data in response to an internal clock. From a data standpoint, the clock that is synchronized to the data changes, which is commonly referred to as "domain crossing."

Various circuits are provided in the semiconductor memory device to ensure such domain crossing, and among these circuits, an output enable signal generator is provided. The output enable signal generator is a circuit for ensuring that data transmitted in synchronization with the internal clock is output in synchronization with the external clock CLK_EXT after the cascading time.

1 is a block diagram illustrating a conventional output enable signal generator.

Referring to FIG. 1, the output enable signal generator includes a counter reset signal generator 10, an initialization unit 20, a DLL clock counting unit 30, a delay model unit 40, and an external clock counting unit. The part 50, the latching part 60, and the comparison part 70 are provided.

The counter reset signal generator 10 may generate a first reset signal RST_DLL in response to a reset signal RST corresponding to an external command (eg, / RAS, / CAS, / CS, / WE) and a DLL clock CLK_DLL. Outputs

The initialization unit 20 provides the DLL clock counting unit 30 with an initial counting value corresponding to the cascade latency CL in response to the first reset signal RST_DLL. Table 1 below shows the initial counting value corresponding to the cascade latency CL to the cascade latency CL3 and the signals S <0: 2> output from the initialization unit 20 accordingly.

CL Initial counting value S <2> S <1> S <0> 3 4 5 6 7 5 4 3 2 1 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1

FIG. 2 is a circuit diagram illustrating the initialization unit 20 of FIG. 1.

Referring to FIG. 2, the initialization unit 20 is enabled in response to the first reset signal RST_DLL and output signal S for initializing the DLL clock counting unit 30 according to the cascade latency CL. <0: 2>, R <0: 2>). The CAS latency CL is a signal output from a mode register set (not shown) and relates to the number of external clocks CLK_EXT until data is output after the read command RD (see FIG. 4). Have information

Meanwhile, referring back to FIG. 1, the DLL clock counting unit 30 counts from an initial counting value according to the DLL clock CLK_DLL to output a DLL clock counting value CNT_DLL <0: 2>. For example, if the initial counting value is set to 4 according to the cascade latency CL, the DLL clock counting unit 30 starts counting from 4 according to the DLL clock CLK_DLL.

The delay model unit 40 models a delay element until the DLL clock CLK_DLL outputs data, and reflects the delay time modeled in the first reset signal RST_DLL to reflect the second reset signal RST_CLK. )

The external clock counting unit 50 counts the external clock CLK_EXT in response to the second reset signal RST_CLK, and the latching unit 60 outputs the external clock counting unit 50 in response to the read command RD. The signal CNT_CLK <0: 2> is latched and output as the external clock counting value CNT_RD <0: 2>.

The comparator 70 compares the DLL clock counting value CNT_DLL <0: 2> and the external clock counting value CNT_RD <0: 2> and outputs an output enable signal OE when the two values are the same.

3 is a circuit diagram illustrating the comparison unit 70 of FIG. 1.

Referring to FIG. 3, the comparator 70 is configured to compare the 3-bit DLL clock counting value (CNT_DLL <0: 2>) and the 3-bit external clock counting value (CNT_RD <0: 2>). If the counting value CNT_DLL <0: 2> and the external clock counting value CNT_RD <0: 2> are the same, the output enable signal OE is activated. For reference, data is output in correspondence with the output enable signal OE and burst length information.

4 and 5 are timing diagrams for describing an operation timing of the output enable signal generator of FIG. 1. 4 illustrates a case in which the cascade latency CL is 4, which will be described with reference to FIGS. 1 and 4.

First, since the cascade latency CL is 4, the initial counting value of the initialization unit 20 is set to 4 according to Table 1. When the first reset signal RST_DLL becomes logic 'low', the DLL clock counting unit 30 counts the DLL clock counting value CNT_DLL <0: 2> counting from the initial counting value 4 in response to the DLL clock CLK_DLL. Output

On the other hand, after the delay time of the delay model unit 40 is reflected in the first reset signal RST_DLL, when the second reset signal RST_CLK becomes logic 'low', the external clock counting unit 50 is connected to the external clock CLK_EXT. Start counting in response.

At this time, when the read command RD is input, the latching unit 60 latches 2, which is the value CNT_CLK <0: 2> counting the external clock CLK_EXT, and the external clock counting value CNT_RD <0: 2>. Will output The comparator 70 compares the DLL clock counting value CNT_DLL <0: 2> with the external clock counting value CNT_RD <0: 2>, that is, the DLL clock counting value CNT_DLL <0: 2>. When 2) becomes 2, the output enable signal OE is output. The data D0, D1, D2, and D3 are output to the output terminal DQ using the generated output enable signal OE.

FIG. 5 is a case where the cascade latency CL is 5 and will be described with reference to FIGS. 1 and 5.

First, since the cascade latency CL is 5, the initial counting value of the initialization unit 20 is set to 3 according to Table 1. When the first reset signal RST_DLL becomes logic 'low', the DLL clock counting unit 30 outputs a DLL clock counting value CNT_DLL <0: 2> counting from the initial counting value of three.

On the other hand, after the delay time of the delay model unit 40 is reflected in the first reset signal RST_DLL, when the second reset signal RST_CLK becomes logic 'low', the external clock counting unit 50 starts counting.

Likewise, when the read command RD is input, the latching unit 60 latches 2, which is the value CNT_CLK <0: 2> counting the external clock CLK_EXT, and the external clock counting value CNT_RD <0: 2. >) The comparator 70 compares the DLL clock counting value CNT_DLL <0: 2> with the external clock counting value CNT_RD <0: 2>, that is, the DLL clock counting value CNT_DLL <0: 2>. When 2) becomes 2, the output enable signal OE is output. The data D0, D1, D2, and D3 are output to the output terminal DQ using the generated output enable signal OE.

Up to now, the configuration and operation of the general output enable signal generator have been described. Hereinafter, the vulnerabilities and problems of the output enable signal generator will be described.

First, the cascade latency CL is a signal output from the mode register set. Therefore, the initialization unit 20 has a constraint that the initial counting value must be set only after the mode register set is completed, and the DLL clock counting unit 30 is reset every time the cascade latency CL is changed. There is a hassle to change the initial counting value.

In addition, these days, the high frequency external clock CLK_EXT is being used in the trend of requiring fast operation of the circuit, and thus the cascade latency CL is also increasing. Therefore, the DLL clock counting unit 30 and the external clock counting unit 50 should expand the counting capability to match the cascade latency CL. In other words, when the DLL clock counting unit 30 and the external clock counting unit 50 are configured with, for example, a 3-bit counter, the cascade latency CL may be secured up to seven. Therefore, when the cascade latency CL is further increased, the counter's ability to configure the DLL clock counting unit 30 and the external clock counting unit 50 should also be extended to 3 bits or more. The increased counter configuration caused by this increased number of bits causes more current consumption during active or standby operations.

Subsequently, when the number of bits output from the DLL clock counting unit 30 and the external clock counting unit 50 increases as the cascade latency CL increases, the operation time of the comparator 70 increases, resulting in an output enable signal. There is an additional unwanted delay in generating the. This causes a problem in that the output enable signal cannot be generated at a desired time.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of generating a desired output enable signal without increasing an initial counting value and a number of output bits.

Another object of the present invention is to provide a semiconductor memory device using an optimal current consumption and a minimum delay time in domain crossing.

According to an aspect of the present invention for achieving the above object, a first output for generating a first output enable signal by comparing the value of counting the DLL clock and the value of counting the external clock until the read command is input; A final signal for outputting any one of the enable signal generating means and a plurality of output enable signals shifted from the first output enable signal and the first output enable signal in response to the cascade latency information as a final output enable signal; A semiconductor memory device having an output enable signal generating means is provided.

According to another aspect of the present invention for achieving the above object, a first counting step of outputting a first counting value by counting according to the DLL clock; A second counting step of counting an external clock until a read command is input and outputting a second counting value; Outputting a first output enable signal by comparing the first and second counting values; A shifting step of generating a plurality of output enable signals by shifting the first output enable signal in response to the DLL clock; And a final output enable signal output step of outputting any one of the first output enable signal and the plurality of output enable signals as a final output enable signal in response to the cascade latency information. This is provided.

According to the present invention, a first output enable signal is generated by using a counter having a predetermined initial counting value, and a plurality of output enable signals are generated by shifting the first output enable signal, and then corresponding to the cascade latency information. Any one of the output enable signals may be output as the final output enable signal. Thus, it is possible to improve the problem that occurs while the initial counting value changes depending on the cascade.

The present invention described above uses a constant initial counting value even when the cascading time is changed, thereby eliminating the need for an extended design of the counter, thereby obtaining an effect of generating a desired output enable signal without unnecessary current consumption and undesired delay time. Can be.

In addition, it is possible to obtain an effect that can guarantee the optimum current consumption and delay time in the domain crossing of the external clock and the internal clock.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

6 is a block diagram illustrating an output enable signal generator of a semiconductor memory device according to the present invention.

Referring to FIG. 6, the output enable signal generating apparatus outputs an external clock from a predetermined initial counting value to a DLL clock counting value CNT_DLL <0: 1> counting the DLL clock CLK_DLL and a read command RD. The first output enable signal generator 100 for generating the first output enable signal OE0 by comparing the external clock counting value CNT_RD <0: 1> counting the CLK_EXT, and the latency A plurality of output enable signals OE1, OE2,..., OEn, where n is a natural number, and a first output enable signal, shifting the first output enable signal OE0 in response to CL). A final output enable signal generation unit 300 for outputting any one of (OE0) as the final output enable signal OE_FIN may be provided.

The first output enable signal generator 100 counts from the predetermined initial counting value according to the DLL clock to output a first counting value output unit 110 for outputting the DLL clock counting value CNT_DLL <0: 1>; The second counting value output unit 130 for counting the external clock CLK_EXT until the read command RD is input and outputting the external clock counting value CNT_RD <0: 1>, and the DLL clock counting value CNT_DLL. And a comparator 150 for outputting the first output enable signal OE0 by comparing the external clock counting value CNT_RD <0: 1>.

Meanwhile, according to the present invention, the first reset signal RST_DLL is generated in response to the reset signal RST and the DLL clock CLK_DLL corresponding to an external command (eg, / RAS, / CAS, / CS, / WE). The counter reset signal generator 170 may be further provided.

The first counting value output unit 110 initializes 112 to provide an initial counting value to the DLL clock counting unit 114 in response to the first reset signal RST_DLL output from the counter reset signal generation unit 170. And a DLL clock counting unit 114 for outputting the DLL clock counting value CNT_DLL <0: 1> by counting from the initial counting value according to the DLL clock CLK_DLL. Here, the DLL clock counting unit 114 uses a 2-bit counter that responds to the output signals S <0: 1> and R <0: 1> of the initialization unit 112, which is initially set. It is desirable to be designed to correspond to the maximum counting value that can be. That is, as in the embodiment, when the maximum value of the initial counting value is 4, a 2-bit counter that can count up to 4 may be used.

FIG. 7 is a circuit diagram illustrating the initialization unit 112 of FIG. 6.

Referring to FIG. 7, the initialization unit 112 sets the initial counting value of the DLL clock counting unit 114 to 1 when the first reset signal RST_DLL is logic 'high' (even before the mode register set is set). The output signals S <0: 1> and R <0: 1> are generated. The configuration for setting the initial counting value to 2 may be easily performed by those skilled in the art with reference to FIG. 7, and thus the circuit configuration and description thereof will be omitted.

According to the present invention, a desired operation can be secured even if the initial counting value does not change depending on the cascade latency CL. Therefore, even if the cascade latency CL is changed, the DLL clock counting unit 114 does not need to be reset, and a detailed operation thereof will be described with reference to FIGS. 9 and 10.

Referring to FIG. 6 again, a delay of generating the second reset signal RST_CLK for activating the second counting value output unit 130 by reflecting the delay element of the DLL clock CLK_DLL in the first reset signal RST_DLL. The model unit 190 may be further provided.

The second counting value output unit 130 includes an external clock counting unit 132 for counting according to the external clock CLK_EXT in response to the second reset signal RST_CLK output from the delay model unit 190, and a read command. And a latching unit 134 for latching the output value CNT_CLK <0: 1> of the external clock counting unit 132 and outputting the external clock counting value CNT_RD <0: 1> in response to RD. can do. Here, the external clock counting unit 132 used a 2-bit counter. The external clock counting unit 132 preferably uses a counter having the same number of bits as the DLL clock counting unit 114.

Meanwhile, the DLL clock counting value CNT_DLL <0: 1> output from the DLL clock counting unit 114, the output value CNT_CLK <0: 1> of the external clock counting unit 132, and the latching unit 134. The external clock counting value (CNT_RD <0: 1>) output from the N-th may have a plurality of bit signals, which may vary depending on the design.

8 is a circuit diagram illustrating the comparison unit 150 of FIG. 6.

Referring to FIG. 8, a configuration for comparing a 2-bit DLL clock counting value (CNT_DLL <0: 1>) and an external clock counting value (CNT_RD <0: 1>), and is activated when each value is the same. 1 Output the enable signal OE0. The design of the comparator 150 may also vary in design depending on the number of bits input.

Referring to FIG. 6 again, the final output enable signal generator 300 may include a plurality of shifting units 310, 330, 350, for shifting the first output enable signal OE0 in response to the DLL clock CLK_DLL. 370 and a signal multiplexing signal for outputting any one of the first to nth output enable signals OE0, OE1,..., OEn as the final output enable signal OE_FIN in response to the cascade latency CL. The unit 390 may be provided.

In the present exemplary embodiment, each of the plurality of shifting parts 310, 330, 350, and 370 is configured as a D flip-flop (DFF), but other flip-flops or other configurations may be used. In other words, the plurality of shifting units 310, 330, 350, and 370 include the plurality of output enable signals OE1, OE2, OE3,... As the first output enable signal OE0 is synchronized with the DLL clock CLK_DLL. OEn). The signal multiplexer 390 may be configured as a general multiplexer.

9 and 10 are timing diagrams for describing an operation timing of the output enable signal generator of FIG. 6. FIG. 9 is a case where the cascade latency CL is 4 and will be described with reference to FIGS. 6 and 9.

According to the present invention, since the initial counting value does not need to be changed every time the cascade latency CL is changed, for example, the initial counting value is set to 1.

First, when the first reset signal RST_DLL becomes logic 'low', the DLL clock counting unit 114 outputs a DLL clock counting value CNT_DLL <0: 1> counting from 1, which is an initial counting value. After the delay time of the delay model unit 190 is reflected in the first reset signal RST_DLL, when the second reset signal RST_CLK becomes logic 'low', the external clock counting unit 132 starts counting.

At this time, when the read command RD is input, the latching unit 134 latches 2, which is the value CNT_CLK <0: 1>, counting the external clock CLK_EXT, and the external clock counting value CNT_RD <0: 1>. Will output The comparator 150 compares the DLL clock counting value CNT_DLL <0: 1> and the external clock counting value CNT_RD <0: 1>, that is, the DLL clock counting value CNT_DLL <0: 1>. When 2 is reached, the first output enable signal OE0 is output.

The plurality of shifting units 310, 330, 350, and 370 of the final output enable signal generator 300 shift the first output enable signal OE0 in response to the DLL clock CLK_DLL. (OE1, OE2, ..., OEn), and the signal multiplexer 390 outputs a desired final output enable signal OE_FIN in response to the cascade latency CL.

Here, the second output enable signal OE1 is selected according to the cascade latency CL, and the data D0, D1, D2, and D3 are output terminals DQ using the selected second output enable signal OE1. Is output.

FIG. 10 will be described with reference to FIGS. 6 and 10 as the cascade latency CL is five.

As shown in FIG. 9, since the initial counting value does not need to be changed every time the cascade latency CL is changed, the initial counting value is set to 1 in the same manner.

First, when the first reset signal RST_DLL becomes logic 'low', the DLL clock counting unit 114 outputs a DLL clock counting value CNT_DLL <0: 1> counting from 1, which is an initial counting value. After the delay time of the delay model unit 190 is reflected in the first reset signal RST_DLL, when the second reset signal RST_CLK becomes logic 'low', the external clock counting unit 132 starts counting.

At this time, when the read command RD is input, the latching unit 134 latches 2, which is the value CNT_CLK <0: 1>, counting the external clock CLK_EXT, and the external clock counting value CNT_RD <0: 1>. Will output The comparison unit 150 compares the DLL clock counting value CNT_DLL <0: 1> and the external clock counting value CNT_RD <0: 1>, that is, the DLL clock counting value CNT_DLL <0: 1>. When 2 becomes 2, the first output enable signal OE0 is output.

The plurality of shifting units 310, 330, 350, and 370 of the final output enable signal generator 300 shift the first output enable signal OE0 in response to the DLL clock CLK_DLL. (OE1, OE2, ..., OEn), and the signal multiplexer 390 outputs a desired final output enable signal OE_FIN in response to the cascade latency CL.

Here, the third output enable signal OE2 is selected according to the cascade latency CL, and the data D0, D1, D2, and D3 are output terminals DQ using the third output enable signal OE2 thus selected. Is output.

As described above, the present invention counts according to the DLL clock (CLK_DLL) from the predetermined initial counting value (in this specification, 1 is set as the initial counting value in FIGS. 9 and 10) in outputting the first output enable signal. Outputs the two-bit DLL clock counting value (CNT_DLL <0: 1>) and the external clock counting value (CNT_RD <0: 1>) counting the external clock (CLK_EXT) until the read command (RD) is input. do. The first output enable signal OE0 generated as described above becomes a signal already synchronized to the DLL clock CLK_DLL.

In outputting the final output enable signal OE_FIN, a plurality of output enable signals OE1, OE2, ..., shifted from the first output enable signal OE0 in response to the DLL clock CLK_DLL. OEn), and an output enable signal corresponding to the cascade latency CL among the first output enable signal OE0 and the plurality of output enable signals OE1, OE2, ..., OEn is the final output. Output as an enable signal OE_FIN. Data is output using the final output enable signal OE_FIN thus generated.

As a result, according to the present invention, it is possible to generate a desired final output enable signal OE_FIN without changing the initial counting value every time the cascade latency CL is changed.

Therefore, since the initial counting value output from the initialization unit 112 can be set regardless of whether or not the mode register set is set, the DLL clock counting unit 114 also changes the cascade latency CL even if the cascading time CL is changed. You do not have to perform the reset operation. In addition, the DLL clock counting unit 114 and the external clock counting unit 134 do not have to extend the design of the counter according to the cascade latency CL, and accordingly, the latching unit 134 and the comparison unit 150 are additionally designed. There is no need. As a result, the current consumption during the active operation or the standby operation can be minimized, and the final output enable signal OE_FIN can be generated without unnecessary delay time.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, a case of domain crossing between the DLL clock CLK_DLL and the external clock CLK_EXT has been described as an example. However, the present invention can be applied to domain crossing between different clocks.

1 is a block diagram illustrating a conventional output enable signal generating apparatus.

FIG. 2 is a circuit diagram illustrating an initialization unit of FIG. 1. FIG.

3 is a circuit diagram for explaining a comparison unit of FIG. 1.

4 and 5 are timing diagrams for explaining the operation timing of the output enable signal generator of FIG.

6 is a block diagram illustrating an output enable signal generation device of a semiconductor memory device according to the present invention;

FIG. 7 is a circuit diagram illustrating the initialization unit of FIG. 6. FIG.

FIG. 8 is a circuit diagram for explaining a comparison unit of FIG. 6. FIG.

9 and 10 are timing diagrams for describing operation timings of the output enable signal generating apparatus of FIG. 6.

* Explanation of symbols for the main parts of the drawings

100: first output enable signal generator 110: first counting value output unit

112: initialization unit 114: DLL clock counting unit

130: second counting value output unit 132: external clock counting unit

134: latching section 150: comparison section

170: reset signal generation unit 190: delay model unit

300: final output enable signal generator

310, 330, 350, 370: de-flip-flop (DFF) 390: signal multiplexer

Claims (17)

First output enable signal generating means for generating a first output enable signal by comparing a value counted from a DLL clock with a value counted from an external clock until a read command is input; A final output for outputting any one of a plurality of output enable signals shifted from the first output enable signal in response to the DLL clock and the first output enable signal as final output enable signals in accordance with cascade latency information; Enable signal generation means A semiconductor memory device having a. The method of claim 1, The first output enable signal generating means, First counting value output means for counting according to the DLL clock to output a first counting value; Second counting value output means for counting the external clock until the read command is input and outputting a second counting value; And And comparing means for comparing the first and second counting values to output the first output enable signal. The method of claim 2, And a reset signal generation unit configured to generate a first reset signal for activating the first counting value output means in response to a signal corresponding to an external command and the DLL clock. The method of claim 3, The first counting value output means, An initialization unit for providing an initial counting value in response to the first reset signal; And a DLL clock counting unit for counting the initial counting value from the initial counting value and outputting the first counting value. The method of claim 4, wherein And the DLL clock counting unit includes a counter corresponding to a maximum value of the initial counting value. The method of claim 4, wherein And a delay model unit which generates a second reset signal for activating the second counting value output means by reflecting the delay element of the DLL clock in the first reset signal. The method of claim 6, The second counting value output means, An external clock counting unit for counting according to the external clock in response to the second reset signal; And a latching unit for latching an output value of the external clock counting unit in response to the read command and outputting the output value as the second counting value. The method of claim 7, wherein And the external clock counting unit includes a counter corresponding to a maximum value of the initial counting value. The method of claim 2, And the first counting value and the second counting value include a plurality of bit signals. The method of claim 1, The final output enable signal generating means, A plurality of shifting units for generating the plurality of output enable signals shifted in the first output enable signal in response to the DLL clock; And a signal multiplexer configured to output one of the first output enable signal and the plurality of output enable signals as the final output enable signal in response to the cascade latency information. The method of claim 10, And each of the plurality of shifting units includes a de-flop flop. A first counting step of counting according to a DLL clock to output a first counting value; A second counting step of counting an external clock until a read command is input and outputting a second counting value; Outputting a first output enable signal by comparing the first and second counting values; Shifting the first output enable signal in response to the DLL clock to generate a plurality of output enable signals; And A final output enable signal output step of outputting any one of the first output enable signal and the plurality of output enable signals as a final output enable signal in response to cascade latency information. Method of driving a semiconductor memory device comprising a. The method of claim 12, And generating a first reset signal for activating the first counting step in response to a signal corresponding to an external command and the DLL clock. The method of claim 13, The first counting step, Providing an initial counting value in response to the first reset signal; And counting from the initial counting value according to the DLL clock to output the first counting value. The method of claim 13, And generating a second reset signal for activating a second counting step by reflecting the delay element of the DLL clock to the first reset signal. The method of claim 15, The second counting step, Counting according to the external clock in response to the second reset signal; And latching a value counting the external clock in response to the read command and outputting the counted value as the second counting value. The method of claim 14, And wherein the first counting value and the second counting value comprise a plurality of bit signals.

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