JP2998501B2 - Clock signal / synchronous reset signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal / synchronous reset signal generating circuit used for a sequential logic circuit or the like.

[0002]

2. Description of the Related Art As a clock signal generating circuit for dividing a system clock to obtain an arbitrarily synchronized clock signal, there is a conventional one using a counter 1 as shown in FIG. The counter 1 used here has an appropriate b
When a reset signal REST of "H" is input as shown in FIG. 12B from the outside, the register is cleared. When "L" is input to the RST terminal, CLK is reset. When the value of the system clock signal SCLK input to the terminal shown in FIG. 12A changes from "L" to "H", this is a counter that increments the value of the register.
The signal is output from the terminal as shown in FIG.

A signal obtained by dividing the system clock signal SCLK by a desired number of times is obtained from the counter 1. However, when the reset signal REST is "H", the output of the counter 1 does not change because the counter 1 does not operate. Even at the time of reset, the output of the counter 1 cannot be supplied as a clock signal to a block in which the clock signal needs to change. Therefore, the reset signal REST is used by using the selector 2.
Is "H", the system clock signal SCLK is supplied to the other blocks as the clock signal CLK, and the output of the selector 2 shown in FIG. FIG. 12 is a time chart when the clock signal CLK is generated by dividing the system clock signal SCLK once.

[0004]

However, in the above-mentioned conventional example, there is a problem that a malfunction may occur depending on the timing at which the reset signal REST is input. FIG. 13 shows a time chart in the case where the system clock signal SCLK is frequency-divided twice to generate the clock signal CLK via the selector 2.
In the regions (a), (b) and (c) of FIG. 13 (d), the reset signal REST is “H” as shown in FIG. 13 (b), so that the selector 2 is shown in FIG. 13 (a). In the part where the system clock signal SCLK is selected and output as the clock signal CLK, the area (d) shows that the reset signal REST is “
L ”, the selector 2 selects the output of the counter 1 and outputs it as the clock signal CLK.
Here, in the portion (a) where the reset signal REST changes from "L" to "H" and the portion (c) where the reset signal REST changes from "H" to "L", the reset is performed when the system clock signal SCLK is "H". The signal REST is changing, and as a result, the clock signal CLK output from the selector 2 appears as a signal that is "H" for a time shorter than the system clock signal SCLK. Next, consider a case where the circuit of the conventional example is used as a clock signal generation block of an LSI constituting a certain logic procedure circuit.

FIG. 14 shows a state where the clock signal generating circuit shown in FIG. 11 supplies a clock signal to another block in the same LSI. Clock generation circuit C
G receives a system clock signal SCLK and a reset signal REST and outputs a clock signal CLK. This clock signal CLK is input to the CLK terminal of the block B inside the LSI.
And the block B, the clock signal CLK is supplied to the CL of the block B via the delay element D1.
It is assumed that the signal is input to the K terminal. Similarly, the reset signal REST is input to the RST terminal of the block B via the delay element D2.

FIG. 15 is a time chart when the delay time of the delay element D1 is longer than the delay time of the delay element D2. In this example, the delay time of the delay element D1 is shown in FIG.
(A) is one cycle of the system clock signal SCLK, and the delay time of the delay element D2 is set to the system clock signal SC.
It is set to the half cycle of LK. In such a case, block B
When the clock signal CLK ′ shown in FIG. 15 (e) and the reset signal REST ′ shown in FIG.
The reset signal REST 'of the delay element D2 is input earlier, and an incorrect clock signal (e) is input after the reset signal REST' becomes "L".
The original clock signal used by the block B after the reset is released is (f), and the input of the clock signal (e) causes a malfunction. The period during which the clock signal (e) is "H" depends on the timing at which the reset signal REST changes, and cannot be predicted in advance. Therefore, in the above example, it is not possible to know in advance whether a malfunction will occur. FIG.
(B) and (c) show a reset signal REST input to the clock generation circuit CG and a clock signal CLK output, respectively.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a clock signal which eliminates the possibility that a block in an LSI for supplying a clock signal and a reset signal malfunctions when reset is released. A synchronous reset signal generating circuit is provided.

[0008]

According to a first aspect of the present invention, a clock signal / synchronous reset signal generating circuit divides a system clock signal input from outside of an LSI to an arbitrary period to achieve the above object. A synchronous counter for generating a clock signal output, and an appropriate delay applied to a reset signal input from outside of the LSI to generate an internal reset signal and to stop generating the clock signal when the output of the reset signal changes. And a reset signal generating circuit for generating a reset signal for a synchronous counter.

A clock signal / synchronous reset signal generating circuit according to a second aspect of the present invention is the clock signal / synchronous reset signal generating circuit according to the first aspect, wherein
An initialization circuit for adding a signal to be in a reset state for a predetermined period after a predetermined time after the reset signal is released, and outputting the signal to the reset signal generation circuit.

[0010]

According to the structure of the present invention, the LS signal can be output regardless of the input timing of the reset signal input from outside the LSI.
An internal reset signal that changes when the clock signal is stopped can be given to other blocks in I, and the possibility that a block malfunctions when reset is released can be eliminated.

[0011]

The present invention will be described below with reference to examples.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, a synchronous counter 10 outputs a clock signal CLK obtained by dividing a system clock signal SCLK inputted from outside the LSI into a desired period. . On the other hand, 11 reset signal generation circuits are provided with a reset signal REST from outside the LSI.
To the reset signal input terminal RSTIN to output the reset signal CREST for the synchronous counter and the internal reset signal REST '.

The clock signal CLK and the internal reset signal REST 'are supplied to other blocks in the LSI.

FIG. 2 is a time chart of the above embodiment. In the illustrated example, the system clock signal SCLK shown in FIG. Is output as shown in FIG. As shown in FIG. 2C, the reset signal CREST for the synchronous counter changes from "L" to "H" for a while after the reset signal REST shown in FIG. 2B changes. As a result, when the clock signal CLK is stopped,
The reset signal REST is appropriately delayed so as to change, and output as an internal reset signal REST 'shown in FIG. Other blocks present in the LSI are clock signals
Since the CLK and the internal reset signal REST 'are used as a clock signal and a reset signal, a malfunction due to an incorrect clock signal as in the conventional example does not occur.

FIG. 3 shows a specific example of the above embodiment.
The synchronous counter 10 is internally constituted by a counter having a register of 1 bit length. When the synchronous counter reset signal CREST of "H" is input to the RST terminal, the synchronous counter 10 sets the value of the register to 0. When the rising edge of the system clock signal SCLK shown in FIG. 4A comes to the CLK terminal, the value of the register is incremented. If a rising edge is further input when the value of the register is "1", the value of the register becomes "0". O
The value of this register is output to the UT terminal, whereby the synchronous counter 10 receives the input system clock signal SC.
The clock signal CL shown in FIG.
Works to convert to K.

The reset signal generation circuit 11 has a counter C
1 and C2, comparators CMP1 and CMP2, flip-flops F1 to F4, an OR gate OR, and a NOT gate NT. Each of the counters C1 and C2 has a register having a width of 3 bits. When each of the RST terminals is "H", When the value of the register is set to 0, the value of the register is incremented when the RST terminal is "L" and the value of the register is 4 or less, the value of the register having a width of 3 bits is output as it is. The comparators CMP1 and CMP2 output “H” when the input data is 1 or more and 4 or less, and output “L” otherwise. And these counters C
1 and C2 and the comparators CMP1 and CMP2, the reset signal RE shown in FIG.
As shown in FIG. 4 (c), "H" is input only during a period of one to five cycles of the system clock signal SCLK from the time when ST changes from "L" to "H". Only during a period from one cycle to five cycles of the system clock signal SCLK from the time when the reset signal REST changes from “H” to “L”, FIG.
"H" is input as shown in FIG. The result of the OR operation of both input signals is the reset signal for the synchronous counter.
CREST. Further, the flip-flops F1 to F4 delay the reset signal REST by the time of four cycles of the system clock signal SCLK, and set the internal reset signal RES shown in FIG.
Output as T '. In the above specific example, the clock signal CLK having the necessary characteristics can be easily changed by changing the setting of the synchronous counter 10, the setting of the counters C1 and C2 in the reset signal generating circuit 11, and the number of shift registers for the internal reset signal. An internal reset signal REST 'can be obtained.

In the configuration shown in FIG. 3, the counter C1 of the reset signal generation circuit 11 is a counter which is reset when the RST terminal goes "L" and is incremented when it goes "H", and the counter C2 is RST terminal is "
The counter is reset when the signal becomes H, and is incremented when the signal becomes L. At the time of power-on reset, the register values of the counters C1 and C2 are as shown in Fig. 5. In Fig. 5, (a) is a diagram. It shows an example of a reset signal REST at power-on, which is a signal that changes only from "H" to "L". (B) shows the register value of the counter C1, and (c) shows the register value of the counter C2. ing.
As shown in the figure, the counter C2 is reset and operates normally when the reset signal REST is "H".
As shown in (1), since the counter C1 has not been reset, the registration value thereof is undefined, and there is a possibility that a normal synchronous counter reset signal cannot be output. Therefore, if this circuit is applied to a circuit in which a reset signal REST supplied from the outside only changes from "H" to "L" at the time of power-on reset, the counter C1 cannot be initialized properly, causing a malfunction. When the clock signal / synchronous reset signal generation circuit of the present invention is applied to such a circuit, the circuit may be configured, for example, as shown in the block diagram of FIG.

In a different embodiment shown in FIG. 6, an initialization circuit 21 is added to the clock signal / synchronous reset signal generation circuit shown in FIG. The initialization circuit 21 is configured as shown in FIG.
As shown in FIG. 7B, a reset signal REST as shown in FIG. 7A is input, and as shown in FIG. 7B, after a certain time when the reset signal REST changes from "H" to "L", " This circuit supplies the reset signal generation circuit 11 with an initialization signal RTEST '' to which a signal that changes to "L" after outputting "H" for a predetermined time. FIG. 7C shows the counter C1.
FIG. 7D shows the register value of the counter C2. Thus, the reset signal REST is set to “L”.
After resetting the counter C1, the counter C1 and C2 can be normally reset by setting the reset signal REST to "H" for a predetermined period.

A specific circuit of the embodiment shown above will be described with reference to FIG. The clock signal / synchronous reset signal generation circuit shown in the figure has a register of 1 bit length internally, synchronizes the system clock SCLK by two times and outputs a clock signal CLK, and a reset signal generation circuit. 11 and an initialization circuit 21 connected before the reset signal generation circuit 11. A function of supplying the system clock signal SCLK to the synchronization counter 10, the reset signal generation circuit 11, and the initialization circuit 21, and inputting the reset signal REST to the initialization circuit 21 to normally initialize the reset signal generation circuit 11. Initialization signal having
The signal is converted to REST '' and supplied to the reset signal generation circuit 11.

In the initialization circuit 21, C3 is a counter having a register of 4-bit length, and the reset signal REST is "H".
In the case of (1), when the reset signal REST is "L" and the data is 14 or less, the data is incremented, and the value held in the 4-bit length register is output as it is as data DATA. In CMP3, the 4-bit length data DATA input from the counter C3 is 0.
A comparator which outputs "L" in the case of 6 or less or 15 or "H" in other cases. S1 receives the reset signal REST and the output of the comparator CMP3, and outputs the reset signal REST. Is “H”, the reset signal REST (“H”)
And when the reset signal REST is “L”, the comparator C
This is a selector that outputs the output of MP3. FIG. 9 shows a time chart of the initialization circuit 21 configured as described above. As shown in FIG. 9B, the reset signal REST is “
H ", the data DA which is the output of the counter C3
TA (FIG. 9C) is reset to 0, and as shown in FIG. 9D, the reset signal REST of "H" is output as it is as the initialization signal REST ". . When the reset signal REST changes from “H” to “L”, since the data DATA is 0, the comparator C which is “L”
The output of MP3 is output as an initialization signal REST ″. Since the RST terminal of the counter C3 is in the "L" state, the data DATA of the counter C3 is incremented, and while the data DATA is from 1 to 6, the comparator CMP3 is in the "L" state.
And the comparator CMP3 outputs "H" while the data DATA is between 7 and 14. After that, the data DATA
Is no longer incremented when it reaches 15, and the comparator CMP3 outputs "" as the initialization signal REST ".
An L "state is output.

FIG. 10 is a time chart at the time of power-on reset of the clock signal / synchronous reset signal generation circuit shown in FIG. In the figure, (a) is a system clock signal SCLK, (b) is an externally applied reset signal REST, (c) is an output of the comparator CMP1, (d) is an output of the comparator CMP2, and (e) is a clock signal. CLK, (f)
Is the internal reset signal REST ', and (g) is the initialization signal REST''
It is. As shown in the figure, the counter C1 is reset for the first time at the portion (g) where the initialization signal REST "is" L ", and at the portion (h) during the period when the initialization signal REST" is "H". The register is incremented and the correct comparator C
The output (c) of MP1 is obtained. Also, the counter C2 is reset again at the portion (h) of the initialization signal REST ″, so that the normal output (d) of the comparator CMP2 is obtained.
As a result, the clock signal CLK is set to “” at the time of the rise and fall of the portion (i) of the internal reset signal REST ′.
L ", and the other blocks of the LSI are normally reset at the (R) portion of the internal reset signal REST '.

As described above, by adding the initialization circuit 21 to the clock signal / synchronous reset signal generation circuit shown in FIG. 3, the reset signal input from outside the LSI changes from "H" to "L". Even if the circuit is just
The clock signal / synchronous reset signal generation circuit can be correctly initialized, and malfunction can be prevented. Note that the initialization circuit is not limited to the circuit of the embodiment.

[0023]

The present invention provides a synchronous counter which divides a system clock signal input from outside the LSI to generate a clock signal output of an arbitrary period, and an appropriate delay for a reset signal input from the outside of the LSI. And a reset signal generating circuit for generating a reset signal for a synchronous counter for generating an internal reset signal and stopping the generation of the clock signal when the output of the internal reset signal changes. Regardless of the input timing of the reset signal, an internal reset signal that changes when the clock signal is stopped can be given to other blocks in the LSI,
There is an effect that it is possible to eliminate the possibility that another block of the LSI may malfunction when reset is released.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the above operation.

FIG. 3 is a specific circuit diagram of the above.

FIG. 4 is a time chart for explaining the operation of the above specific circuit.

FIG. 5 is a time chart for explaining a malfunction of the concrete circuit according to the embodiment.

FIG. 6 is a circuit block diagram showing another embodiment of the present invention.

FIG. 7 is a time chart for explaining the operation of another embodiment of the present invention.

FIG. 8 is a specific circuit diagram of another embodiment of the present invention.

FIG. 9 is a time chart of an initialization circuit according to another embodiment of the present invention.

FIG. 10 is a time chart for explaining the operation of another embodiment of the present invention.

FIG. 11 is a circuit block diagram of a conventional example.

FIG. 12 is a time chart for explaining the above operation.

FIG. 13 is a time chart for explaining the malfunction of the above.

FIG. 14 is a block diagram when the above is incorporated in an LSI.

FIG. 15 is a time chart for explaining the above operation.

[Explanation of symbols]

 10 Synchronous counter 11 Reset signal generation circuit 21 Initialization circuit SCLK System clock signal CLK Clock signal REST Reset signal REST 'Internal reset signal REST' 'Initialization signal CREST Reset signal for synchronous counter

Continuation of the front page (56) References JP-A-63-169826 (JP, A) JP-A-2-256321 (JP, A)

Claims (2)

(57) [Claims] 1. A synchronous counter for dividing a system clock signal input from the outside of an LSI to generate a clock signal output of an arbitrary period, and an internal reset by applying an appropriate delay to a reset signal input from the outside of the LSI A reset signal generating circuit for generating a reset signal for a synchronous counter for generating a signal and stopping the generation of the clock signal when the output of the internal reset signal changes. Reset signal generation circuit. 2. An initialization circuit for adding a signal to be in a reset state for a predetermined period after a predetermined time from when the reset signal is released to the reset signal and outputting the reset signal to the reset signal generation circuit. The clock signal / synchronous reset signal generation circuit according to claim 1.