JPH0746115A - Input/output circuit - Google Patents

Abstract

PURPOSE:To provide the input/output circuit which can be operated without being affected by an external transmission line connected to an input/output terminal. CONSTITUTION:In the input/output circuit provided with an output buffer circuit 100, which is switched to the input state or the output state by the control of a three-state control signal and outputs an output control signal to an input/ output terminal 28 in the case of the output state, and an input buffer circuit 200 which is connected to an input/output terminal 28 and outputs the signal from an external transmission line 300 inputted to the input/output terminal 28 to an internal circuit, a selector circuit 400 is provided which is controlled by the three-state control signal and transmits the output control signal to the internal circuit but cuts off the signal from the external transmission line 300 in the case of the output state and cuts off the output control signal but transmits the signal from the external transmission line 300 to the internal circuit in the case of the input state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit, and more particularly to an input / output circuit with reduced influence from an external transmission line connected to an input / output terminal.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional input / output circuit. The input / output circuit includes an output buffer circuit 100 and an input buffer circuit 200. The output buffer circuit 100 selects the input state or the output state under the control of the three-state “Z” control signal 15, and outputs the output control signal 14 to the input / output terminal 28 in the output state.
To output to. This circuit configuration has a CMOS inverter 16, a NAND circuit 17, a NOR circuit 18, and a P-type M.
The OS transistor 19 and the N-type MOS transistor 20 are connected as shown in the figure.

The output control signal 14 and the three-state "Z" control signal 15 are input to the input terminal of the NAND circuit 17. In addition, the input buffer circuit 200
Is a CMOS inverter including a P-type MOS transistor 21 and an N-type MOS transistor 22, and a signal from the node 10 is transmitted to an internal circuit (not shown).
An external transmission path 300 is connected to the input / output terminal 28, and the external transmission path 300 can be considered as an equivalent circuit of the external capacitor 29 and the external resistor 30.

As described above, the conventional input / output circuit employs a configuration in which the input / output terminal 28 is provided between the output buffer circuit 100 and the input buffer circuit 200, and the signal from the external transmission path 300 is input / output. It is configured to be transmitted to the input buffer circuit 200 through the terminal 28 and enter the internal circuit from the node 10.

[0005]

In the conventional input / output circuit as shown in FIG. 3, the external resistance 30 and the external capacitance 2 of the external transmission path 300 connected to the input / output terminal 28 in the output state.
9 has a problem that ringing noise or the like is superimposed on the input / output terminal 28 and is transmitted to the internal circuit via the input buffer circuit 200.

FIG. 4 is a waveform diagram at each operating point in FIG. 3, in which the output control signal 14 as shown in FIG. 4A has ringing noise as shown in FIG. However, there is a problem that the internal circuit malfunctions because it appears at the node 10 via the input buffer circuit 200.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide an input / output circuit which can operate without being affected by an external transmission path connected to an input / output terminal. .

[0008]

According to the present invention, an input buffer and an output state are selected by controlling a three-state control signal as a control signal, and an output control signal is output to an input / output terminal in the output state. And an input buffer circuit that is connected to the input / output terminal and outputs a signal from the external transmission path input to the input / output terminal to an internal circuit, controlled by the three-state control signal. In the output state, the output control signal is transmitted to the internal circuit, but the signal from the external transmission path is cut off, in the input state, the output control signal is cut off, and the signal from the external transmission path is sent to the internal circuit. A selector circuit for transmission is provided.

[0009]

According to the present invention, the selector circuit is provided between the input buffer circuit and the signal transmission node to the internal circuit, and the selector circuit is controlled by the three-state control signal so that the output control signal is output from the node to the internal circuit in the output state. However, the signal from the external transmission path is blocked. In the input state, the output control signal is cut off and only the signal from the external transmission path is transmitted to the internal circuit. Therefore, even if noise from the external transmission path is superimposed on the input / output terminals, the signal from the external transmission path is not transmitted to the internal circuit by the selector in the output state. The problem of becoming unstable can be solved.

[0010]

FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the present invention, the selector circuit 400 is provided between the node 27 which is a transmission point of a signal to the internal circuit and the output terminal of the input buffer circuit 200. The selector circuit 400 is controlled by the three-state "Z" control signal 15 and outputs the output control signal 14 to the node 2
7 and the operation of transmitting the signal from the input / output terminal 28 to the node 27 are switched.

In the conventional circuit shown in FIG. 3, when the output control signal 14 is transmitted to the internal circuit (not shown) via the node 10, it is performed via the input / output terminal 28. Therefore, the external transmission path 300 connected to the input / output terminal 28
The ringing noise and the like are directly generated by the input / output terminal 28 and are transmitted from the node 10 to the internal circuit to cause a malfunction.

The present invention solves the above-mentioned problem by providing a selector circuit 400 as shown in FIG. In this selector circuit 400, the transfer gate 23 whose input side is connected to the output terminal of the input buffer circuit 200 and the output side is connected to the node 27, the output control signal 14 is connected to the input side, and the input terminal of the CMOS inverter 26 is connected to the output side. Control of the transfer gate 23, the CMOS inverter 26 that inverts the signal on the output side of the transfer gate 24 and outputs the inverted signal to the node 27, and the inversion of the signal of the three-state “Z” control signal 15 to control the transfer gate 23 and the transfer gate 24. It is composed of a CMOS inverter 25 supplied to a terminal.

Here, the transfer gate 23 and the transfer gate 24 are controlled by the three-state "Z" control signal 15, and when one of them is turned on, the other is turned off. That is, the selector operation is performed, and either the signal from the input buffer circuit 200 or the output control signal 14 is applied to the node 2
The operation output to 7 is performed. When the logic of the three-state “Z” control signal 15 becomes “1” and the output state is selected, the output control signal 14 turns on the transfer gate 24 and turns off the transfer gate 23, so that the output control signal is applied to the node 27. The inverted signal of the signal 14 is transmitted in the state as shown in FIG. Since the transfer gate 23 is in the off state, ringing noise or the like superimposed on the input / output terminal 28 is not transmitted to the node 27.

Next, when the logic of the three-state "Z" control signal 15 becomes "0" and is not in the output state, that is, when the input / output terminal 28 is in the input state or the three-state "Z" state, the transfer gate 23 is turned on. The transfer gate 24 is turned off. At this time, the input signal from input / output terminal 28 is propagated to node 27.

FIG. 2 is a waveform diagram at each operating point in FIG. 1. In the output state, ringing noise is not transmitted to the node 27 as shown in (C).

[0016]

As described above in detail with reference to the embodiments, in the present invention, the selector circuit is inserted so that the signal from the input / output terminal is cut off in the output state. It is possible to solve the problem that the internal circuit malfunctions due to the influence.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram at each operating point in FIG.

FIG. 3 is a circuit diagram of a conventional input / output circuit.

FIG. 4 is a waveform diagram at each operating point in FIG.

[Explanation of symbols]

 14 output control signal 15 three-state “Z” control signal 16, 25, 26 CMOS inverter 17 NAND circuit 18 NOR circuit 19, 21 P-type MOS transistor 20, 22 N-type MOS transistor 23, 24 transfer gate 27 node 28 input / output terminal 29 External capacitance 30 External resistance 100 Output buffer circuit 200 Input buffer circuit 300 External transmission path 400 Selector circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/003 Z 8842-5J

Claims (1)

[Claims] 1. An output buffer circuit for selecting an input state and an output state by controlling a control signal and outputting an output control signal to an input / output terminal in the output state,
In an input / output circuit connected to the input / output terminal, the input buffer circuit outputting a signal from an external transmission path input to the input / output terminal to an internal circuit, the input / output circuit being controlled by a control signal A selector circuit that transmits an output control signal to the internal circuit but blocks a signal from the external transmission path, blocks the output control signal in an input state, and transmits a signal from the external transmission path to the internal circuit. An input / output circuit characterized by being provided.