JPH0745953A - Manufacture of multilayer wiring board - Google Patents

Manufacture of multilayer wiring board

Info

Publication number
JPH0745953A
JPH0745953A JP18459993A JP18459993A JPH0745953A JP H0745953 A JPH0745953 A JP H0745953A JP 18459993 A JP18459993 A JP 18459993A JP 18459993 A JP18459993 A JP 18459993A JP H0745953 A JPH0745953 A JP H0745953A
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
eyelet
molding
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18459993A
Other languages
Japanese (ja)
Other versions
JP3237324B2 (en
Inventor
Shuji Kitagawa
修次 北川
Yoshinori Urakuchi
良範 浦口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP18459993A priority Critical patent/JP3237324B2/en
Publication of JPH0745953A publication Critical patent/JPH0745953A/en
Application granted granted Critical
Publication of JP3237324B2 publication Critical patent/JP3237324B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards

Abstract

PURPOSE:To provide a manufacturing method, of a multilayer wiring board, which can reduce an irregularity in the interlayer positional accuracy of the multilayer wiring board whose sheet thickness after a molding operation is at a specific thickness. CONSTITUTION:In the manufacturing method of a multilayer wiring board, a laminated body in which prepregs 2 are arranged on every surface and every rear surface of a plurality of inner layer materials 1 is fixed by eyelet pins 3, metal foils 5 are arranged on outermost layers, the multilayer wiring board is molded, and a sheet thickness after its molding operation is 0.3 to 1.0mm. In the manufacturing method of the multilayer wiring board, the height (h) of the eyelet pins 3 before their caulking operation satisfies a formula of h<=b+d [in the formula, (h) represents the height of the eyelet pins before their caulking operation, (b) represents the width of a guard part at every eyelet pin, and (d) represents the sheet thickness after the molding operation of the multilayer wiring board].

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器等に使用され
る多層配線板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board used in electronic equipment and the like.

【0002】[0002]

【従来の技術】従来、多層配線板の製造方法は図4に示
すように回路7を有する複数の内層材1,1間にプリプ
レグ2を配し、これらを所要位置でハトメピン3にてか
しめて固定し、その後、その両側にプリプレグ2、そし
て最外層に金属箔5を配して、成形プレート6,6にて
挟んで積層成形する方法が知られていた。しかし、この
方法では、積層成形時にずれが生じやすく、成形異常と
なり、良品を歩留りよく得られないという問題があり、
このずれを防止する方法が検討され、本発明者等も特開
平3−129797号において、図1に示すように複数
の内層材1,1の各上面及び又は下面にプリプレグ2を
配した積層体をプリプレグ2を含めてハトメピン3で固
定した後、最外層に金属箔5を配して積層成形する多層
配線板の製造方法を提案している。
2. Description of the Related Art Conventionally, as shown in FIG. 4, a method for manufacturing a multilayer wiring board has a method in which a prepreg 2 is arranged between a plurality of inner layer materials 1 and 1 having a circuit 7, and these are caulked with eyelet pins 3 at required positions. There has been known a method of fixing, then prepreg 2 on both sides thereof, and metal foil 5 on the outermost layer, sandwiched by molding plates 6 and 6, and laminated molding. However, with this method, there is a problem that misalignment is likely to occur during lamination molding, molding abnormalities occur, and good products cannot be obtained with high yield,
A method for preventing this displacement has been studied, and the inventors of the present invention have also disclosed in Japanese Patent Laid-Open No. 3-129797 a laminated body in which prepregs 2 are arranged on the upper and / or lower surfaces of a plurality of inner layer materials 1, 1 as shown in FIG. A method for manufacturing a multilayer wiring board is proposed in which the prepreg 2 and the prepreg 2 are fixed by eyelet pins 3 and then the metal foil 5 is placed on the outermost layer to laminate-mold.

【0003】これらのハトメピンで固定する方法によれ
ば、積層成型後の板厚が厚い場合には、多層配線板の層
間位置精度は比較的良好に保つことができていたが、積
層成型後の板厚が薄い場合には層間位置精度のバラツキ
が大きい傾向があった。近年、積層成型後の板厚が0.
3〜1.0mmと薄い多層配線板の製造が増大するに伴
い、ハトメピンで固定する方法で得られる多層配線板の
層間位置精度のバラツキを小さくできる方法の開発が求
められている。
According to these methods of fixing with eyelet pins, the accuracy of the interlayer position of the multilayer wiring board could be kept relatively good when the plate thickness after lamination molding was thick, but after lamination molding. When the plate thickness is thin, there is a tendency that there is a large variation in the interlayer positional accuracy. In recent years, the plate thickness after lamination molding is 0.
With the increase in the production of thin multilayer wiring boards of 3 to 1.0 mm, it is required to develop a method capable of reducing the variation in the interlayer positional accuracy of the multilayer wiring board obtained by the method of fixing with eyelet pins.

【0004】[0004]

【発明が解決しようとする課題】上記の事情に鑑み、本
発明は、複数の内層材の各上面及び又は下面にプリプレ
グを配した積層体をハトメピンで固定した後、最外層に
金属箔を配して成形して得られる、成型後の板厚が0.
3〜1.0mmの多層配線板の層間位置精度のバラツキ
を小さくすることができる多層配線板の製造方法を提供
することを目的としている。
SUMMARY OF THE INVENTION In view of the above circumstances, according to the present invention, a laminated body having prepregs on the upper and / or lower surfaces of a plurality of inner layer materials is fixed with eyelet pins, and then a metal foil is disposed on the outermost layer. The plate thickness after molding obtained by molding is 0.
It is an object of the present invention to provide a method for manufacturing a multilayer wiring board capable of reducing variations in interlayer positional accuracy of the multilayer wiring board of 3 to 1.0 mm.

【0005】[0005]

【課題を解決するための手段】本発明は、複数の内層材
の各上面及び又は下面にプリプレグを配した積層体をハ
トメピンで固定した後、最外層に金属箔を配して成形し
て、成型後の板厚が0.3〜1.0mmの多層配線板を
製造する多層配線板の製造方法において、かしめ前のハ
トメピンの高さ(h)が下記式(I)を h≦b+d ───(I) (式中hはかしめ前のハトメピンの高さ、bはハトメピ
ンの鍔部の幅、dは多層配線板の成型後の板厚である)
満足することを特徴とする多層配線板の製造方法であ
る。
According to the present invention, a laminate having prepregs on the upper and / or lower surfaces of a plurality of inner layer members is fixed with eyelet pins, and then a metal foil is placed on the outermost layer to form a molded product, In the method of manufacturing a multilayer wiring board for manufacturing a multilayer wiring board having a thickness of 0.3 to 1.0 mm after molding, the height (h) of the eyelet pins before crimping is expressed by the following formula (I): h ≦ b + d ── (I) (where h is the height of the eyelet pin before crimping, b is the width of the collar portion of the eyelet pin, and d is the thickness of the multilayer wiring board after molding)
This is a method for manufacturing a multilayer wiring board, which is characterized by being satisfied.

【0006】また、ハトメピンの肉厚が0.1〜0.3
mmである多層配線板の製造方法である。
The thickness of the eyelet pin is 0.1 to 0.3.
It is a method for manufacturing a multilayer wiring board having a size of mm.

【0007】本発明に用いる内層材としてはエポキシ樹
脂、ポリイミド樹脂、弗素樹脂等の樹脂と紙、ガラス布
等の基材等からなる基板の片面または両面に銅、ニッケ
ル等の金属成分よりなる導体回路が形成されたものが使
用される。内層材の上面及び又は下面に配設されるプリ
プレグとしては、前記の内層材の基板を製造するのに使
用されたものと同一材料のプリプレグであっても、ある
いは異なる材料のプリプレグであってもよく、例えば、
エポキシ樹脂、ポリイミド樹脂、弗素樹脂等の樹脂を
紙、ガラス布等の基材に含浸、乾燥して得られるものが
使用される。また、最外層に配する金属箔については、
例えば銅箔、ニッケル箔、アルミ箔等を例示できる。
The inner layer material used in the present invention is a conductor made of a metal component such as copper or nickel on one or both sides of a substrate made of a resin such as an epoxy resin, a polyimide resin or a fluorine resin and a base material such as paper or glass cloth. What has a circuit formed is used. The prepreg disposed on the upper surface and / or the lower surface of the inner layer material may be the same material as that used for manufacturing the substrate of the inner layer material, or a prepreg of a different material. Well, for example,
A material obtained by impregnating a base material such as paper or glass cloth with a resin such as an epoxy resin, a polyimide resin, or a fluororesin and drying the resin is used. Also, for the metal foil to be placed on the outermost layer,
For example, copper foil, nickel foil, aluminum foil and the like can be exemplified.

【0008】本発明で使用するハトメピンの材質につい
ては特に限定はなく、例えば、鉄、真鍮、ステンレス等
の金属製または合成樹脂製のものを用いることができ
る。また、本発明では成形時のずれ防止のため、最外層
に配する金属箔以外の材料の積層体をハトメピンで固定
するようにしている。そして、かしめ前のハトメピンの
高さ(h)については、積層体を固定するにはかしめ後
の積層体の厚みより長いことが必須であるが、成形後の
板厚が0.3〜1.0mmと薄い多層配線板を製造する
際には、前記式(I)を満足することが本発明では重要
である。なぜならば、かしめ前のハトメピンの高さ
(h)が前記式(I)を満足せずに、ハトメピンの鍔部
の幅(b)と多層配線板の成型後の板厚(d)の和より
長い場合には、かしめたとき、または成形したときにハ
トメピンに異常な変形が生じて、その結果内層材の層間
の位置ずれが生じる可能性が高くなるからである。な
お、図2、図3にはハトメピンのかしめ前の状態の平面
図、断面図を示し、本発明でいうハトメピンの高さ
(h)、ハトメピンの鍔部の幅(b)がどの部分の長さ
かを図3に示している。
The material of the eyelet pin used in the present invention is not particularly limited, and, for example, metal such as iron, brass, stainless steel, or synthetic resin can be used. Further, in the present invention, in order to prevent misalignment at the time of molding, a laminated body made of a material other than the metal foil arranged as the outermost layer is fixed with eyelet pins. Regarding the height (h) of the eyelet pin before crimping, in order to fix the laminated body, it is essential that it is longer than the thickness of the laminated body after crimping, but the plate thickness after molding is 0.3 to 1. When manufacturing a multilayer wiring board as thin as 0 mm, it is important in the present invention to satisfy the above formula (I). This is because the height (h) of the eyelet pin before crimping does not satisfy the above formula (I), and the sum of the width (b) of the collar portion of the eyelet pin and the thickness (d) of the multilayer wiring board after molding. This is because if the length is long, abnormal deformation occurs in the eyelet pins during crimping or molding, and as a result, there is a high possibility that the inner layer material will be displaced between the layers. 2 and 3 are plan views and sectional views of the state before crimping of the eyelet pin, showing the length of the portion where the height (h) of the eyelet pin and the width (b) of the collar portion of the eyelet pin are referred to in the present invention. The fish is shown in FIG.

【0009】また、本発明で使用するハトメピンの肉厚
〔図3において(c)として示す〕については、積層体
を固定できて、かつ、最外層の金属箔に成型時にシワを
発生させないためには、0.1〜0.3mmであること
が望ましい。なぜなら、肉厚が0.1mm未満であると
積層体の固定がしにくくなり、0.3mmを越えるとハ
トメピンの突起により金属箔にシワが発生しやすくなる
からである。
Regarding the wall thickness of the eyelet pin used in the present invention (shown as (c) in FIG. 3), the laminate can be fixed, and wrinkles do not occur in the outermost metal foil during molding. Is preferably 0.1 to 0.3 mm. This is because if the wall thickness is less than 0.1 mm, it becomes difficult to fix the laminate, and if it exceeds 0.3 mm, wrinkles are likely to occur on the metal foil due to the projections of the eyelet pins.

【0010】[0010]

【作用】かしめ前のハトメピンの高さhが、ハトメピン
の鍔部の幅bと多層配線板の成型後の板厚dの和以下で
あることは、積層体をかしめたときにハトメピンが長す
ぎることにより生じるハトメピンの異常な変形を防止す
る作用をする。
The height h of the eyelet pin before crimping is not more than the sum of the width b of the collar portion of the eyelet pin and the thickness d of the multilayer wiring board after molding. That is, the eyelet pin is too long when the laminate is crimped. It acts to prevent abnormal deformation of the eyelet pin caused thereby.

【0011】また、ハトメピンの肉厚を0.1〜0.3
mmにすることは、ハトメピンの外側に配置される金属
箔に対するハトメピンの突起を低いものとするので、金
属箔に生じる成型時のシワの発生を防止する作用をす
る。
The thickness of the eyelet pin is 0.1 to 0.3.
Since the protrusion of the eyelet pin with respect to the metal foil arranged on the outer side of the eyelet pin is made low by setting it to be mm, it has an action of preventing the generation of wrinkles in the metal foil at the time of molding.

【0012】[0012]

【実施例】以下本発明を実施例を図面に基づいて説明す
る。
Embodiments of the present invention will now be described with reference to the drawings.

【0013】(実施例1)図1に示すように厚み0.1
5mmの両面銅張りガラス布基材エポキシ樹脂積層板の
両面に回路7を形成して内層材1とし、2枚の内層材
1,1の各上面及び下面に成型後の板厚が0.08mm
/枚となるプリプレグ2を合計6枚配し積層体とし、得
られた積層体の4隅部に直径3.5mmの孔を開孔し
た。次いで、材質が真鍮であり図3に示す断面形状を有
し、鍔全体の直径(a)が7.5mmであり、鍔の幅
(b)が2.5mmであり、肉厚(c)が0.25mm
であり、ハトメピンの高さ(h)が3.0mmであるハ
トメピン3を前記の開孔部に挿通してから、かしめて積
層体を固定した。次いで、最外側の両側に厚み18μm
の銅箔を金属箔5として配し、成形プレート6,6にて
挟んで、成形圧力30kg/cm2 、成形温度170℃
で90分間積層成形して、内層に回路7を有する成型後
の板厚(d)が0.8mmである6層の多層配線板を得
た。なお、この場合、h(3.0mm)<b(2.5m
m)+d(0.8mm)となり、前記の式(I)を満足
している。
Example 1 A thickness of 0.1 as shown in FIG.
A circuit 7 is formed on both surfaces of a 5 mm double-sided copper-clad glass cloth base material epoxy resin laminated board to form an inner layer material 1, and the upper and lower surfaces of the two inner layer materials 1 and 1 have a thickness of 0.08 mm after molding.
A total of 6 prepregs 2 each of which is a sheet were arranged to form a laminated body, and holes having a diameter of 3.5 mm were opened at four corners of the obtained laminated body. Next, the material is brass and has the cross-sectional shape shown in FIG. 3, the overall diameter (a) of the collar is 7.5 mm, the width (b) of the collar is 2.5 mm, and the wall thickness (c) is 0.25 mm
The eyelet pin 3 having a height (h) of the eyelet pin of 3.0 mm was inserted into the above-mentioned opening portion and then caulked to fix the laminated body. Next, thickness of 18 μm on both outermost sides
The copper foil of No. 3 is placed as the metal foil 5, sandwiched between the molding plates 6 and 6, the molding pressure is 30 kg / cm 2 , the molding temperature is 170 ° C.
Was laminated and molded for 90 minutes to obtain a 6-layer multilayer wiring board having a circuit 7 in the inner layer and having a thickness (d) of 0.8 mm after molding. In this case, h (3.0 mm) <b (2.5 m
m) + d (0.8 mm), which satisfies the above formula (I).

【0014】(実施例2)ハトメピンの肉厚(c)が
0.40mmであるハトメピンを使用したこと以外は全
て実施例1と同条件により内層に回路を有する成型後の
板厚が0.8mm(d)である6層の多層配線板を得
た。なお、この場合、h(3.0mm)<b(2.5m
m)+d(0.8mm)となり、前記の式(I)を満足
している。
(Example 2) Under the same conditions as in Example 1, except that eyelet pins having a thickness (c) of eyelet pins of 0.40 mm were used, the plate thickness after molding having a circuit as an inner layer was 0.8 mm. A 6-layer multilayer wiring board, which is (d), was obtained. In this case, h (3.0 mm) <b (2.5 m
m) + d (0.8 mm), which satisfies the above formula (I).

【0015】(比較例1)ハトメピンの高さ(h)が
4.2mmであるハトメピンを使用したこと以外は全て
実施例1と同条件により内層に回路を有する成型後の板
厚が0.8mm(d)である6層の多層配線板を得た。
なお、この場合、h(4.2mm)>b(2.5mm)
+d(0.8mm)となり、前記の式(I)は満足して
いない。
(Comparative Example 1) Under the same conditions as in Example 1, except that the eyelet pin having a height (h) of 4.2 mm was used, the plate thickness after molding having a circuit in the inner layer was 0.8 mm. A 6-layer multilayer wiring board, which is (d), was obtained.
In this case, h (4.2 mm)> b (2.5 mm)
+ D (0.8 mm), which does not satisfy the above formula (I).

【0016】実施例1と2及び比較例1で得られた6層
の多層配線板について、層間位置精度と最外層の銅箔の
シワの発生の有無を調べた、その結果を表1に示す。な
お、層間位置精度については2枚の内層材1,1に設け
た基準点のズレの程度をX線装置を用いて検出して測定
した。この層間位置精度の測定は20か所を測定し、そ
の最小値、最大値及び平均値を表1に示した。また、最
外層の銅箔のシワの発生の有無は目視で行った。
With respect to the 6-layered multilayer wiring boards obtained in Examples 1 and 2 and Comparative Example 1, the interlayer positional accuracy and the presence or absence of wrinkles in the outermost copper foil were examined, and the results are shown in Table 1. . The interlayer positional accuracy was measured by detecting the degree of deviation of the reference points provided on the two inner layer members 1 and 1 using an X-ray device. This interlayer position accuracy was measured at 20 locations, and the minimum, maximum and average values are shown in Table 1. The presence or absence of wrinkles in the outermost copper foil was visually checked.

【0017】[0017]

【表1】 [Table 1]

【0018】表1の結果から、かしめ前のハトメピンの
高さhが、ハトメピンの鍔部の幅bと多層配線板の成型
後の板厚dの和以下である実施例1と2の方が、かしめ
前のハトメピンの高さhが、ハトメピンの鍔部の幅bと
多層配線板の成型後の板厚dの和より大きい比較例1よ
り層間位置精度が良好であると確認された。
From the results shown in Table 1, in Examples 1 and 2 in which the height h of the eyelet pins before crimping was less than the sum of the width b of the collar portion of the eyelet pins and the thickness d of the multilayer wiring board after molding. It was confirmed that the interlayer position accuracy was better than in Comparative Example 1 in which the height h of the eyelet pin before crimping was larger than the sum of the width b of the collar portion of the eyelet pin and the thickness d of the multilayer wiring board after molding.

【0019】また、肉厚が0.40mmと厚いハトメピ
ンを用いた実施例2では銅箔に成型時のシワが発生して
おり、シワ発生の防止にはハトメピンの肉厚を0.3m
m以下であることが有効であることも確認された。
Further, in Example 2 in which the eyelet pin having a large thickness of 0.40 mm was used, the copper foil had wrinkles at the time of molding. To prevent the wrinkles from occurring, the thickness of the eyelet pin was 0.3 m.
It was also confirmed that m or less was effective.

【0020】[0020]

【発明の効果】本発明に係る製造方法によれば、複数の
内層材の各上面及び又は下面にプリプレグを配した積層
体をハトメピンで固定した後、最外層に金属箔を配して
成形して得られる、成型後の板厚が0.3〜1.0mm
の多層配線板の層間位置精度のバラツキを小さくするこ
とができる。
According to the manufacturing method of the present invention, a laminate having prepregs on the respective upper and / or lower surfaces of a plurality of inner layer materials is fixed by eyelet pins, and then a metal foil is disposed on the outermost layer to form the laminate. The plate thickness after molding is 0.3 to 1.0 mm
It is possible to reduce the variation in the interlayer positional accuracy of the multilayer wiring board.

【0021】また、請求項2に係る製造方法によれば、
金属箔にシワが発生するのを防止できるようになる。
According to the manufacturing method of the second aspect,
Wrinkles can be prevented from occurring on the metal foil.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に係る断面図である。FIG. 1 is a sectional view according to an embodiment of the present invention.

【図2】本発明の実施例に係る、ハトメピンの平面図で
ある。
FIG. 2 is a plan view of an eyelet pin according to an embodiment of the present invention.

【図3】本発明の実施例に係る、ハトメピンの断面図で
ある。
FIG. 3 is a sectional view of an eyelet pin according to an embodiment of the present invention.

【図4】従来例に係る断面図である。FIG. 4 is a sectional view according to a conventional example.

【符号の説明】[Explanation of symbols]

1 内層材 2 プリプレグ 3 ハトメピン 5 金属箔 6 成形プレート 7 回路 1 Inner layer material 2 Prepreg 3 Eyelet pin 5 Metal foil 6 Molding plate 7 Circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の内層材の各上面及び又は下面にプ
リプレグを配した積層体をハトメピンで固定した後、最
外層に金属箔を配して成形して、成型後の板厚が0.3
〜1.0mmの多層配線板を製造する多層配線板の製造
方法において、かしめ前のハトメピンの高さ(h)が下
記式(I)を h≦b+d ───(I) (式中hはかしめ前のハトメピンの高さ、bはハトメピ
ンの鍔部の幅、dは多層配線板の成型後の板厚である)
満足することを特徴とする多層配線板の製造方法。
1. A laminate in which a prepreg is arranged on each upper surface and / or lower surface of a plurality of inner layer materials is fixed by eyelet pins, and then a metal foil is arranged on the outermost layer for molding, so that the plate thickness after molding is 0. Three
In the method for manufacturing a multilayer wiring board for manufacturing a multilayer wiring board having a thickness of up to 1.0 mm, the height (h) of the eyelet pins before crimping is expressed by the following formula (I): h ≦ b + d ─── (I) (where h is (The height of the eyelet pin before crimping, b is the width of the collar portion of the eyelet pin, and d is the thickness of the multilayer wiring board after molding.)
A method for manufacturing a multilayer wiring board, which is satisfied.
【請求項2】 ハトメピンの肉厚が0.1〜0.3mm
である請求項1記載の多層配線板の製造方法。
2. The thickness of the eyelet pin is 0.1 to 0.3 mm.
The method for manufacturing a multilayer wiring board according to claim 1, wherein
JP18459993A 1993-07-27 1993-07-27 Method for manufacturing multilayer wiring board Expired - Fee Related JP3237324B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18459993A JP3237324B2 (en) 1993-07-27 1993-07-27 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18459993A JP3237324B2 (en) 1993-07-27 1993-07-27 Method for manufacturing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH0745953A true JPH0745953A (en) 1995-02-14
JP3237324B2 JP3237324B2 (en) 2001-12-10

Family

ID=16156034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18459993A Expired - Fee Related JP3237324B2 (en) 1993-07-27 1993-07-27 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3237324B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020023888A (en) * 2001-12-27 2002-03-29 박종선 Multilayer printed circuit board and manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020023888A (en) * 2001-12-27 2002-03-29 박종선 Multilayer printed circuit board and manufacturing method

Also Published As

Publication number Publication date
JP3237324B2 (en) 2001-12-10

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