JPH0745630A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a third semiconductor layer of a semiconductor device at a high speed without increasing the number of processes. CONSTITUTION:In a semiconductor device manufacturing method by which a semiconductor device having a P-type base layer 32 an N-type collector layer 31 and N-type emitter layers 35 and 36 in the layer 32 can be manufactured, the emitter layers 35 and 36 are formed by respectively introducing two kinds of impurities of a first conductivity into the base layer 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art When a reverse bias is applied to the emitter / base junction of a bipolar transistor, the electric field causes carriers to become hot and trapped in an oxide film near the junction, degrading the current amplification factor (h _FE ) of the bipolar transistor. . To alleviate this phenomenon, it is a good idea to weaken the electric field at the emitter-base junction. This measure is disclosed in JP-A-2-283032, JP-A-2-148849,
JP-A-3-149833, JP-A-3-225950
JP-A-4-75348, JP-A-4-159721
No. These are manufactured as shown in FIG. 2 (A), (B) or FIG. 3 (A), (B).

The conventional example shown in FIGS. 2A and 2B is manufactured as follows. First, an N-type collector layer 1 is formed on the surface of a substrate (not shown), a P-type base layer 2 is further formed on the surface of the collector layer 1, and then an insulating film 3 is formed.
Next, an emitter window is opened in this insulating film 3. Next, using the insulating film 3 as a mask, the N ⁻ type emitter layer 4 is formed.
Then, a thin oxide film 5 is formed on the exposed surface of the emitter layer 4 (see FIG. 2A). Next, a side wall (side wall) 6 made of polycrystalline silicon is formed on the side wall of the opening. Here, when the side wall 6 is formed, part of the oxide film 5 is etched, and a window for forming the N ⁺ emitter is opened. Subsequently, an N ⁺ -type polycrystalline silicon layer 7 is formed and diffused to form an N ⁺ -type emitter layer 8
Are formed (see FIG. 2B).

The conventional example shown in FIGS. 3A and 3B is manufactured as follows. First, an N type collector layer 1 is formed on the surface of a substrate (not shown), and a P type base layer 2 is further formed on the surface of the collector layer 1. Then, N the resist 11 as a mask ^- -type emitter layer 4 (FIG. 3 (A)
reference). Subsequently, the N ⁺ type emitter layer 8 is formed using the resist 12 as a mask (see FIG. 3B).

[0005]

[Problems to be Solved by the Invention]
In the conventional example, since the N ⁻ type emitter layer 4 is formed around the N ⁺ type emitter layer 8, the electric field at the emitter-base reverse bias is weakened and the deterioration of h _FE is alleviated. However, in order to obtain such a structure, the manufacturing method shown in FIG. 2 requires a step of forming the N ⁻ type emitter layer 4 and a step of forming the side wall 6, which increases the number of steps. Further, since the oxide film 5 is thin, the capacitance between the emitter and the base increases, which hinders the speedup.

In the manufacturing method of FIG. 3, the N ⁻ -type emitter layer 4 and the N ⁺ -type emitter layer 8 are formed using the resists 11 and 12 as masks, respectively. However, there is a problem that the area becomes large and the emitter size cannot be reduced, which hinders speeding up.

The present invention has been made in consideration of such circumstances, and provides a method of manufacturing a semiconductor device capable of forming a third semiconductor layer of the first conductivity type without increasing the number of steps and capable of speeding up. The purpose is to do.

[0008]

According to the present invention, a second conductivity type second semiconductor layer is formed on a first conductivity type first semiconductor layer,
A method of manufacturing a semiconductor device, wherein a third semiconductor layer of the first conductivity type is formed on the second semiconductor layer, wherein the third semiconductor layer introduces two kinds of impurities of the first conductivity type into the second semiconductor layer. It is a method of manufacturing a semiconductor device, which is characterized in that the semiconductor device is formed.

In the present invention, as the semiconductor device,
There is a bipolar transistor in which the first semiconductor layer is a collector, the second semiconductor layer is a base, and the third semiconductor layer is an emitter.

In the present invention, the two types of first conductivity type impurities forming the third semiconductor layer include impurities having different diffusion coefficients. Here, examples of the two types of impurities of the first conductivity type include arsenic and phosphorus, or boron and aluminum.

[0011]

According to the present invention, the third semiconductor layer of the first conductivity type can be formed without increasing the number of steps, and at the same time, high speed can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a bipolar transistor according to an embodiment of the present invention will be described below in the order of steps with reference to FIGS.
Will be described with reference to. (1) First, an N-type collector layer is formed on the surface of a substrate (not shown).
After forming 31, the P-type base layer 32 was formed on the surface of the collector layer 31 (see FIG. 1A). Next, after forming an insulating film 33 on the entire surface, this insulating film 33 was selectively etched to form an emitter window 33a. Furthermore, thickness 100 to 5
After forming the 00 nm polycrystalline silicon layer 34, arsenic (A
s) is an acceleration voltage of 50 to 150 KeV, a dose amount of 1 × 10
Ion implantation of ¹⁵ to 1 × 10 ¹⁶ cm ⁻² is performed, phosphorus is continuously added at 50 to 150 KeV, and dose is 1 × 10 ¹³ to 1 × 10.
Ion implantation was performed at ¹⁶ cm ^-2 (see FIG. 1B).

(2) Next, after etching the polycrystalline silicon layer 34 into which As and phosphorus have been ion-implanted, 900 to 100
Annealing treatment was performed at 0 ° C. for 10 to 60 minutes. As a result, impurities are diffused from the polycrystalline silicon layer 34 to the P type base layer 32, and a shallow N ⁺ type emitter layer 35 and a deep N ⁻ type emitter layer 36 are formed (see FIG. 1C). ). The emitter layer 35 is formed of As having a small diffusion coefficient, and the other emitter layer 36 is formed of phosphorus having a large diffusion coefficient.

According to the above-mentioned embodiment, two different diffusion coefficients are used.
Since the shallow N ⁺ -type emitter layer 35 and the deep N ⁻ -type emitter layer 36 are simultaneously formed by the kinds of impurities (As, P), h _FE deterioration at the time of reverse bias of the emitter-base is prevented without increasing the number of processes. A small emitter layer can be formed. Further, the N ⁺ type emitter layer 35 and the deep N ⁻ type emitter layer 36
Can be simultaneously formed by diffusion from the polycrystalline silicon layer 34, so that the emitter size can be reduced and an emitter layer capable of speeding up can be formed.

In the above embodiment, the n-type conductivity type impurities, that is, As and P are used as the two types of impurities, but the present invention is not limited to this, and the p-type conductivity type impurity, ie, boron. And Al, or other two kinds of impurities having different diffusion coefficients can be used.
Further, in the above-mentioned embodiment, the bipolar and the transistor are described, but the present invention is not limited to this and may be applied to other semiconductor devices.

[0016]

As described above in detail, according to the present invention, the first conductive type third semiconductor layer such as the emitter layer can be formed without increasing the number of steps, and the low concentration and high concentration third semiconductor layers can be formed. It is possible to provide a method for manufacturing a semiconductor device such as a bipolar transistor which can form a fine layer and can alleviate h _FE deterioration at the time of reverse bias of an emitter / base, and can further speed up.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a bipolar transistor according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a conventional bipolar transistor in the order of steps.

3A to 3D are cross-sectional views showing another conventional method for manufacturing a bipolar transistor in the order of steps.

[Explanation of symbols]

31 ... N ^- type collector layer, 32 ... P type base layer, 33 ...
Insulating film, 33a ... Emitter window, 34 ... Polycrystalline silicon layer, 35 ... N ⁺ type emitter layer, 36 ... N ^-- type emitter layer.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a second conductivity type second semiconductor layer is formed on a first conductivity type first semiconductor layer, and a first conductivity type third semiconductor layer is formed on the second semiconductor layer. In the method, the third semiconductor layer is formed by introducing two kinds of impurities of the first conductivity type into the second semiconductor layer. 2. The first semiconductor layer is a collector, and the second semiconductor layer is a collector.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is a base and the third semiconductor layer is an emitter. 3. The method of manufacturing a semiconductor device according to claim 1, wherein two types of impurities of the first conductivity type forming the third semiconductor layer have different diffusion coefficients. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the two types of first conductivity type impurities forming the third semiconductor layer are arsenic and phosphorus, or boron and aluminum. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the third semiconductor layer is simultaneously formed by diffusing two kinds of impurities from polycrystalline silicon.