JPH0744379A - Microprogram controller - Google Patents

Abstract

PURPOSE:To prevent the throughput of a firmware from being lowered by suppressing increase in the number of clock steps even when correctable one-bit errors are frequently generated in a microinstruction from a control memory. CONSTITUTION:This device is provided with a first microinstruction storage means 2, ECC check/correction circuit 32 for a field to instruct the control memory address of the next cycle, ECC check/correction circuit 31 for fields excepting for the field to instruct the next cycle control memory address, second microinstruction storage means 4 for holding the outputs of circuits 31 and 32, microinstruction selecting means 5 for selecting either of means 2 and 4, and microinstruction execution suppress signal generating means 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram controller for correcting errors in control memory.

[0002]

2. Description of the Related Art Information stored in a RAM is inverted due to radiation such as α rays generated in access to a control memory formed of a random access memory (RAM) as a memory element, but it is necessary to rewrite the information. For example, an error correction function using a 1-bit error correction 2-bit error detection code (hereinafter referred to as ECC) is adopted as a measure against so-called soft error that normally operates. In this error detection and correction by ECC, if an error of 2 bits or more occurs, the error cannot be corrected, but when the 1-bit error occurs, the error is automatically corrected and the operation can be continued normally.

As a measure for further improving the reliability, Japanese Patent Laid-Open No. 58-215798 discloses the following method.
That is, as a measure for improving reliability, in order to reduce the probability of occurrence of an uncorrectable failure called a 2-bit error, 1
A method of rewriting the corrected data in the control memory when a correctable error called a bit error occurs is shown.

[0004]

SUMMARY OF THE INVENTION In such a system,
If a correctable 1-bit error occurs frequently, normal operation can be continued, but the number of clock steps of the firmware increases, and the processing capacity of the device is reduced.

[0005]

An apparatus according to the present invention comprises a control memory for storing a microprogram composed of a plurality of microinstructions, a first microinstruction storing means for storing microinstructions from the control memory, and A first ECC check correction for detecting and correcting a 1-bit error in the content of the field indicating the control storage address of the next machine cycle of the micro-instruction stored in the first micro-instruction storing means and detecting a 2-bit error. A circuit and a 1-bit error in the contents of fields other than the field indicating the control storage address of the machine cycle following the micro-instruction stored in the first micro-instruction storing means are detected and corrected to detect a 2-bit error. A second ECC check correction circuit, the first ECC check correction circuit and the second E A second micro-instruction storing means for storing a microinstruction corrected by C check and correction circuit,
Means for generating a non-execution signal for inhibiting execution of a microinstruction when the first ECC check correction circuit detects the first 1-bit error, and the first ECC check correction circuit first 1-bit error For executing the microinstruction stored in the second microinstruction storing means from the time of detecting at least one of the interrupt request signal, the firmware processing start request signal, and the interrupt processing end signal. To the first E
Microinstruction selecting means for selecting to execute the microinstruction stored in the second microinstruction storing means for one machine cycle after detecting one bit error in the CC check correction circuit.

[0006]

An embodiment of the present invention will now be described in detail with reference to the drawings. Referring to FIG. 1, an embodiment of the present invention includes a control memory 1 for storing a microprogram composed of a plurality of microinstructions, and a register or a buffer for storing the microinstructions read from the control memory 1. 1 of the contents of the first microinstruction storage means 2 and the next address field indicating the control storage storage position of the microinstruction read in the next cycle of the microinstruction stored in the first microinstruction storage means 2 ECC check correction circuit 3 for performing ECC check and error correction for bit error detection and correction and 2-bit error detection
2 and ECC for detecting and correcting 1-bit error and 2-bit error in the contents of fields other than the next address field stored in the first microinstruction storing means 2.
An ECC check correction circuit 31 for performing checking and error correction, and these ECC check correction circuits 31 and 32
The second microinstruction storing means 4 stores the microinstruction in which the 1-bit error is corrected in the first microinstruction storing means 2 without rewriting.

The microinstruction execution inhibiting signal generating means 6, which is one of the features of the embodiment of the present invention, is the ECC in one firmware processing unit or until interrupted when an interrupt occurs in the middle. Check correction circuit 32
When a signal indicating a 1-bit error in the contents of the next address field is given from the or from the ECC check correction circuit 31 a signal indicating a first 1-bit error in the contents of the fields other than the next address field is given. Non-execution to suppress instruction execution (NOEX)
Generate a signal. The microinstruction selecting means 5, which is another feature of the embodiment of the present invention, selects the microinstruction from the first microinstruction storing means (MIR1) 2 in the normal state, and the ECC check correction circuit. 32 when a signal indicating a 1-bit error in the content of the next address field is given for one machine cycle or ECC
An interrupt request signal, a firmware processing start request signal, an interrupt processing end signal, or the contents of the next address field from the circuit 32 after the check correction circuit 31 gives a signal indicating a 1-bit error of the contents of fields other than the next address field. Second microinstruction storing means (MIR2) 4 until a signal indicating a 1-bit error of
Select a microinstruction from.

In this embodiment, the non-execution (NOEX) signal generated by the microinstruction execution suppression signal generating means 6 suppresses the execution of the microinstruction for one machine cycle, and the next machine cycle restarts. The microinstruction which is error-corrected and stored in the second microinstruction storing means 4 is selected by the microinstruction selecting means 5 and executed. When the ECC check correction circuit 32 detects a 1-bit error in the content of the next address field, the first
The content of the next address field indicating the control storage address of the next machine cycle of the microinstruction storing means 2 is guaranteed because it is corrected. Another feature of the embodiment of the present invention is that the control memory address generating means 7 selects the contents of the corrected next address field to generate an address for the control memory 1. By the address generation by the control memory address generating means 7, the prefetching of the control memory 1 as compared with the second micro instruction storing means 4 can be performed. Therefore, it is possible to suppress the increase in the number of clock steps when the same 1-bit error occurs after the second time.
The ECC check error reporting means 8, which is another feature of the embodiment of the present invention, is the ECC in the circuit 31 or 32.
An error occurrence due to the check is notified to a host device (not shown). Even if the error notified by the ECC check error reporting means 8 is a correctable error, by issuing a warning to the upper device, it is possible to contribute to the improvement of the reliability of the device.

Next, the detailed structure of the microinstruction selecting means 5, the microinstruction execution inhibiting signal generating means 6 and the control memory address generating means 7 in the embodiment of the present invention will be described in detail with reference to FIGS. Explained.

Referring to FIG. 4, the micro-instruction selecting means 5 shown in FIG. 1 has a D-flip-flop (hereinafter D-FF) 51 named SEL1 and 1 bit of the content of the next address field from the circuit 32. A D-flip-flop (hereinafter D-FF) 52 named SEL2 which is set by an error detection signal, and these D-FFs
An OR gate 53 that ORs the outputs of 51 and 52,
A selector 54, D-FF 51 for selecting either one of the microinstruction from the first microinstruction storing means 2 or the microinstruction from the second microinstruction storing means 3 according to the selection SEL signal output from the OR gate 53. The OR gate 54 for holding the output of the OR gate, and the D-FF 51 is continuously set by the output of the OR gate 54,
An interrupt request signal given from the outside to cancel this set,
An AND gate 55 is provided for performing either the firmware processing start request signal, the interrupt request signal, or the setting signal from the D-FF 52.

The negative output Q from the D-FF 51 is given to the micro-instruction execution inhibiting signal generating means 6 and the circuit 31.
In response to the generation of the 1-bit error signal for the second time and thereafter, the generation of the non-execution (NOEX) signal is stopped.

The microinstruction execution inhibiting signal generating means 6 is
An AND gate 61 which takes the logical product of the negative output Q from the D-FF 51 of the microinstruction selecting means 5 and the 1-bit error signal of the contents of fields other than the next address field from the circuit 31, and the output of the AND gate 61. , An ECC gate 32 for ORing a 1-bit error signal of the contents of the next address field from the ECC check-correction circuit 32 and a signal indicating another non-execution (NOEX) factor.

The D-FF 52 outputs an output Q signal for one machine cycle from the occurrence of a 1-bit error in the content of the next address field from the circuit 32. The output Q signal of the D-FF 52 is given to the control storage address generation means 7 as a selection instruction signal.

The control storage address generating means 7 is the DF
A selector 71 for selecting either the content of the next address field of the first micro instruction storage means 2 or the content of the next address field of the second micro instruction storage means 4 by the output Q signal of F52, and this selector 71.
The selector 72 is provided for selecting one of the output of the address and the interrupt address by the interrupt request signal.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.
And it demonstrates in detail with reference to FIG.

When a 1-bit error occurs in the contents of fields other than the next address field in the circuit 31, and the control memory address generating means 7 selects the contents of the next address field from the first microinstruction storing means 2.
Preemptive reading of the control memory 1 as compared with the second micro instruction storage means 4 can be performed. An example of the operation that enables the pre-reading will be described in detail with reference to FIG.

With reference to FIGS. 1 and 2, the microinstruction A2 read from the position of the control memory 1 designated by the address a from the control memory address generating means 7 is read by the first microinstruction storing means 2 at the timing T2. Stored in.
When the first 1-bit error of the contents of the fields other than the next address field of the microinstruction A2 is detected by the circuit 31, it is corrected and the microinstruction execution inhibition signal generating means 6 sends a non-execution (NOEX) signal to one machine. Occurs during the cycle. While the non-execution signal is being generated, execution of the micro instruction is suppressed. Referring to FIGS. 1, 2 and 4, in response to the detection of the first 1-bit error in this circuit 31, a D-FF 51 called SEL1 is set. The micro-instruction selecting means 5 during the setting selects the micro-instruction from the second micro-instruction storing means 4.
While the D-FF 51 called SEL1 is being set, the first micro instruction storing means 2 is set at timings T4 and T5.
Even if the second and third 1-bit errors of the contents of the fields other than the next address field of the microinstructions A4 and A5 stored in the circuit 31 occur in the AND circuit 61, the AND gate 61 of the microinstruction execution inhibiting signal generating means 6
Does not generate a signal, so does not generate a non-execution (NOEX) signal. The micro-instruction selecting means 5 generates a 1-bit error in the circuit 31 after the second time even at timings T4 and T5.
, The output of the D-FF 51 called SEL1 is input through the OR gate 54 and the AND gate 55, so that the D-FF 51 continues to be set. This D
-The selector 54 of the microinstruction selection means 5 during the setting of the FF 51 can select the microinstruction from the second microinstruction storage means 4 in which the 1-bit error has been corrected, so that prefetching is possible and the number of clock steps can be increased. Can be suppressed.

The D-FF 51 is reset in response to the supply of the interrupt request signal to the AND gate 55. After this reset, the selector 54 of the microinstruction selecting means 5 selects the microinstruction from the first microinstruction storing means 5.

The operation when the ECC check correction circuit 32 causes a 1-bit error in the content of the next address field will be described in detail with reference to FIG.

Referring to FIGS. 1, 3 and 4, the microinstruction A2 is stored in the first microinstruction storage means 2 from the position of the control storage 7 indicated by the address a2 from the control storage address generation means 7. It There is a 1-bit error in the content of the next address field of the microinstruction A2 stored in the first microinstruction storing means 2, and the ECC
The 1-bit error is detected and corrected by the check correction circuit 32. The 1-bit error detection signal from this circuit 32 outputs 1 to the D-FF 52 called SEL2.
Set only during machine cycles. By setting the D-FF 52, the selector 54 of the microinstruction selecting means 5
Selects the corrected microinstruction A2 stored in the second microinstruction storing means 4 and supplies it to the microinstruction register (not shown). Since the contents supplied to the microinstruction register at the timing T2 are contents that cannot be executed, the error signal from this circuit 32 is output as a non-execution (NOEX) signal through the OR gate 62 of the microinstruction execution suppression signal generation means 6. To be done. This output prevents inappropriate execution of microinstructions.

The contents of the corrected next address field of the microinstruction A2 corrected and stored in the second microinstruction storing means 4 are given to the control memory address generating means 7 and the control memory 1 of the next machine cycle. Is used as the address a3.

At timing T5, the second 1-bit error corresponding to the first micro-instruction A2 in the micro-instruction A4 stored in the first micro-instruction storing means 2 is detected by the circuit 3
It is assumed that it is detected in 2. This 1-bit error is caused by the circuit 32
It is stored in the second microinstruction storage means 4 corrected by. The 1-bit error detection signal from the circuit 32 is output as a non-execution (NOEX) signal via the OR gate 62 of the micro instruction execution inhibition generation means 6. Due to this non-execution signal, the inappropriate microinstruction stored in the microinstruction register (not shown) at timing T5 is not executed.

[0023]

According to the present invention, even if a correctable 1-bit error frequently occurs in microinstructions read from the control memory, if the 1-bit error is not in the control memory address designating field of the next cycle, the number of clock steps is increased. There is an effect that it is possible to suppress the increase of the firmware, and to prevent the deterioration of the processing capability of the firmware.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation when a 1-bit error is detected by a circuit 31 in one embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation when a 1-bit error is detected by the circuit 32 in the embodiment of the present invention.

FIG. 4 is a diagram showing a detailed configuration of microinstruction selection means 5, microinstruction execution suppression signal generation means 6, and control storage address generation means 7 in the embodiment shown in FIG.

[Explanation of symbols]

1 Control Memory 2 First Microinstruction Storage Means 31 ECC Check Correction Circuit for Field Contents Excluding Next Address Field of Microinstruction 32 ECC Check Correction Circuit for Contents of Next Address Field of Microinstruction 4 Second Microinstruction Storage Means 5 microinstruction selection means 6 microinstruction execution suppression signal generation means 7 control memory address generation means 8 ECC check error reporting means

Claims (3)

[Claims] 1. A control storage means for storing a microprogram composed of a plurality of microinstructions, a first microinstruction storage means for storing a microinstruction from the control storage means, and a first microinstruction storage means. Detects and corrects a 1-bit error in the contents of fields other than the field indicating the control storage address of the next machine cycle of the stored microinstruction, and detects a 2-bit error E
CC check / correction means, second microinstruction storage means for storing microinstructions from the ECC check / correction means, interrupt request signal, firmware processing start from the first 1-bit error detection by the ECC check / correction means A microinstruction selection means for selecting to execute the microinstruction stored in the second microinstruction storage means until at least one of a request signal and an interrupt processing end signal is supplied; and the ECC check correction means. And a means for generating a non-execution signal for suppressing execution of a microinstruction when the first 1-bit error is detected. 2. A control storage means for storing a micro program composed of a plurality of micro instructions, a first micro instruction storage means for storing a micro instruction from the control storage means, and a first micro instruction storage means. An ECC check correction means for detecting and correcting a 1-bit error in the content of the field indicating the control storage address of the next machine cycle of the stored microinstruction, and for detecting a 2-bit error, and a micro check from this ECC check correction means. Second microinstruction storing means for storing an instruction, and a microselection means for executing the microinstruction stored in the second microinstruction storing means in response to detection of a 1-bit error by the ECC check correcting means. 1-bit error detected by the instruction selection means and the ECC check correction means Microprogram control apparatus characterized by comprising a means for generating a non-execution signal for inhibiting the execution of the microinstruction can. 3. A control storage means for storing a micro program composed of a plurality of micro instructions, a micro instruction storage means for storing a micro instruction from the control storage means, and a micro instruction stored in the micro instruction storage means. The first E for detecting and correcting a 1-bit error in the contents of fields other than the field indicating the control storage address of the next machine cycle and detecting a 2-bit error
Second, a CC check correction means and a second bit error detection means for detecting and correcting a 1-bit error in the content of the field indicating the control storage address of the next machine cycle of the micro-instruction stored in the micro-instruction storage means. Error check signal from the first ECC check correction unit and at least one of the check error signal from the second ECC check correction unit. A microprogram controller comprising: reporting means.