JPH0744127A - Plasma display panel - Google Patents

Abstract

PURPOSE:To obtain accurate display gradations and to improve the display quality of a gradation display by varying the level of maintaining pulses according to a display rate. CONSTITUTION:The value from a high voltage generating circuit 30 to a high voltage control circuit part 29 is different between an address period and a trickle discharge period. An external high voltage VS is supplied as it is in the address period, but in the trickle discharge period, a variable high voltage VS+alpha which is adjusted according to the current display rate of the display data is supplied. Therefore, the level of the maintaining pulses VS in the trickle discharge period varies with the display rate. Further, the luminance of a screen varies in proportion to the level of the maintaining pulses VS, so the level of the adjusting voltage alpha (data stored in a data converting ROM 32) is optimized to display a high-gradation display part and a low-gradation display part with correct lightness even in case of, for example, a 256-gradation or more gradation display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (hereinafter, abbreviated as "PDP"), and in particular, an AC (AC) driven by separating one driving cycle into an address period and a sustain discharge period. ) Type plasma display panel improvement technology.

Since the PDP has a small depth and can realize a large screen, it is used for a display device such as a computer and a television. For example, it can be used for a high definition display such as a high definition, and 256 gradations. It is required to have a high gradation property of a degree or more.

[0003]

2. Description of the Related Art FIG. 5 is a schematic panel plan view of an AC PDP, and FIG. 6 is a schematic sectional view of one display dot (also referred to as a discharge cell). This PDP has a so-called three-electrode / surface-discharge type structure. Reference numerals 1 and 2 are two glass substrates laminated with a minute gap. Back glass substrate 1
Is an electrode Y for each display line laid in the horizontal direction of the screen.
_i (also referred to as a Y electrode; i is 1 to n) and an electrode X (also referred to as an X electrode) common to all display lines laid parallel to the electrode Y _i are wrapped in a dielectric layer 3. A MgO (magnesium oxide) film 4 is provided as a protective film on the surface of the dielectric layer 3. Further, the front glass substrate 2 is provided with an electrode A _j (also referred to as an address electrode; j is 1 to m) in a direction intersecting with the electrode Y _i (and the electrode X) (that is, the vertical direction of the screen). The phosphor 5 attached to the lower surface of the electrode A _j is partitioned by a wall (barrier) 6. A space (hereinafter referred to as “discharge space”) 7 defined by the wall 6 forms one display dot (display cell), and a phosphor of three adjacent dots (each having a red, green, or blue emission characteristic). Color display is performed by photosynthesis.
Various discharge phenomena, that is, selective discharge (also referred to as address discharge) 8 and sustain discharge 9 can be freely generated inside the discharge space 7 by controlling the potential difference between the electrode Y _i , the electrode X, or the electrode A _j. You can

FIG. 7 is a schematic overall configuration diagram of a PDP including a drive system. Reference numeral 10 is a panel unit having the configuration shown in FIGS. 5 and 6, 11 is an external supply signal (display data DATA,
Dot clock CLOCK, vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, etc.) and power supply voltage,
Control circuit for generating various internal signals and internal power supply voltage necessary for display, 12 an address driver for driving the address electrodes from A ₁ to A _m, 13 from Y ₁ to Y _n Y
Y driver for driving the electrode, 14 is X for driving the X electrode
Is a driver.

[0005] The AC type PDP is a device for sustaining a discharge by alternately applying a pulse-shaped voltage waveform to two sustain electrodes (Y electrode and X electrode) to perform light emission display. One discharge ends in about 1 μs to several μs immediately after the pulse application, but the positive ions generated by the discharge are
Electrons, which are accumulated on the surface of the dielectric layer 3 on the electrode to which the negative voltage is applied, are also accumulated on the surface of the dielectric layer 3 on the electrode to which the positive voltage is applied. It

Therefore, after a high voltage pulse (hereinafter referred to as "writing pulse Vw") is first discharged to generate wall charges, a pulse having a lower voltage than the previous pulse (hereinafter referred to as "sustain pulse or sustain discharge") having different polarities. Pulse Vs ”), new wall charges are superimposed on the previously accumulated wall charges, the voltage for the discharge space increases, and the discharge is started beyond the threshold of the discharge voltage.

That is, the cell in which the write discharge is performed once to generate the wall charge is characterized by sustaining the discharge by applying the sustain pulse alternately in the opposite polarity, which is a memory effect, or It is called the memory function. Generally, the AC type PDP performs display by utilizing this memory effect. AC type PDPs include a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes, and a three-electrode type that performs address discharge by adding a third electrode. In the color PDP for performing the above, a three-electrode structure is generally used for the purpose of avoiding a decrease in the life of the phosphor. In the color PDP, ultraviolet rays generated by discharge are used to excite the fluorescent substance in the display cell, but this fluorescent substance has a drawback that it is weak against impact of ions simultaneously generated by the discharge. Since the two-electrode type has a structure in which the phosphor directly hits the ions, the life of the phosphor is short.

FIG. 8 is a drive waveform diagram of the PDP shown in FIGS. 5 and 6, and is a waveform for one subframe (also referred to as subfield) period in the so-called “address / sustain discharge period separated type / self-erasing address system”. is there. In this driving method, one sub-frame period is divided into an address period including a full write period and a sustain discharge period (also called a sustain period). Hereinafter, such a period-separated driving method is referred to as an "address / sustain discharge separated method".

Operation in Address Period In this period, first, 0 potential (GND level) is applied to all Y electrodes, and at the same time, pulsed high voltage (write pulse Vw) is applied to X electrodes to discharge all cells. After resetting the display data, the potential of the Y electrode and X
The potentials of the electrodes are adjusted to the same level (Vs) to cause all cells to perform sustain discharge.

Then, the cell is turned on / off according to the display data.
In order to turn off, the address discharge is performed line-sequentially. First, the GND-level address pulse is applied to the Y electrode, and at the same time, the address pulse of the voltage Va is applied to the address electrode corresponding to the cell in which the sustain discharge does not occur (that is, the non-lighted cell). As a result, the self-erasing discharge of the non-lighted cells is performed, and the writing (address) of the selected display line is executed.

Thereafter, the same operation is sequentially performed on the other display lines, and new display data is written on all the display lines. Operation during Sustain Discharge Period During this period, sustain pulse (also referred to as sustain pulse) Vs is alternately applied to the Y electrode and the X electrode at a predetermined cycle to generate sustain discharge between both electrodes.

The brightness of the screen is determined by the length of the sustain discharge period, that is, the number of sustain pulses Vs. That is, increasing the number of sustain discharge pulses Vs increases the brightness,
If it is reduced, the brightness will decrease. FIG. 9 is a conceptual diagram of the present drive system when _one frame is divided into _four subframes SF _{1 to} SF ₄ .

The lengths Ta ₁ to Ta ₄ of the address period of all the subframes are the same, but the length T of the sustain discharge period is T.
s _{1 to} Ts ₄ are different. First subframe SF
_When the length Ts ₁ of the sustain discharge period of ₁ is A, the length Ts ₂ of the sustain discharge period of the _second subframe SF ₂ is A × 2.
¹ fold, the third subframe SF length Ts ₃ of the sustain discharge period of ₃ A × 2 ² times the length Ts ₄ of the fourth sustain discharge period of the sub-frame SF ₄ is turned A × 2 ³ times ing. That is, assuming that the number of subframes is N, the lengths Ts ₁ to Ts ₄ of the sustain discharge periods of the first to Nth subframes.
Is A × 2 ⁰ , A × 2 ¹ , A × 2 ² , ..., A × 2 ^N-1
Becomes

[0014] Therefore, since the period of the sustain discharge pulse Vs is the same in all subframes, number 2 ⁰ times the sustain pulse Vs of each subframe, 2 ^1-fold, 2
^2-fold, ..., it becomes successively more and 2 ^N-1 times, by selecting the subframes to be illuminated becomes easy to display a 2 ^N gradation. Note that FIG. 10 is an example of another "address / sustain discharge separation method", which is a drive method called "address / sustain discharge separation type / write address method".

One sub-frame is divided into an address period and a sustain discharge period as in the above-described driving method, but a wide erase pulse of voltage Ve is applied at the beginning of the address period to perform full erase. Is different.

[0016]

By the way, in the surface discharge type PDP, even if the number of sustain pulses is the same due to the influence of the electrode resistance of the panel, as shown in FIG. 11, there is a problem that the brightness changes depending on the display rate. is there. In FIG. 11, the vertical axis represents the luminance and the horizontal axis represents the display ratio (100%: all cell lighting, 0%:
All cells are turned off), the broken line is an ideal characteristic with no brightness change, and the solid line is an actual characteristic of each of the subframes SF _{1 to} SF ₄ . Increased number of lit cells (increased display rate)
As the brightness decreases.

Such a problem is caused by a single gradation display or 1
If it is a gradation display of about 6 gradations, it is not so conspicuous, and it is not a problem in practical use. However, if it is 256 gradations or more, for example, depending on the screen pattern,
The brightness of the high gradation display portion and the brightness of the low gradation display portion may be reversed, and there is a problem that the display quality is greatly impaired. [Object] Therefore, an object of the present invention is to improve the display quality in a gradation display of 256 gradations or higher by changing the magnitude of the sustain pulse according to the display ratio.

[0018]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention uses one frame for N first to Nth frames.
The sub-frame is temporally divided into two sub-frames, and the length of the sustain discharge period of the second sub-frame is multiplied by 2 ¹ times the length of the sustain discharge period of the ^first sub-frame. The length of the sustain discharge period is set to 2 ² times, and the length of the sustain discharge period of the Nth subframe is set to 2 ^N-1 times, and these N subframes from the 1st to the Nth are set. In addition to the configuration for selecting according to the gradation of the display data, during the sustain discharge period of the selected subframe, a potential difference is applied between the X electrode and the Y electrode to maintain a write phenomenon between the two electrodes for maintaining write data. In the plasma display panel that causes the above-mentioned, a detection unit that detects a display rate represented by a ratio of a lighted cell and a non-lighted cell of all display cells forming one screen,
Adjusting means for adjusting the potential difference applied between the X electrode and the Y electrode according to the display rate.

[0019]

The brightness in the above-mentioned "address / sustain discharge separation system" is determined by the number of sustain pulses during the sustain discharge period. Therefore, since the minimum unit of brightness variation depends on the size of one sustain pulse, the potential difference between the X electrode and the Y electrode depends on the display rate of all the display cells forming one screen as in the present invention. If the (sustain pulse size) is adjusted, 256
It is possible to avoid inadvertent grayscale inversion in grayscale or higher grayscale display, and to improve display quality.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are views showing an embodiment of a plasma display panel according to the present invention. First, the configuration will be described. In FIG. 1, 20 is a PDP unit, P
The DP unit 20 includes a panel section (see FIGS. 5 and 6 for the structure) 21, an address driver 22, a Y driver 23, and an X unit.
It is configured to include a driver 24 and a control circuit 25.

The control circuit 25 stores a display data buffer memory 26 for temporarily storing display data from the outside in order to display each time-divided subfield, and various basic waveform data required for display. Drive waveform ROM
(Read only memory) 27, a logic control circuit unit 28 that generates various signals required for the drivers 22 to 24, a high voltage control circuit unit 29 that supplies high voltage pulses required to the drivers 22 to 24, and the high voltage pulse. Voltage generation circuit (detection means, adjustment means) 3 for generating a high voltage power supply for
Equipped with 0.

The high voltage generation circuit 30, which is the point of this embodiment, has a display rate detection circuit 31 for detecting a display rate corresponding to the ratio of the lit cells to the non-lit cells in all cells based on the display data, and the display rate detection circuit 31. A data conversion ROM 32 for converting the display rate into voltage data, a time adjustment buffer 33 for adjusting the display timing for each subframe, and a D / A converter 34 for converting the time adjusted voltage data into an analog voltage.
A voltage amplifier 35 that amplifies the output of the D / A converter 34 at a constant amplification rate, a period determination circuit 36 that determines an address period and a sustain discharge period, and a voltage output circuit 37. The voltage output circuit 37 includes a P-channel MOS transistor 37a and an N-channel MOS transistor.
The transistor 37b is connected in series between the output of the voltage amplifier 35 and the ground, and each MOS transistor 3
A FET driver that inserts a capacitor 37d between the connection node of 7a and 37b and the cathode of the high breakdown voltage diode 37c, and responds to the output logic of the period determination circuit 36 to turn on / off each MOS transistor 37a and 37b complementarily. 37e. During the address period, the N-channel MOS transistor 37b is turned on to output the high voltage Vs supplied from the outside as it is, while during the sustain discharge period, the P-channel MOS transistor 37a is turned on to output the high voltage Vs supplied from the outside to the voltage amplifier. The output (α) of 35 is added and output.

FIG. 2 shows a preferred configuration example of the display rate detection circuit 31. R _{1 to} R ₆ , G _{1 to} G ₆ , and B _{1 to} B ₆ are each 6 bits (in the case of 64 gradations; in 256 gradations). 8-bit) display data (R: red, G: green, B: blue), V
SYNC is a vertical synchronizing signal, and CLOCK is a dot clock. 38 _{R1 to} 38 _R6 , 39 _{G1 to} 39 _G6 , 40 _B1 to
40 _B6 is a counter provided for each bit of red, green, and blue display data, and each counter has a predetermined logic (a logic for lighting a cell) of a corresponding bit of the display data in one vertical scanning period. Counting the number of high logics, for example). Outputs of all of the counters are added by the adder 41 ₁ to 41 ₆ for each bit, the output of the adder 41 ₁ re lower bit becomes the first display rate of the sub-frame SF _1, ......, the uppermost The output of the bit adder 41 ₆ is the sixth
The display rate is that of the sub-frame SF ₆ .

Next, the operation will be described. In the present embodiment, the value of the high voltage supplied from the high voltage generation circuit 30 to the high voltage control circuit unit 29 differs between the address period and the sustain discharge period. That is, as shown in FIG. 3A, in the address period,
The high voltage Vs supplied from the outside is supplied as it is, but during the sustain discharge period, the variable high voltage Vs + α adjusted according to the display rate of the display data at that time is supplied.

Therefore, the above-mentioned driving method (see FIG. 8 or FIG. 10) is used.
The magnitude of the sustaining pulse Vs during the sustaining discharge period (see FIG. 3) changes according to the display rate.
As shown in (b), since the screen brightness changes in proportion to the magnitude of the sustain pulse Vs within a certain voltage range, the magnitude of the adjustment voltage (α) (specifically, in the data conversion ROM 32). By optimizing the stored data), it becomes possible to correctly display the brightness of the high gradation display portion and the low gradation display portion even in the case of multi-gradation display of 256 gradations or more. The quality can be improved.

In the present embodiment, the high voltage Vs is adjusted only during the sustain discharge period, and the reason is as follows. The brightness of the screen can be changed by adjusting the high voltage Vs in the address period. However, the margin of Vs in this address period is shown in FIG.
As shown in (a), since it is given only in an extremely narrow range, when Vs deviates from the stable operation region, the non-selected cell may be turned on (region a) or the selected cell may be turned off (region b). Cause a malfunction. On the other hand, as shown in FIG. 4B, the margin of Vs in the sustain discharge period is from the upper limit voltage Vs _UP (the voltage at which the first one cell of all cells starts to discharge in the all erase screen) to the lower limit voltage Vs.
There is a considerable margin up to _LOW (the voltage at which the first one cell of all cells disappears in the all-lighted screen), and even if Vs is changed according to the display rate, the operation is similar to the address period. There is no inconvenience.

[0027]

According to the present invention, since the magnitude of the sustain pulse is changed according to the display ratio, it is possible to obtain an accurate display gradation and display 256 gradations or more. It is possible to improve the display quality.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a display rate detection circuit of the present invention.

FIG. 3 is a diagram showing a Vs composite output time chart and a relationship between Vs and luminance.

FIG. 4 is a Vs margin diagram for a sustain discharge period and a Vs margin diagram for an address period.

FIG. 5 is a schematic plan view of a typical three-electrode / surface discharge / AC PDP.

6 is a schematic cross-sectional view of one display cell of FIG.

FIG. 7 is a schematic block diagram of a conventional example.

FIG. 8 is a drive waveform diagram in the address / sustain discharge separate type self-erasing address system.

FIG. 9 is a time chart for 16 gradation display.

FIG. 10 is a drive waveform diagram in the address / sustain discharge separate type / write address system.

FIG. 11 is a relationship diagram between a display rate and brightness.

[Explanation of symbols]

A _j : Address electrodes SF _{1 to} SF ₄ : Subframe X: X electrode Y _i : Y electrode 7: Discharge space (display cell) 30: High voltage generation circuit (detection means, adjustment means)

Claims (1)

[Claims] 1. One frame is temporally divided into N subframes from a first to an Nth subframe, and the length of the sustain discharge period of the first subframe is compared with that of the second subframe. 2 ¹ times the length of the sustain discharge period, the third
² times the length of the sustain discharge period of the subframe of ...
The length of the sustain discharge period of the Nth subframe is set to 2 ^N-1 times, and N subframes from the 1st to the Nth can be selected according to the gradation of the display data. In addition, in the sustain discharge period of the selected sub-frame, one screen is formed in the plasma display panel that applies a potential difference between the X electrode and the Y electrode to generate a discharge phenomenon for maintaining write data between the both electrodes. A detection unit that detects a display ratio represented by a ratio of a lighted cell to a non-lighted cell of all display cells; and an adjustment unit that adjusts a potential difference applied between the X electrode and the Y electrode according to the display ratio. A plasma display panel characterized by being equipped.