KR100669274B1 - Method of driving flat panel display apparatus - Google Patents

Abstract

A data discrimination unit and a subfield control unit are provided to determine which of the gray levels divided into two or two or more based on the most significant bit or the highest number bit of the original image data is included in the gray level group. The subfield combination corresponding to the gradation-luminance characteristic matched to is selected. It has a complementary relationship with human visibility characteristics, and the luminance difference between the gray scales becomes smaller in the lower luminance region, and the luminance difference between gray scales becomes larger in the upper luminance region, so that the luminance density is uniformly visually recognized over the entire luminance region to obtain a good display quality. Can be.

Description

Method of driving flat display device {METHOD OF DRIVING FLAT PANEL DISPLAY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a flat panel display device that performs gradation display according to the length of lighting time, such as a plasma display panel (PDP).

PDP, which obtains a desired display image by controlling light emission and non-emission for each pixel by using plasma discharge, has the advantage of being thin, and is active as a flat panel display with a liquid crystal display (LCD). Development is in progress.

The PDP is formed so that the row electrode and the column electrode cross each other on a pair of opposed substrates with a discharge space between the substrates interposed therebetween, and a gas in which discharge is performed is enclosed in the gap between the substrates. The discharge light emission is performed by applying a voltage to an electrode cell corresponding to the intersection of the column electrodes and the row electrodes designated matrixwise, and these dot-shaped discharge light emission are visually recognized macroscopically to form images such as letters and figures. In the PDP using this principle, the amount of light emitted by discharge cannot be linearly controlled by the applied voltage. For this reason, each gradation is realized by controlling the lighting time in each pixel corresponding to the luminance.

Fig. 1 shows the structure of a conventional PDP. The original image data of R, G, and B is sent to the multi-tone coordination processor 10, in which the error diffusion processing described in the present applicant in Japanese Unexamined Patent Publication (JP-A) Hei 6-118920 is performed, and a predetermined bit is performed. For example, it is converted into 4 bits of data. The converted original image data is once stored in the frame memory 11, then sent to the data controller 12, and prescribed pixel data is created and sent to the data driver 18 of the PDP display unit 15. On the other hand, the horizontal sync pulse SYNC separated from the composite video signal is transmitted to the subfield timing controller 13, and various timing control signal pulses such as columns and rows, subfields, fields, and frames are generated, and a multi-gradation processor is generated. (10), the frame memory 11, the data controller 12, and the driver controller 14 are supplied. The driver controller 14 controls the drive timing of the Y electrode driver 16, the X electrode driver 17, and the data driver 18 of the PDP display unit 15 under the control of the subfield timing controller 13. .

In the PDP display unit 15, a plurality of Y electrodes 19 and an X electrode 20 are arranged in parallel with each other, and a plurality of data electrodes 21 are arranged in crossing with each other. The Y electrode 19 and the X electrode 20 are formed on one substrate, and the data electrode 21 is formed on the other substrate. The Y electrode 19 and the X electrode 20 are covered with a dielectric layer, and phosphors of R, G, and B are provided on the substrate on which one data electrode 21 is formed. Further, in the discharge cells composed of the Y electrodes 19, the X electrodes 20, and the data electrodes 21, the discharge space is divided by barrier ribs formed of the insulator layer formed on the substrate.

The Y electrode driver 16 supplies scan pulses and sustain pulses in the row direction to the Y electrode 19, and the X electrode driver 17 supplies sustain pulses to the X electrode 20. The X electrodes 20 are commonly driven in their entirety on the substrate. In addition, the data driver 18 supplies an address pulse to the data electrode 21 and performs an address in the column direction. Such three-electrode having a three-electrode type is called.

In the three-electrode type PDP, one field consists of a plurality of subfields, and each subfield mainly consists of an address period and a sustain discharge period. In each address period, one row, i.e., one scan line, consisting of a set of Y electrodes 19 and X electrodes 20 is selected first. That is, a scan pulse is applied to the Y electrode 19, and a sufficiently large voltage is applied between the X electrode 20 and the X electrode 20. In this state, a signal voltage is applied from the data driver 18 to the predetermined data electrode 21, and write discharge is performed in the discharge cells corresponding to one point designated in a matrix, and the Y electrodes with the dielectric layers interposed therebetween. (19) and wall charges are formed on the X electrode 20. In the subsequent sustain discharge period, sustain discharge pulses are applied to the Y electrode 16 and the X electrode 17 alternately at the same time, and the Y electrode 16 and the X so that the wall charges selectively generated in the address period change their polarities. The discharge light is emitted while moving between the electrodes 17 while maintaining the charge. This discharge is repeatedly performed irreversibly, and is lit to display sufficient luminance.

In the batch erasing and batch writing system, signal voltages are simultaneously applied to all the cells from the data driver 18 during batch writing before the address period, and wall charges are generated in all the cells. In the following address period, an erase pulse is selectively applied from the data driver 18. This erase pulse is a pulse whose wavelength or amplitude is smaller than that of the sustain discharge pulse. In the cell to which the erase pulse is supplied, an erase discharge is performed by applying a voltage having a polarity opposite to the wall charge generated at the time of writing to erase the wall charge. In the sustain discharge period, as described above, the sustain discharge pulse is alternately applied to the Y electrode 16 and the X electrode 17, and the sustain discharge is repeated a predetermined number of times.

In the case of performing grayscale display in the PDP, the luminance of each pixel serving as the discharge cell is adjusted by changing the length of the sustain discharge period controlled by the number of sustain discharges of each discharge cell. That is, a plurality of subfields having a sustain discharge period corresponding to the ratio of the predetermined luminance are created in the subfield timing controller 13, and the respective fields of the original image data are to be turned on in the form of assigning each bit of the original image data to these subfields. The combination of subfields is selected. That is, the pixels are turned on only in the selected subfield, and the length of the total sustain discharge is performed for each pixel is controlled in a form corresponding to the gradation of the original image data, and the total of these lighting times is recognized as the desired display luminance.

Conventionally, since a gamma correction is performed in accordance with the display characteristics of a CRT, a composite video signal for TV broadcasting or a computer output is used. Therefore, when displaying on a display other than a CRT, luminance correction is performed so as to match the inherent voltage-luminance characteristics of the display. Is done. Even in the configuration shown in Fig. 1, the original image data of each of R, G, and B supplied to the multi-gradation processor 10 is again subjected to gamma correction for the PDP to a signal subjected to gamma correction at the time of image transmission or computer output. By performing the correction, the voltage-luminance relationship curve is straight. In this example, the 16-gradation display can be obtained from the 4-bit original image data, but the relationship curve between the gradation and the display luminance is in a straight line form. In other words, the luminance difference between the gradations is the same at all levels. However, when actually observed with the naked eye, the human visibility is high in the low luminance region and the luminance difference is clearly recognized. On the contrary, in the high luminance region, the visibility is low and the luminance difference is difficult to be clearly recognized. For this reason, in visual recognition, the density of brightness | luminance generate | occur | produced over the whole brightness | luminance area | region, and the display quality was deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a driving method having a low luminance density and high display quality over the entire luminance region in a flat display of multi-gradation display.

In order to achieve this object, the present invention has the following features.

A driving method of a flat panel display device that displays luminance different for each pixel by multi-gradation display, and the gradation display is performed by making the luminance difference between the gradations on the low luminance side of the multi gradations smaller than the luminance difference between the gradations on the high luminance side of the multi gradations.

As a result, the luminance difference between the gray scales compressed in the low luminance region with high visibility is expanded and visually recognized. On the contrary, the luminance difference between the gray scales expanded in the high luminance region with low visibility is compressed and visually recognized. There is no loss of luminance.

In addition, in the driving method of the flat panel display device of the present invention, in order to display desired luminance in one field period composed of a plurality of subfield periods, each of the plurality of subfield periods is a pixel lighting period according to a luminance relative ratio. Set to,

The multi-gradation is divided into a plurality of gradation groups between the low luminance and the high luminance to determine which luminance level indicated by the original image data belongs to the plural gradation groups, and among the plural gradation groups Any of the plurality of subfield period groups, which are created by combining predetermined subfield periods from the plurality of subfield periods, so that the luminance difference between the gray levels in the gray level group on the side is smaller than the luminance difference between the gray levels in the gray level group on the high brightness side. Select one according to which the original image data belongs to the plurality of gradation groups,

The original image data is associated with each subfield period of the selected subfield period group, and the lighting and non-lighting of each pixel in the subfield period are controlled to perform multi-gradation display.

Further, in the present invention, from the predetermined upper bits of the digital original image data, it is discriminated to which of the plurality of gradation groups the luminance level of the original image data belongs.

In this way, when the gradation group belonging to it is determined based on the bit on the upper side of the original image data, it is possible to make a quick determination with a simple configuration.

In addition, in the driving method of the flat panel display device of the present invention, in order to display desired luminance in one field period composed of a plurality of sub-field periods, each of the plurality of sub-field periods has a pixel lighting period according to a luminance relative ratio. Set to,

A driving method of a flat panel display device which performs multi-gradation display by controlling the total lighting time of each pixel in the one field period by controlling the lighting and non-lighting of the pixels in the plurality of subfield periods, respectively.

The multi-gradation is divided into plural gradation groups between the low luminance and the high luminance, and the luminance difference between the gradations in the gradation group on the low luminance side is made smaller than the luminance difference between the gradations in the gradation group on the high luminance side.

In the present invention, the one field period is composed of n + 1 subfield periods.

2 levels of gradation are divided into a low luminance side 2 ^n-1 gradation group and a high luminance side 2 ^n-1 gradation group,

The luminance difference between the gradations in the gradation group on the low luminance side among the plurality of gradation groups is different depending on which of the low luminance side 2 ^n-1 gradation group and the high luminance side 2 ^n-1 gradation group belongs to. A predetermined n + 1 subfield period is selected from the n + 1 subfield periods so as to be smaller than the luminance difference between the gray levels in the gradation group on the high luminance side,

The original image data is associated with the selected subfield period, and the lighting and non-lighting of the pixels in the selected subfield period are controlled to perform gray level display of 2 ⁿ levels.

For example, by setting n = 4, all 16 levels of gradation are divided into gradation groups on the low luminance side and the high luminance side, and the predetermined four subfield periods are selected from the five subfield periods. 16 gradations can be displayed in which the luminance difference of the gradation group on the low luminance side becomes smaller than the luminance difference of the gradation group on the high luminance side.

In the present invention, the one field period is composed of n + 2 subfield periods.

The ²ⁿ level gradation is divided into a low luminance side 2 ^n-2 gradation group, a medium luminance side 2 ^n-2 gradation group, and a high luminance side 2 ^n-1 gradation group,

According to which of the three gradation groups the original image data belongs, so that the luminance difference between gradations in the gradation group on the low luminance side among the gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side. n + 2 predetermined subfield periods are selected from n + 2 subfield periods,

The original image data is associated with the selected subfield period, and the lighting and non-lighting of the pixels in the selected subfield period are controlled to perform gray level display of 2 ⁿ levels.

For example, in the above configuration, the one field period consists of six subfield periods,

The 16 levels of gradation are divided into a low luminance side 4 gradation group, a medium luminance side 4 gradation group, and a high luminance side 8 gradation group,

According to which of the three gradation groups the original image data belongs, so that the luminance difference between gradations in the gradation group on the low luminance side among the gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side. Selects six or less predetermined subfield periods from six subfield periods,

16 bits of gradation display are performed by controlling the lighting and non-lighting of pixels in the selected subfield period by matching each bit of the 4-bit original image data with the selected subfield period.

Thus, by dividing the gradation into three and selecting each gradation group from six subfield periods, it is easy to reduce the luminance difference of the gradation group on the low luminance side. Further, by setting a larger number of gradation groups to be divided, the gradation group on the low luminance side where the human visual perception is highest and the gradation group on the medium luminance side where the visual recognition degree is relatively high can be set to the luminance difference according to the visual recognition degree, respectively. In addition, since signal processing is simple, such driving can be realized by a simple configuration.

In addition, in the present invention, the one field period includes n + 3 subfield periods.

2 ⁿ gradations are divided into a low luminance side 2 ^n-2 gradation group, a medium luminance side 2 ^n-2 gradation group, and a high luminance side 2 ^n-1 gradation group,

According to which of the three gradation groups the original image data belongs, so that the luminance difference between gradations in the gradation group on the low luminance side among the gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side. select n + 3 subfield periods from n + 3 subfield periods,

The original image data is associated with the selected subfield period, and the lighting and non-lighting of the pixels in the selected subfield period are controlled to perform gray scale display of ²ⁿ .

For example, the one field period is composed of seven subfield periods.

The 16 levels of gradation are divided into a low luminance side 4 gradation group, a medium luminance side 4 gradation group, and a high luminance side 8 gradation group,

According to which of the three gradation groups the original image data belongs, so that the luminance difference between gradations in the gradation group on the low luminance side among the gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side. Four predetermined subfield periods are selected from the seven subfield periods,

16 bits of gradation display are performed by controlling the lighting and non-lighting of pixels in the selected subfield period by matching each bit of the 4-bit original image data with the selected subfield period.

Even in the case where seven subfield periods are set in this manner, the luminance difference of the gradation group on the low luminance side can be sufficiently low by a simple process. In addition, the luminance difference in the gradation group on the side of the medium luminance having the visual recognition degree can also be the appropriate luminance difference according to the visual recognition degree.

In the present invention, when the 16-level gray scale is divided into three gray scale groups, the low luminance side 2 ^n-2 gradation group, the medium luminance side 2 ^n-2 gradation group, and the high luminance side 2 ^n-2 gradation group Each luminance difference in E is smaller as the high luminance side 2 ^n-1 gradation group becomes the middle luminance side 2 ^n-2 gradation group and the low luminance side 2 ^n-2 gradation group.

[First Embodiment]

2 shows the configuration of a PDP according to the embodiment of the present invention. For example, each of the 8-bit original image data of R, G, and B is accepted by the multi-gradation processor 10, where error diffusion processing is performed and converted into predetermined bits, for example, 4 bits of data. . The converted original image data is temporarily stored in the frame memory 11, and the most significant bit is also supplied to the data discriminating unit 1 according to the present invention. In the data discriminating unit 1, from the most significant bit of the original image data, it is determined which area of the gradation group, which is divided into a plurality of original image data, for example. The determination signal generated by the data determination unit 1 is sent to the subfield timing control unit 4 according to the present invention. The subfield timing controller 4 is provided with subfield data for realizing the characteristics of the gradation and the display brightness corresponding to each of the two gradation groups, and based on the discrimination signal sent from the data discriminating unit 1 The display luminance area including the original image data is determined, and the subfield data is transmitted to the frame memory 11 and stored in a form related to the corresponding 4-bit original image data.

Each bit of the original image data stored in the frame memory 11 is supplied to the data controller 12 in a form associated with the subfield data obtained from the subfield timing control unit 4, and the pixel data is created to generate a PDP display unit ( The data driver 18 is supplied to the data driver 18 of FIG.

On the other hand, the horizontal and vertical synchronizing signals SYNC separated from the composite video signal are sent to the subfield timing controller 4 to generate signal pulses for the frame period, the field period, the subfield period, and the timing control of the rows and columns. To the multi-gradation processor 10, the frame memory 11, the data controller 12, and the driver controller 14. The driver controller 14 controls the driving of the Y electrode driver 16, the X electrode driver 17, and the data driver 18 so that the frame period, the field period, the subfield period, and the address period and sustain discharge of each subfield period are maintained. Control the timing of the columns and rows in the period. In addition, the data driver 18 receives timing control from the driver controller 14 and, based on the pixel data sent from the data controller 12, applies a signal voltage to the PDP display unit 15 in the subfield period to be turned on. Supplying to turn on pixels specified in a matrix.

3 shows a detailed configuration of the data discriminating unit 1 and the subfield timing controller 4. The data determination unit 1 includes a frame memory 2 and a data determination circuit 3. The subfield timing controller 4 includes a timing controller 5, first and second subfield timing circuits 6, 7) and the selector circuit 8.

The most significant bits of the original image data R, G, and B sent from the multi-gradation processor 10 are once stored in the frame memory 2. The most significant bit of this original image data is read by the data discriminating circuit 3, and discriminates whether it is 1 or 0 to determine whether the original image data is included in the upper or lower gradation group divided into two. That is, when the most significant bit is 0, it is determined as the lower region, and when it is 1, it is determined as the upper region. This determination signal is sent to the selector circuit 8 of the subfield timing controller 4.

On the other hand, in the subfield timing controller 4, the timing controller 5 generates various timing pulses of frames, fields, subfields, lines, and dots based on horizontal and vertical synchronization signals SYNC supplied from the outside. It is created and sent to the multi-gradation processor 10, the frame memory 11, the data controller 12, and the driver controller 14.

The timing controller 5 also controls the timing of the first and second subfield timing circuits 6, 7. The first and second subfield timing circuits 6 and 7 read subfield data corresponding to the upper and lower grayscale groups, respectively, from the subfield timing information provided in the ROM or the like under the control of the timing controller 5, Supply to the selector circuit 8. In the ROM, each subfield timing control data of the first subfield SF0, the second subfield SF1, the third subfield SF2, the fourth subfield SF3, and the fifth subfield SF4 is stored. Maintained. In these first to fifth subfields SF0, SF1, SF2, SF3, SF4, the relative ratios of the lengths of the sustain discharge periods of the respective subfields are obtained at 2: 4: 8: 16: 17. The first subfield timing circuit 6 includes first timing control data including the first subfield SF0, the second subfield SF1, the third subfield SF2, and the fifth subfield SF4. The subfield data is provided, and the second subfield timing circuit 7 includes the second subfield SF1, the third subfield SF2, the fourth subfield SF3, and the fifth subfield SF4. Second subfield data consisting of the respective timing control data is provided. That is, the first and second subfield data are four subfields selectively designated by the above-described combination from the five subfield timing control data, thereby realizing driving of the 4-bit five subfield system. The selector circuit 8 receives the discrimination signal of the gradation group sent from the data discriminating unit 1, selects any subfield data, and sends it to the frame memory 11. In the frame memory 11, this subfield data is stored in association with the 4-bit original image data. That is, the 4-bit original image data is associated with a combination of predetermined subfields depending on which of the upper and lower levels of the gradation group belongs to.

Table 1 shows the gradations of the original image data in the 4-bit 5 subfield system of the present invention, the subfield combinations corresponding thereto, the luminance at that time, and the relative ratio thereof.

First embodiment of the present invention 4 bit 5 subfield scheme Comparative Example 4 Bit 4 Subfield Method Gradation SF SF SF SF SF 0 1 2 3 4 Luminance (% of contrast) SF SF SF SF 0 1 2 3 Luminance (% of contrast) One 0 0 0 0 0 0  0 (0) 0 0 0 0  0 (0) 2 One 1 0 0 0 0  2 (4.4) 1 0 0 0  2 (6.8) 3 10 0 1 0 0 0  4 (8.9) 0 1 0 0  4 (13.3) 4 11 1 1 0 0 0  6 (13.3) 1 1 0 0  6 (20.0) 5 100 0 0 1 0 0  8 (17.8) 0 0 1 0  8 (26.7) 6 101 1 0 1 0 0 10 (22.2) 1 0 1 0 10 (33.3) 7 110 0 1 1 0 0 12 (26.7) 0 1 1 0 12 (40.0) 8 111 1 1 1 0 0 14 (31.1) 1 1 1 0 14 (46.7) 9 1000 0 0 0 0 1 17 (37.8) 0 0 0 1 16 (53.3) 10 1001 0 1 0 0 1 21 (46.7) 1 0 0 1 18 (60.0) 11 1010 0 0 1 0 1 25 (55.6) 0 1 0 1 20 (66.7) 12 1011 0 1 1 0 1 29 (64.4) 1 1 0 1 22 (73.3) 13 1100 0 0 0 1 1 33 (73.3) 0 0 1 1 24 (80.0) 14 1101 0 1 0 1 1 37 (82.2) 1 0 1 1 26 (86.7) 15 1110 0 0 1 1 1 41 (91.1) 0 1 1 1 28 (93.3) 16 1111 0 1 1 1 1 45 (100.) 1 1 1 1 30 (100.)

In addition, as a comparative example, the same value in the case of the conventional 4-bit 4 subfield system is described. As can be seen from the table, in the first embodiment according to the present invention, in 16 gray scale display using 4 bit original image data, in the lower 8 gray scales on the low luminance side, the subfield ( Four subfields (SF0, SF1, SF2, SF4) are selected, and each bit of the original image data is assigned to it. In the upper eight gradations on the high luminance side, the subfields SF1, SF2, SF3, SF4 are selected based on the above-described second subfield data, and each bit of the original image data is assigned thereto. As a result, the luminance difference from 2 to 8 to 9 is between 1 and 8, and the luminance difference between 3 to 9 and 16 to 4 is from 4 to 9, respectively. On the other hand, in the comparative example, the luminance difference is constant at 2 between grays from 1 to 16 grays.

In Fig. 4, the relationship between the gradation obtained from Table 1 and the luminance is shown by characteristic curves A and B, respectively, for each case of the invention and the comparative example. The horizontal axis represents the number of gray scales, and the vertical axis represents the relative ratio of luminance. As shown in curve A, in the first embodiment according to the present invention, the slopes of the characteristic curves from 1 to 8 and 9 to 16 are different. That is, the luminance difference between the gradations in the low luminance region from 1 to 8 gradations is smaller than the luminance difference between the gradations in the high luminance region from 9 to 16 gradations.

On the other hand, as shown in the curve B, conventionally, the relationship curve between the gradation and the luminance is linear, and the luminance rises or falls with the direct relation with the gradation. Originally, human visibility is high in the low luminance region and human visibility is low in the high luminance region. When the display is performed by gray scale control such as the characteristic curve B, the luminance difference between the gray scales is felt in the low luminance region, and the luminance between the gray scales in the high luminance region. The car feels small. For this reason, a clear image cannot be observed over the entire luminance region. On the other hand, in the first embodiment according to the present invention, by reducing the luminance difference between the gray scales in the low luminance region and increasing the luminance difference between the gray scales in the high luminance region, the display characteristics of the human are corrected. The luminance difference between the gray scales is uniformly recognized over the entire luminance region, and there is no dense luminance and a clear image is observed.

5 shows the configuration of one field in the PDP driving method according to the embodiment of the present invention. (A) of FIG. 1 is a structure of one field created by the timing controller 5, and consists of five subfields SF0, SF1, SF2, SF3, SF4 which have an address period and a sustain discharge period. In each of these subfields SF0, SF1, SF2, SF3, SF4, the length of the sustain discharge period is changed to show a predetermined luminance ratio. The length of the sustain discharge period is the length of the lighting period and corresponds to the luminance. The relative ratio of the lighting time of each subfield SF0, SF1, SF2, SF3, SF4 is set to 2: 4: 8: 16: 17.

(B) of the figure is one field consisting of four subfields SF0, SF1, SF2, SF4 to which each bit is allocated when the original image data is from 1 to 8 gradations, and (c) in the figure When image data is from 9 to 16 gradations, it is one field composed of four subfields SF1, SF2, SF3, SF4 to which each bit is allocated. That is, within one field consisting of five subfields as shown in (a), four subfields are selectively provided as shown in (b) or (c) according to the displayed gray level, and the lighting and non-lighting are performed. The gray scale display is controlled.

Second Embodiment

6 shows a configuration of a PDP according to the second embodiment of the present invention. In the drawings to be described later, the description of the same parts corresponding to the configurations in the drawings described in the above-described embodiments will be omitted. The converted original image data is temporarily stored in the frame memory 11, and in this embodiment, the upper two bits of the four bits of the original image data sent from the multi gradation processor 10 are the data discriminating unit 22 according to the present invention. Is also supplied. In the data discriminating unit 22, from the upper two bits of the original image data, it is determined in which region of the gradation group the original image data is divided into three levels of lower, middle, and upper. The discrimination signal produced by the data discriminating unit 22 is sent to the subfield timing controller 24 according to the second embodiment of the present invention. The subfield timing controller 24 is provided with subfield data for realizing the characteristics of the gradation corresponding to each of the three gradation groups and the display luminance, and is based on the discrimination signal sent from the data discrimination unit 22. Thus, the display luminance region in which the original image data is included is determined, and the subfield data is sent to the frame memory 11, and the frame memory 11 is connected to the four-bit original image data. Stored.

7 shows a detailed configuration of the data discriminating unit 22 and the subfield timing controller 24 according to the second embodiment. The data determination unit 1 includes a frame memory 2 and a data determination circuit 23. The subfield timing controller 24 includes a timing controller 25 and first, second and third subfield timings. Circuits 26, 27, and 28, and a selector circuit 29. As shown in FIG.

The upper two bits of the original image data R, G, and B sent from the multi-gradation processor 10 are once stored in the frame memory 2. The upper two bits of the original image data are read by the data discriminating circuit 23, and the data discriminating circuit 23 determines whether the upper two bits of the data is 00, 01, or 1x, so that the original image data is three. It is determined whether it is included in the lower, middle, or upper gradation group divided into dogs. That is, it is determined as the lower region when the upper 2 bits are 00, the middle region when 01, and the upper region when the most significant bit is 1. This discrimination signal is sent from the data discriminating circuit 23 to the selector circuit 29 of the subfield timing control section 24.

On the other hand, in the subfield timing controller 24, the timing controller 25 creates various timing pulses of frames, fields, subfields, lines, and dots based on horizontal and vertical synchronization signals SYNC supplied from the outside. To the multi-gradation processor 10, the frame memory 11, the data controller 12, and the driver controller 14.

The timing controller 25 also controls the timing of the first, second and third subfield timing circuits 26, 27, 28. The first, second, and third sub-field timing circuits 26, 27, and 28 correspond to the lower, middle, and upper gradation groups, respectively, from the sub-field timing information provided in the ROM or the like, under the control of the timing controller 25. One subfield data is read and supplied to the selector circuit 29. The ROM includes a first subfield SF0, a second subfield SF1, a third subfield SF2, a fourth subfield SF3, a fifth subfield SF4, and a sixth subfield SF5. Each subfield timing control data is stored. In these first to sixth subfields SF0, SF1, SF2, SF3, SF4, SF5, the relative ratio of the lengths of the sustain discharge periods of each subfield is set to 1: 2: 4: 16: 5: 14. do. The first subfield timing circuit 26 includes the first subfield SF0, the second subfield SF1, the third subfield SF2, and the sixth subfield SF5. One subfield data is provided. The second sub-field timing circuit 27 includes the timing control data of the second sub-field SF1, the third sub-field SF2, the fifth sub-field SF4 and the sixth sub-field SF5. Two subfield data are provided. The third subfield timing circuit 28 includes a first subfield SF0, a second subfield SF1, a third subfield SF2, a fourth subfield SF3, and a fifth subfield SF4. And third subfield data including the sixth subfield SF5. That is, the first, second and third subfield data are selectively designated four or all subfields in the above-described combination from the six subfield timing control data, thereby realizing driving of the 4-bit 6 subfield method. . The selector circuit 29 receives the discrimination signal of the gradation group sent from the data discriminating unit 22, selects one subfield data, sends it to the frame memory 11, and associates it with the 4-bit original image data. Even in the frame memory 11. That is, the 4-bit original image data is associated with a combination of predetermined subfields depending on which of the lower, middle, and upper levels of the gradation group belongs.

Table 2 shows the gradations of the original image data in the 4-bit 6 subfield system of the second embodiment, the subfield combinations corresponding to them, the luminance at that time, and the relative ratio thereof.

Second embodiment of the present invention 4 bit 6 subfield scheme Comparative Example 4 Bit 4 Subfield Method Gradation SF SF SF SF SF SF 0 1 2 3 4 5 Luminance (% of contrast) SF SF SF SF 0 1 2 3 Luminance (% of contrast) One 0 0 0 0 0 0 0  0 (0) 0 0 0 0  0 (0) 2 One 1 0 0 0 0 0  1 (2.4) 1 0 0 0  2 (6.7) 3 10 0 1 0 0 0 0  2 (4.8) 0 1 0 0  4 (13.3) 4 11 1 1 0 0 0 0  3 (7.1) 1 1 0 0  6 (20.0) 5 100 0 0 0 0 1 0  5 (11.9) 0 0 1 0  8 (26.7) 6 101 0 1 0 0 1 0  7 (16.7) 1 0 1 0 10 (33.3) 7 110 0 0 1 0 1 0  9 (21.4) 0 1 1 0 12 (40.0) 8 111 0 1 1 0 1 0 11 (26.2) 1 1 1 0 14 (46.7) 9 1000 0 0 0 0 0 1 14 (33.3) 0 0 0 1 16 (53.3) 10 1001 0 0 1 0 0 1 18 (42.9) 1 0 0 1 18 (60.0) 11 1010 1 1 0 0 1 1 22 (52.4) 0 1 0 1 20 (66.7) 12 1011 1 1 1 0 1 1 26 (61.9) 1 1 0 1 22 (73.3) 13 1100 0 0 0 1 0 1 30 (71.4) 0 0 1 1 24 (80.0) 14 1101 0 0 1 1 0 1 34 (81.0) 1 0 1 1 26 (86.7) 15 1110 1 1 0 1 1 1 38 (90.5) 0 1 1 1 28 (93.3) 16 1111 1 1 1 1 1 1 42 (100.) 1 1 1 1 30 (100.)

In addition, as a comparative example, the same value in the case of the conventional 4-bit 4-subfield system is described similarly to Table 1. As can be seen from the table, in the second embodiment, in the 16th gradation display by the 4-bit original image data, in the lower 4 gradations on the low luminance side, the four subfields SF0 are based on the first subfield data described above. , SF1, SF2, SF5) are selected, and each bit of the original image data is assigned to it. In the median four gradations, four subfields SF1, SF2, SF4, SF5 are selected based on the above-described second subfield data, and each bit of the original image data is assigned thereto. In addition, in the upper eight gradations on the high luminance side, all subfields SF0, SF1, SF2, SF3, SF4, SF5 are selected based on the third subfield data, and one bit of the original image data is converted into the third subfield SF2. ), Two bits are allocated to the first, second and fifth subfields SF0, SF1, SF4, three bits are allocated to the fourth subfield SF3, and four bits are assigned to the sixth subfield. Assign to (SF5). As a result, the luminance difference between gradations from 1 to 4 gradations is 1, the luminance difference between gradations from 2 to 8 gradations is 2, the luminance difference between 8 gradations and 9 gradations is 3, and the luminance difference from 9 to 16 gradations becomes 4. On the other hand, in the comparative example, the luminance difference is constant at 2 between grays from 1 to 16 grays.

In Fig. 8, the relationship between the gradation obtained from Table 2 and the luminance is shown by the characteristic curves B and C in each case of the second example and the comparative example, respectively. The horizontal axis represents the number of gray scales, and the vertical axis represents the relative ratio of luminance. From the curve C, in the second embodiment, the inclination of the characteristic curve is different in the lower region from 1 to 4 gradations, the middle region from 4 to 8 gradations, and the upper region from 9 to 16 gradations. That is, the luminance difference between the gray scales in the low luminance region from 1 to 4 gray scales is smaller than the luminance difference between the gray scales in the high luminance region from 9 to 16 gray scales.

On the other hand, the curve B according to the comparative example is the same as the curve B in Fig. 4, and the relationship curve of the gradation and the luminance is linear, and the luminance is rising or falling in proportion to the gradation. For this reason, a clear image cannot be observed over the entire luminance region. In contrast, in the second embodiment, the display characteristics are corrected by human detection characteristics by reducing the luminance difference between the gray scales in the low luminance region and increasing the luminance difference between the gray scales in the high luminance region. The luminance difference between the gray scales is uniformly recognized over the luminance region, and a clear image without dense luminance is observed. Further, in the second embodiment, the luminance difference between the gray scales in the low luminance region is smaller than that in the first embodiment, so that visually more uniform images can be displayed.

9 shows the configuration of one field in the PDP driving method according to the embodiment of the present invention. (A) of FIG. 1 is a structure of one field created by the timing controller 5, and consists of six subfields SF0, SF1, SF2, SF3, SF4, SF5 which have an address period and a sustain discharge period. In each of these subfields SF0, SF1, SF2, SF3, SF4, SF5, the length of the sustain discharge period is changed to show a predetermined luminance ratio. The length of the sustain discharge period is the length of the lighting time and corresponds to the luminance. The relative ratio of the lighting time of each subfield SF0, SF1, SF2, SF3, SF4, SF5 is set to 1: 2: 4: 16: 5: 14.

(B) of the figure is one field consisting of four subfields SF0, SF1, SF2, SF5 to which each bit is allocated when the original image data is from 1 to 4 gradations, and (c) in the figure One field consisting of four subfields (SF1, SF2, SF4, SF5) to which each bit is allocated when the image data is from 5 to 8 gray scales, (d) in the drawing shows that the original image data is from 9 gray scales to 16 gray scales. In this case, it is one field including six subfields SF0, SF1, SF2, SF3, SF4, SF5 allocated to each bit. That is, within one field composed of six subfields as shown in (a), four or six subfields are selectively provided as shown in (b), (c) or (d) according to the displayed gray level. Each bit of the original image data is assigned to each subfield by the combination described above, and lighting and non-lighting are controlled to perform gradation display.

10 shows the configuration of a PDP according to the third embodiment. The original image data of each of the four bits of R, G, and B sent from the multi gradation processor 10 is temporarily stored in the frame memory 11, and, as in the second embodiment, the upper two bits are the data determination unit according to the present invention. Also supplied to (31). In the data discriminating unit 31, from the upper two bits of the original image data, it is determined which region of the gradation group is divided into three groups of lower, middle and upper. The determination signal generated by the data determination unit 31 is sent to the subfield timing controller 34 according to the present invention. The subfield timing controller 4 is provided with subfield data for realizing the characteristics of the gradation corresponding to each of the three gradation groups and the display luminance, and is based on the discrimination signal sent from the data discrimination unit 31. Then, the gradation group including the original image data is determined, and the subfield data is transmitted to the frame memory 11, and stored in the form associated with the corresponding 4-bit original image data.

11 shows a detailed configuration of the data discriminating unit 31 and the subfield timing controller 34. The data discriminating unit 31 includes a frame memory 32 and a data discriminating circuit 33. The subfield timing controller 34 includes a timing controller 35, first, second and third subfield timing circuits. 36, 37, 38 and the selector circuit 39.

The timing controller 35 also controls the timing of the first, second and third subfield timing circuits 36, 37, 38. The first, second, and third subfield timing circuits 36, 37, and 38 correspond to the lower, middle, and upper gradation groups, respectively, from the subfield timing information provided in the ROM or the like, under the control of the timing controller 35. One subfield data is read and supplied to the selector circuit 39. In the present embodiment, the ROM includes the first subfield SF0, the second subfield SF1, the third subfield SF2, the fourth subfield SF3, the fifth subfield SF4, and the sixth subfield. Each subfield timing control data of the SF5 and the seventh subfield SF6 is held. In these first to seventh subfields SF0, SF1, SF2, SF3, SF4, SF5, SF6, the relative ratio of the length of the sustain discharge period of each subfield is 1: 2: 4: 8: 16: 5 Is set to 14. The first subfield timing circuit 36 includes the first subfield SF0, the second subfield SF1, the sixth subfield SF5, and the seventh subfield SF6. One subfield data is provided. The second subfield timing circuit 37 includes a timing control data including respective timing control data of the second subfield SF1, the third subfield SF2, the sixth subfield SF5, and the seventh subfield SF6. Two subfield data are provided. The third subfield timing circuit 38 further includes a third subfield including the third subfield SF2, the fourth subfield SF3, the fifth subfield SF4, and the seventh subfield SF6. Data is provided. That is, the first, second, and third subfield data are four subfields selectively designated in the above-described combination from the seven subfield timing control data, thereby realizing driving of the 4-bit 7 subfield system. The selector circuit 39 receives the discrimination signal of the gradation group sent from the data discriminating unit 31, selects any one of the subfield data, sends it to the frame memory 11, and associates it with the 4-bit original image data. Are stored. That is, the 4-bit original image data is associated with a combination of predetermined subfields depending on which of the lower, middle, and upper levels of the gradation group belongs.

Table 3 describes the gradations of the original image data in the 4-bit 7 subfield system of the third embodiment, the subfield combinations corresponding thereto, the luminance at that time, and the relative ratio thereof.

Third embodiment of the present invention 4 bit 7 subfield scheme Comparative Example 4 Bit 4 Subfield Method Gradation SF SF SF SF SF SF SF 0 1 2 3 4 5 6 Luminance (% of contrast) SF SF SF SF 0 1 2 3 Luminance (% of contrast) One 0 0 0 0 0 0 0 0  0 (0) 0 0 0 0  0 (0) 2 One 1 0 0 0 0 0 0  1 (2.4) 1 0 0 0  2 (6.7) 3 10 0 1 0 0 0 0 0  2 (4.8) 0 1 0 0  4 (13.3) 4 11 1 1 0 0 0 0 0  3 (7.1) 1 1 0 0  6 (20.0) 5 100 0 0 0 0 0 1 0  5 (11.9) 0 0 1 0  8 (26.7) 6 101 0 1 0 0 0 1 0  7 (16.7) 1 0 1 0 10 (33.3) 7 110 0 0 1 0 0 1 0  9 (21.4) 0 1 1 0 12 (40.0) 8 111 0 1 1 0 0 1 0 11 (26.2) 1 1 1 0 14 (46.7) 9 1000 0 0 0 0 0 0 1 14 (33.3) 0 0 0 1 16 (53.3) 10 1001 0 0 1 0 0 0 1 18 (42.9) 1 0 0 1 18 (60.0) 11 1010 0 0 0 1 0 0 1 22 (52.4) 0 1 0 1 20 (66.7) 12 1011 0 0 1 1 0 0 1 26 (61.9) 1 1 0 1 22 (73.3) 13 1100 0 0 0 0 1 0 1 30 (71.4) 0 0 1 1 24 (80.0) 14 1101 0 0 1 0 1 0 1 34 (81.0) 0 0 1 1 26 (86.7) 15 1110 0 0 0 1 1 0 1 38 (90.5) 0 1 1 1 28 (93.3) 16 1111 0 0 1 1 1 0 1 42 (100.) 1 1 1 1 30 (100.)

In addition, in Table 3, the comparative example shows the same value in the case of the conventional 4-bit 4 subfield system similarly to the comparative example of Table 1, Table 2. As can be seen from Table 3, in the third embodiment, in the 16th gradation display by the 4-bit original image data, in the lower 4 gradations on the low luminance side, four subfields ( SF0, SF1, SF5, SF6) are selected, and each bit of the original image data is assigned to it. In the median four gradations, four subfields SF1, SF2, SF5, SF6 are selected based on the above-described second subfield data, and each bit of the original image data is assigned thereto. In the upper eight gradations on the high luminance side, four subfields SF2, SF3, SF4, SF6 are selected based on the third subfield data, and each bit of the original image data is assigned to it. As a result, the luminance difference between gradations from 1 to 4 gradations is 1, the luminance difference between gradations from 2 to 8 gradations is 2, the luminance difference between 8 gradations and 9 gradations is 3, and the luminance difference from 9 to 16 gradations becomes 4. On the other hand, in the comparative example, the luminance difference is constant at 2 between grays from 1 to 16 grays.

In Fig. 12, the relationship between the gradation obtained from Table 3 and the luminance is shown by the characteristic curves D and B in each case of the third example and the comparative example, respectively. The horizontal axis represents the number of gray scales, and the vertical axis represents the relative ratio of luminance. In addition, curve B is the same comparative example as curve B of FIG. 4 and FIG. 8 demonstrated in 1st Example and 2nd Example. Curve D shows the characteristics of the third embodiment, and the slope of the characteristic curve in the lower region from 1 to 4 gray, the middle region from 4 to 8 gray, and the upper region from 9 to 16 gray different. That is, in this third embodiment, the luminance difference between the gray scales in the low luminance region from 1 to 4 gray scales is the smallest, and the luminance difference between the gray scales in the high luminance region from 9 gray scales to 16 gray scales is the largest.

By controlling the gradation in the 4-bit 7 subfield method, the luminance difference between the gradations in the low luminance region is reduced, and the luminance difference between the gradations in the high luminance region is increased, which is the same as the second embodiment of the 4 bit 6 subfield system. In the form in which the detection characteristic of the human is corrected the display characteristic, the luminance difference between the gray scales is uniformly recognized over the entire luminance region, and a clear image without denseness of luminance is observed.

Fig. 13 shows the structure of one field in the PDP driving method according to the third embodiment. FIG. 13A shows the configuration of one field created by the timing control 5, and consists of seven subfields SF0, SF1, SF2, SF3, SF4, SF5, SF6 having an address period and a sustain discharge period. . In each of the subfields SF0, SF1, SF2, SF3, SF4, SF5, SF6, the length of the sustain discharge period is changed to display a predetermined luminance ratio. The length of the sustain discharge period is the length of the lighting time and corresponds to the luminance. The relative ratio of the lighting time of each subfield SF0, SF1, SF2, SF3, SF4, SF5, SF6 is set to 1: 2: 4: 8: 16: 5: 14.

(B) in FIG. 1 is a field consisting of four subfields SF0, SF1, SF5, SF6 to which each bit is allocated when the original image data is from 1 to 4 grayscales, and (c) in FIG. One field consisting of four subfields (SF1, SF2, SF5, SF6) to which each bit is allocated when the image data is from 5 to 8 gray scales, (d) in the drawing shows that the original image data is from 9 gray scales to 16 gray scales. In this case, it is one field composed of four subfields SF2, SF3, SF4, SF6 allocated to each bit. That is, within one field consisting of seven subfields as shown in (a), four subfields as shown in (b), (c) or (d) are selectively provided according to the displayed gray level. Each bit of the image data is assigned to each subfield, and gradation display is performed by controlling lighting and non-lighting.

According to the present invention, since the luminance difference between the gray scales becomes smaller in the lower luminance region and the luminance difference between the gray scales increases in the lower luminance region, the luminance density is visually recognized uniformly over the entire luminance region. Good display quality can be obtained.

1 is a diagram showing a schematic configuration of a conventional PDP.

Fig. 2 is a diagram showing a schematic configuration of a PDP according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating the configuration of the data discriminating unit and the subfield timing control unit of FIG. 2. FIG.

Fig. 4 is a diagram showing a relationship between gray scales and display luminances of a PDP according to the first embodiment.

Fig. 5 is a diagram showing a combination of subfields in the PDP driving method according to the first embodiment.

6 is a diagram showing a schematic configuration of a PDP according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a data discriminating unit and a subfield timing control unit of FIG. 6. FIG.

Fig. 8 is a diagram showing the relationship between the grayscale and display luminance of a PDP according to the second embodiment.

Fig. 9 is a diagram showing a combination of subfields in the PDP driving method according to the second embodiment.

10 is a diagram showing the schematic configuration of a PDP according to a third embodiment of the present invention;

FIG. 11 is a diagram showing the configuration of the data discriminating unit and the subfield timing control unit of FIG. 10; FIG.

Fig. 12 is a diagram showing a relationship between gray scales and display luminances of a PDP according to the third embodiment.

Fig. 13 is a diagram showing a combination of subfields in the PDP driving method according to the third embodiment.

<Explanation of symbols for the main parts of the drawings>

1: data determination unit

4: sub-field timing controller

8: selector circuit

10: multi-gradation processor

11: frame memory

12: data controller

14: Driver Controller

15: PDP display unit

16: Y electrode driver

17: X electrode driver

18: data driver

Claims (9)

In the driving method for multi-gradation display of the flat panel display device, In one field period consisting of a plurality of subfield periods, in order to display desired luminance, each of the plurality of subfield periods is set to a pixel lighting period according to the luminance relative ratio, The multi-gradation is divided into a plurality of gradation groups from the low luminance to the high luminance, and it is determined by the upper bit of the original image data whether the luminance level represented by the original image data belongs to the plurality of gradation groups, It is created by combining predetermined subfield periods from the plurality of subfield periods so that the luminance difference between the gradations in the gradation group on the low luminance side among the plurality of gradation groups is smaller than the luminance difference between the gradations in the gradation group on the high luminance side. One of the plurality of sub-field period groups is selected based on which of the plurality of gradation groups the original image data belongs to, Correlating the original image data to each subfield period of the selected subfield period group, and controlling lighting and non-lighting of each pixel in the selected subfield period to perform multi-gradation display. A multi-gradation display driving method of a flat panel display device. In one field period consisting of a plurality of subfield periods, in order to display desired luminance, each of the plurality of subfield periods is set to a pixel lighting period according to the luminance relative ratio, A driving method of a flat panel display device which performs multi-gradation display by controlling the total lighting time of each pixel in the one field period by controlling the lighting and non-lighting of the pixels in the plurality of subfield periods, respectively. The multi-gradation original image data is divided into a plurality of gradation groups from low to high luminance by the higher bits, and the luminance difference between gradations in the gradation group on the low luminance side is selected on the high luminance side by selection of the plurality of subfield periods. A method for driving a multi-gradation display of a flat panel display device, characterized in that it is smaller than the luminance difference between the gray scales in the grayscale group. The method of claim 2, wherein the one field period comprises n + 1 subfield periods. 2 ^n- level gradation is divided into a low luminance side 2 ^n-1 gradation group and a high luminance side 2 ^n-1 gradation group, The luminance difference between the gradations in the gradation group on the low luminance side among the plural gradation groups is high depending on which of the low luminance side 2 ^n-1 gradation groups and the high luminance side 2 ^n-1 gradation group belongs to the original image data. A predetermined n + 1 subfield period is selected from the n + 1 subfield periods so as to be smaller than the luminance difference between the gray levels in the gradation group on the side, Corresponding the original image data to the selected subfield period, and controlling the lighting and non-illumination of pixels in the selected subfield period to perform ²ⁿ level gradation display. Way. The method of claim 2, wherein the one field period comprises n + 2 subfield periods. The ²ⁿ level gradation is divided into a low luminance side 2 ^n-2 gradation group, a medium luminance side 2 ^n-2 gradation group, and a high luminance side 2 ^n-1 gradation group, N according to which of the three gradation groups, the luminance difference between the gradations in the gradation group on the low luminance side among the three gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side N + 2 predetermined subfield periods are selected from +2 subfield periods, Corresponding the original image data to the selected subfield period, and controlling the lighting and non-illumination of pixels in the selected subfield period to perform ²ⁿ level gradation display. Way. The method of claim 4, wherein the low-luminance side ^{2 n-2} gradation level group, wherein the luminance-side ^{2 n-2} gradation level group, and each of the luminance in the high luminance side 2 ^n-1 gray scale group difference, a high luminance side 2 ^n-1 gradations A method for driving a multi-gradation display of a flat panel display device, characterized in that it becomes smaller as a group becomes a medium luminance side 2 ^n-2 gradation group and a low luminance side 2 ^n-2 gradation group. The method of claim 2, wherein the one field period is composed of six subfield periods. The 16 levels of gradation are divided into a low luminance side 4 gradation group, a medium luminance side 4 gradation group, and a high luminance side 8 gradation group, Depending on which of the three gradation groups the original image data belongs to, the luminance difference between the gradations in the gradation group on the low luminance side among the gradations is smaller than the luminance difference between the gradations in the gradation group on the high luminance side. 6 or less predetermined subfield periods are selected from the six subfield periods, A 16-level grayscale display is performed by associating each bit of the 4-bit original image data with the selected subfield period, and controlling lighting and non-lighting of pixels in the selected subfield period. Multi-gradation display driving method. The method of claim 2, wherein the one field period comprises n + 3 subfield periods. 2 ⁿ gradations are divided into a low luminance side 2 ^n-2 gradation group, a medium luminance side 2 ^n-2 gradation group, and a high luminance side 2 ^n-1 gradation group, The n is such that the luminance difference between the gradations in the gradation group on the low luminance side among the three gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side depending on which of the three gradation groups belongs to the original image data. Select n + 3 subfield periods from +3 subfield periods, The gray scale display driving method of the flat display device characterized in that the original image data is associated with the selected subfield period, and the lighting and non-lighting of the pixels in the selected subfield period are controlled to perform ²ⁿ gradation display. . 8. The luminance difference method according to claim 7, wherein the luminance difference in the low luminance side 2 ^n-2 gradation group, the medium luminance side 2 ^n-2 gradation group, and the high luminance side 2 ^n-1 gradation group is higher than the high luminance side 2 ^n-1 gradation group. And a small luminance side 2 ^n-2 gradation group and a lower luminance side 2 ^n-2 gradation group. The method of claim 2, wherein the one field period is composed of seven subfield periods. The 16 levels of gradation are divided into a low luminance 4 gradation group, a medium luminance 4 gradation group, and a high luminance 8 gradation group. Depending on which of the three gradation groups the original image data belongs to, the luminance difference between the gradations in the gradation group on the low luminance side among the three gradation groups becomes smaller than the luminance difference between the gradations in the gradation group on the high luminance side. 7 or less predetermined subfield periods are selected from the 7 subfield periods, A 16-level grayscale display is performed by associating each bit of the 4-bit original image data with the selected subfield period, and controlling lighting and non-lighting of pixels in the selected subfield period. Multi-gradation display driving method.

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