JPH0740621B2 - Method for manufacturing surface-emitting type semiconductor laser - Google Patents
Method for manufacturing surface-emitting type semiconductor laserInfo
- Publication number
- JPH0740621B2 JPH0740621B2 JP30499686A JP30499686A JPH0740621B2 JP H0740621 B2 JPH0740621 B2 JP H0740621B2 JP 30499686 A JP30499686 A JP 30499686A JP 30499686 A JP30499686 A JP 30499686A JP H0740621 B2 JPH0740621 B2 JP H0740621B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- blocking layer
- type
- semiconductor laser
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
Landscapes
- Semiconductor Lasers (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は内部電流狭窄構造を備えた面発光型半導体レー
ザの製造方法に関する。The present invention relates to a method for manufacturing a surface-emitting type semiconductor laser having an internal current confinement structure.
一般に面発光型半導体レーザは基板表面とエピタキシャ
ル成長層面との間で共振器を形成し、面方向に光を出射
する構造となっており、レーザ素子の2次元アレイ化、
或いはレーザ素子と周辺電子回路との集積化が可能であ
り、また劈開のための手作業を要しないモノリシックな
加工が可能となり、更に単一縦モード発振を得やすく、
そのうえ発光スポットが大きいためビーム出射角が鋭い
等の利点を有しており、近年その開発が進められてい
る。Generally, a surface-emitting type semiconductor laser has a structure in which a resonator is formed between the substrate surface and the epitaxial growth layer surface and emits light in the surface direction.
Alternatively, it is possible to integrate the laser element and the peripheral electronic circuit, and it becomes possible to perform monolithic processing that does not require manual work for cleavage, and it is easy to obtain single longitudinal mode oscillation.
In addition, since the light emission spot is large, it has advantages such as a sharp beam emission angle, and the development thereof has been advanced in recent years.
ところでこのような面発光型半導体レーザにおいても電
流密度を部分的に集中させ得て閾値電流の低下、発光効
率の向上が図れる内部電流狭窄構造の採用が試みられて
いる。Even in such a surface-emitting type semiconductor laser, it has been attempted to adopt an internal current confinement structure capable of partially concentrating the current density to reduce the threshold current and improve the light emission efficiency.
内部電流狭窄構造自体はインナーストライプ型の半導体
レーザ等においては既に広く採用されており、その製造
に工数が少なくて済むメルトバック法を用いることも既
に知られている(昭和58年春季応物学会予稿7P−H−
7)。The internal current confinement structure itself has already been widely adopted in inner stripe type semiconductor lasers and the like, and it is already known to use the meltback method, which requires a small number of man-hours, for manufacturing (Spring Society of Applied Physics, 1983. 7P-H-
7).
第8図は従来のインナーストライプ型半導体レーザの断
面構造図であり、メサストライプ構造を有する導電型が
n型のGaAs基板11上に電導型がp型のAlGaAsからなるブ
ロック層12を形成し、次いで未飽和のGa−As融液に接触
させて全体をメルトバックする。メサ部周面に成長せし
められたp型AlGaAs層は薄いため、この部分で先に基板
11が露出し、V溝11aが形成される。FIG. 8 is a cross-sectional structural view of a conventional inner stripe type semiconductor laser, in which a block layer 12 made of AlGaAs having a conductivity type of p-type is formed on a GaAs substrate 11 having a mesa stripe structure and a conductivity type of n-type. Then, the whole is melted back by contacting with an unsaturated Ga-As melt. Since the p-type AlGaAs layer grown on the peripheral surface of the mesa is thin, the substrate is first formed at this part.
11 is exposed and a V groove 11a is formed.
そこでこれに続いてn型のAlGaAsからなるクラッド層1
3、AlGaAs活性層14、p型のAlGaAsクラッド層15をこの
順序で成長せしめて屈折率導波構造及び電流狭窄構造を
作り付けたインナーストライプ型の半導体レーザを製造
する。Therefore, following this, the cladding layer 1 made of n-type AlGaAs
3, an AlGaAs active layer 14 and a p-type AlGaAs clad layer 15 are grown in this order to manufacture an inner stripe type semiconductor laser having a refractive index guiding structure and a current constriction structure.
ところで上述した如きメルトバック法を利用して電流狭
窄構造を形成する方法は、GaAsからなるメサ部11aを直
接基板11表面に形成する構成をとっているため、基板そ
れ自体を部分的にエッチン除去する面発光型半導体レー
ザにはそのままでは適用出来ないという問題があった。By the way, in the method of forming the current constriction structure using the meltback method as described above, since the mesa portion 11a made of GaAs is directly formed on the surface of the substrate 11, the substrate itself is partially removed by etching. There is a problem that it cannot be applied as it is to the surface emitting semiconductor laser.
本発明はかかる事情に鑑みなされたものであって、その
目的とするところはメルトバック法を利用して内部電流
狭窄構造を容易に作り付け得るようにした面発光型半導
体レーザの製造方法を提供するにある。The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a surface-emitting type semiconductor laser in which an internal current constriction structure can be easily built by using a meltback method. It is in.
本発明の面発光型半導体レーザの製造方法は、基板上に
メルトバックをストップさせるための阻止層及び該阻止
層上に1又は複数の層を形成する第1の結晶成長工程
と、表面の層にメサ部を形成するエッチング工程と、該
メサ部を形成した層上に電流ブロック層を形成した後、
このメサ部及びこれに対応する部分の上記電流ブロック
層を選択的にメルトバックして上記阻止層に達するよう
に凹孔を形成する工程と、該凹孔を埋め戻す態様で上記
電流ブロック層上にクラッド層を形成し、該クラッド層
上に活性層及び他のクラッド層をこの順序に積層形成す
る第2の結晶成長工程と、を有することを特徴とする。A method of manufacturing a surface-emitting type semiconductor laser according to the present invention comprises a blocking layer for stopping meltback on a substrate, a first crystal growth step of forming one or a plurality of layers on the blocking layer, and a surface layer. After an etching step of forming a mesa portion on the film, and forming a current blocking layer on the layer on which the mesa portion is formed,
A step of selectively melting back the current blocking layer in the mesa portion and a portion corresponding to the mesa portion to form a concave hole so as to reach the blocking layer; and a step of backfilling the concave hole on the current blocking layer. And a second crystal growth step of forming an active layer and another cladding layer on the cladding layer in this order.
特に、上記基板の上記凹孔下に上記阻止層に達する窓を
エッチング形成する工程を有し、該阻止層がこのエッチ
ングをストップさせることを特徴とする。In particular, the method is characterized in that a step of etching a window reaching the blocking layer is formed under the concave hole of the substrate, and the blocking layer stops this etching.
本発明方法はこれによって結晶成長工程は2工程で済
み、しかも内部電流狭窄構造により特性の大幅な向上が
図れる。According to the method of the present invention, the crystal growth step can be performed in two steps, and the characteristics can be greatly improved by the internal current confinement structure.
以下本発明をその製造工程を示す図面に基づき具体的に
説明する。第1〜7図は本発明方法の工程図であり、先
ず第1図に示す如く第1の結晶成長工程では液相エピタ
キシャル成長法により電導型がp型のGaAs基板1上に、
電導型が基板1のそれと同じp型のGa1-xAlxAs(x≧0.
1)からなるメルトバック及びエッチングをストップさ
せる阻止層2、p型のGaAsからなり、阻止層2の酸化防
止を兼ねるメサ部形成層3をこの順序に積層形成する。
次いでエッチング工程で第2,3図に示す如く前記メサ部
形成層3の表面の略中央部に直径5〜10μm、高さ0.5
〜2μmのメサ部3aを形成する。The present invention will be specifically described below with reference to the drawings showing the manufacturing process thereof. FIGS. 1 to 7 are process diagrams of the method of the present invention. First, as shown in FIG. 1, in the first crystal growth process, a p-type GaAs substrate 1 of conductivity type is formed by a liquid phase epitaxial growth method.
The conductivity type is the same as that of the substrate 1, that is, p-type Ga 1-x Al x As (x ≧ 0.
A blocking layer 2 for stopping the melt-back and etching of 1) and a mesa portion forming layer 3 of p-type GaAs which also serves as an anti-oxidant of the blocking layer 2 are laminated in this order.
Then, in the etching process, as shown in FIGS. 2 and 3, a diameter of 5 to 10 μm and a height of 0.5 are formed in the substantially central portion of the surface of the mesa portion forming layer 3.
A mesa portion 3a having a thickness of 2 μm is formed.
次いで第2の結晶成長工程では同じく液相エピタキシャ
ル成長法により最初に第4図に示す如くメサ部3aを含む
p型のGaAs層3の全表面にわたって電導型がn型のGa
1-yAlyAs(y≧0.1)からなるブロック層(電流ブロッ
ク層)4を形成した後、選択メルトバック法によって第
5図に示す如く前記メサ部3a及びこれに対応するブロッ
ク層4、メサ部形成層3をその表面側から阻止層2表面
まで円筒状の凹孔3bが形成されるように除去する。Next, in the second crystal growth step, similarly, as shown in FIG. 4, the n-type Ga of the n-type conductivity type is first formed over the entire surface of the p-type GaAs layer 3 including the mesa 3a as shown in FIG.
After forming the block layer (current block layer) 4 made of 1-y Al y As (y ≧ 0.1), the mesa portion 3a and the corresponding block layer 4 as shown in FIG. The mesa portion forming layer 3 is removed from the surface side to the surface of the blocking layer 2 so that a cylindrical concave hole 3b is formed.
メルトバック法はブロック層4を構成するGa1-yAlyAs結
晶と、メサ部形成層3を構成するGaAs結晶とはAs未飽和
融液内におけるメルトバック速度が大きく異なることを
利用する方法であって、ブロック層4表面にAs未飽和の
Ga−As融液を接触させると先ずブロック層4が融け出
し、ブロック層4が所定厚さ融け出すとブロック層4の
膜厚の薄いメサ部3a形成部分ではメサ部3a表面が露出す
る。メサ部3aを構成するGaAs結晶の融け出し速度はAlGa
As結晶のそれよりも著しく大きい結果、メサ部3aが急速
に融け出し、ここに阻止層2表面に達する円筒状の凹孔
3bが形成されることとなるのである。The meltback method utilizes the fact that the Ga 1-y Al y As crystal forming the block layer 4 and the GaAs crystal forming the mesa portion forming layer 3 have large meltback speeds in the As unsaturated melt. And the As unsaturated on the surface of the block layer 4.
When the Ga-As melt is brought into contact, the block layer 4 first melts, and when the block layer 4 melts to a predetermined thickness, the surface of the mesa 3a is exposed in the thin mesa 3a forming portion of the block layer 4. The melting rate of the GaAs crystal forming the mesa 3a is AlGa
As a result of being significantly larger than that of As crystal, the mesa portion 3a melts rapidly, and a cylindrical concave hole reaching the surface of the blocking layer 2 there.
3b will be formed.
引き続いて第6図に示す如く電導型がp型のGa1-zAlzAs
(z≧0.3)からなるクラッド層5を円筒状の凹孔3b内
を充填する態様でブロック層4の表面に所要厚さに形成
して内部電流狭窄構造を構成し、更にその上に電導型が
p型のGa1-wAlwAs(w≦0.15)からなる活性層6、電導
型がn型のGa1-zAlzAsからなるクラッド層7、の3層か
らなるダブルヘテロ接合層を形成し、次いで電導型がn
型のGa1-vAlvAs(v≦0.15)からなるキャップ層8を積
層形成する。Subsequently, as shown in FIG. 6, the conductivity type is p-type Ga 1-z Al z As
An internal current constriction structure is formed by forming a cladding layer 5 made of (z ≧ 0.3) to a required thickness on the surface of the block layer 4 in a manner of filling the cylindrical concave hole 3b, and further forming a conductive type layer thereon. Is a p-type Ga 1-w Al w As (w ≦ 0.15) active layer 6 and a conductivity type is an n-type Ga 1-z Al z As clad layer 7, and is a double heterojunction layer consisting of three layers. Of the conductivity type n
The cap layer 8 made of Ga 1-v Al v As (v ≦ 0.15) of the mold is laminated.
最後に第7図に示す如く基板1の下面及びキャップ層8
上面に夫々電極9u,9dを形成し、電極9uの中央であって
前記した内部電流狭窄部と対応する位置には反射鏡10u
を形成し、また電極9dの中央には基板1を貫通して阻止
層2に達する出射窓1aをエッチング形成し、露出させた
ブロック層2の表面に反射鏡10dを形成して内部電流狭
窄構造を有する面発光型半導体レーザを得る。Finally, as shown in FIG. 7, the lower surface of the substrate 1 and the cap layer 8 are formed.
Electrodes 9u and 9d are formed on the upper surface, and a reflecting mirror 10u is provided at the center of the electrode 9u and at a position corresponding to the internal current constriction.
In addition, an emission window 1a that penetrates the substrate 1 and reaches the blocking layer 2 is formed by etching in the center of the electrode 9d, and a reflecting mirror 10d is formed on the exposed surface of the block layer 2 to form an internal current constriction structure. A surface-emitting type semiconductor laser having
このような面発光型半導体レーザにあっては電極9u,9d
間に所要の電圧を印加することにより、電流は狭窄部を
経て流れ、光は両反射鏡10u,10d間で反復移動して共振
せしめられ、白抜矢符方向に出射せしめられることとな
る。In such surface emitting semiconductor lasers, electrodes 9u and 9d
By applying a required voltage in between, a current flows through the narrowed portion, and light is repeatedly moved between both reflecting mirrors 10u and 10d to be resonated, and emitted in the direction of the white arrow.
次に各層のp型GaAs基板を用いた場合についてその電導
性、成分組成、膜厚について具体的な数値例を示すと次
のとおりである。Next, specific numerical examples of the electric conductivity, component composition, and film thickness in the case of using the p-type GaAs substrate for each layer are as follows.
基板1…p型GaAs基板 阻止層2…p型Ga0.6Al0.4As阻止層(膜厚:1〜10μm以
内) メサ部形成層3…p型GaAsメサ部形成層(膜厚:1.5μm
以内) メサ部3a …直径:5μm,高さ:1μm以内 ブロック層4…n型Ga0.6Al0.4Asブロック層 クラッド層5…p型Ga0.6Al0.4Asクラッド層 活 性 層6…p型Ga0.9Al0.1As活性層 クラッド層7…n型Ga0.6Al0.4Asクラッド層 キャップ層8…n型Ga0.85Al0.15Asキャップ層 なお上述の実施例では基板にp型のGaAsを用いる場合に
つき説明したがn型のGaAsを用いてもよく、この場合は
上記各層のp型はn型に、またn型はp型にすればよ
い。Substrate 1 ... p-type GaAs substrate Blocking layer 2 ... p-type Ga 0.6 Al 0.4 As blocking layer (film thickness: within 1 to 10 μm) Mesa portion forming layer 3 ... p-type GaAs mesa portion forming layer (film thickness: 1.5 μm
Mesa part 3a… Diameter: 5μm, Height: within 1μm Block layer 4… n-type Ga 0.6 Al 0.4 As block layer clad layer 5… p-type Ga 0.6 Al 0.4 As clad layer active layer 6… p-type Ga 0.9 Al 0.1 As active layer Clad layer 7 ... N-type Ga 0.6 Al 0.4 As clad layer Cap layer 8 ... N-type Ga 0.85 Al 0.15 As cap layer In the above-mentioned embodiment, the case of using p-type GaAs for the substrate has been described. N-type GaAs may be used. In this case, the p-type of each of the above layers may be n-type, and the n-type may be p-type.
また上記実施例ではGaAs系の面発光型半導体レーザを製
造する場合について説明したが、これに限らず、例えば
InP系の面発光型半導体レーザについても適用し得るこ
とは勿論である。In the above embodiment, the case of manufacturing a GaAs surface emitting semiconductor laser has been described.
Of course, it can be applied to an InP-based surface-emitting type semiconductor laser.
以上の如く本発明方法に依れば第1,第2の結晶成長工程
とメサ部形成のためのエッチング工程の三工程に依って
内部電流狭窄構造を備えた面発光型半導体レーザを製造
することが可能となり、製造工程が簡略化され、しかも
特性の大幅な向上を図ることが出来る優れた効果を奏す
る。As described above, according to the method of the present invention, a surface-emitting type semiconductor laser having an internal current confinement structure is manufactured by the three steps of the first and second crystal growth steps and the etching step for forming the mesa portion. And the manufacturing process is simplified, and the characteristics can be greatly improved, which is an excellent effect.
第1〜7図は本発明方法の製造工程を示す説明図、第8
図は従来の内部電流狭窄構造を備えたインナーストライ
プ型半導体レーザの断面構造図である。 1…基板、2…阻止層、3…メサ部形成層、3a…メサ
部、3b…凹孔、4…ブロック層、5…クラッド層、6…
活性層、7…クラッド層、8…キャップ層1 to 7 are explanatory views showing the manufacturing process of the method of the present invention, and FIG.
FIG. 1 is a sectional structural view of an inner stripe type semiconductor laser having a conventional internal current confinement structure. 1 ... Substrate, 2 ... Blocking layer, 3 ... Mesa portion forming layer, 3a ... Mesa portion, 3b ... Recessed hole, 4 ... Block layer, 5 ... Clad layer, 6 ...
Active layer, 7 ... Clad layer, 8 ... Cap layer
Claims (2)
めの阻止層及び該阻止層上に1又は複数の層を形成する
第1の結晶成長工程と、表面の層にメサ部を形成するエ
ッチング工程と、該メサ部を形成した層上に電流ブロッ
ク層を形成した後、このメサ部及びこれに対応する部分
の上記電流ブロック層を選択的にメルトバックして上記
阻止層に達するように凹孔を形成する工程と、該凹孔を
埋め戻す態様で上記電流ブロック層上にクラッド層を形
成し、該クラッド層上に活性層及び他のクラッド層をこ
の順序に積層形成する第2の結晶成長工程と、を有する
ことを特徴とする面発光型半導体レーザの製造方法。1. A first crystal growth step of forming a blocking layer for stopping meltback on a substrate and one or a plurality of layers on the blocking layer, and an etching step of forming a mesa portion in a surface layer. And forming a current blocking layer on the layer on which the mesa portion is formed, and then selectively melting back the current blocking layer in the mesa portion and the portion corresponding to the mesa portion so as to reach the blocking layer. A second crystal growth in which a clad layer is formed on the current blocking layer in a manner of backfilling the concave hole, and an active layer and another clad layer are laminated in this order on the clad layer. And a step of manufacturing a surface-emitting type semiconductor laser.
る窓をエッチング形成する工程を有し、該阻止層がこの
エッチングをストップさせることを特徴とする請求項1
記載の面発光型半導体レーザの製造方法。2. A step of etching a window reaching the blocking layer under the recessed hole of the substrate, wherein the blocking layer stops the etching.
A method for manufacturing the surface-emitting type semiconductor laser described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30499686A JPH0740621B2 (en) | 1986-12-20 | 1986-12-20 | Method for manufacturing surface-emitting type semiconductor laser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30499686A JPH0740621B2 (en) | 1986-12-20 | 1986-12-20 | Method for manufacturing surface-emitting type semiconductor laser |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63157489A JPS63157489A (en) | 1988-06-30 |
JPH0740621B2 true JPH0740621B2 (en) | 1995-05-01 |
Family
ID=17939822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30499686A Expired - Fee Related JPH0740621B2 (en) | 1986-12-20 | 1986-12-20 | Method for manufacturing surface-emitting type semiconductor laser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0740621B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0247886A (en) * | 1988-08-09 | 1990-02-16 | Res Dev Corp Of Japan | Manufacture of surface emission type semiconductor laser |
JPH0252486A (en) * | 1988-08-17 | 1990-02-22 | Res Dev Corp Of Japan | Manufacture of surface-emission type semiconductor laser |
-
1986
- 1986-12-20 JP JP30499686A patent/JPH0740621B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPS63157489A (en) | 1988-06-30 |
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