JPH073852B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH073852B2
JPH073852B2 JP60107588A JP10758885A JPH073852B2 JP H073852 B2 JPH073852 B2 JP H073852B2 JP 60107588 A JP60107588 A JP 60107588A JP 10758885 A JP10758885 A JP 10758885A JP H073852 B2 JPH073852 B2 JP H073852B2
Authority
JP
Japan
Prior art keywords
insulating film
oxide
semiconductor device
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60107588A
Other languages
Japanese (ja)
Other versions
JPS61265860A (en
Inventor
千里 橋本
秀男 及川
中八郎 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60107588A priority Critical patent/JPH073852B2/en
Publication of JPS61265860A publication Critical patent/JPS61265860A/en
Publication of JPH073852B2 publication Critical patent/JPH073852B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置、特に絶縁膜が半導体層又は導電体
層でサンドイッチ状に挟まれた3層積層体を含む半導体
装置に関し、特にその3層積層体で構成されるキャパシ
タの単位面積当たりのキャパシタンスが非常に大きな半
導体装置の特性改善に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a three-layer laminate in which an insulating film is sandwiched between semiconductor layers or conductor layers, and more particularly to the three-layer laminate. The present invention relates to improving the characteristics of a semiconductor device in which the capacitance of a capacitor formed of a body is very large per unit area.

従来の技術 最近の半導体分野においては高集積化、小型化、高速動
作化などの動向がみられ、それに伴ってIC、LSIなどが
発展してきた。即ち、これらの使用によれば、システム
の小型化、高性能化、経済性の向上等各種の利益を期待
することができ、メモリー用、ロジック回路用、マイク
ロコンピュータ用等の広い適用分野を有している。
2. Description of the Related Art In the recent semiconductor field, trends such as high integration, miniaturization, and high speed operation have been observed, and IC and LSI have been developed accordingly. That is, by using these, various benefits such as system miniaturization, high performance, and improvement in economic efficiency can be expected, and there are wide application fields such as memory, logic circuit, and microcomputer. is doing.

メモリー用ICとしては、バイポーラIC、MOSICなどがよ
く知られているが、特に後者は前者に比して高速動作性
の点では劣るものの、素子間のアイソレーションが不要
であり、MOSFETのエンハンスメント特性がスイッチング
に適しており、消費電力が少なく、ゲート容量の蓄積電
荷による一時メモリーの作用を有することからダイナミ
ックメモリー回路を得るために広く利用されている。
As ICs for memory, bipolar ICs, MOSICs, etc. are well known. Especially, the latter is inferior to the former in terms of high-speed operability, but it does not require isolation between elements and enhances the MOSFET's enhancement characteristics. Is suitable for switching, has low power consumption, and has a function of a temporary memory due to accumulated charges of gate capacitance, and is therefore widely used for obtaining a dynamic memory circuit.

このように、半導体デバイスを中心とする電子デバイス
の進歩は著しく、それに伴って要求も一段と厳しくなっ
てきているが、これら要求を満たすためには、能動素子
部分に関る改良もさることながら、抵抗、キャパシタな
どの受動素子の改良も上記改良と並行して行わなければ
ならない重要な課題である。
In this way, the progress of electronic devices centering on semiconductor devices is remarkable, and the requirements are becoming more and more stringent with it, but in order to meet these requirements, not only improvements related to the active element part, Improvement of passive elements such as resistors and capacitors is also an important issue that must be done in parallel with the above improvement.

従来、絶縁膜が半導体層又は導電体層でサンドイッチ状
に挟まれた3層積層体が、様々な半導体装置に使われて
いるが、最近特に注目されているのは上述のようなMOS
ダイナミックメモリの電荷蓄積用キャパシタとして用い
られるものである。即ち、この種のメモリの高集積化は
近年著しいが、それに伴って該キャパシタの面積も縮小
しなければならない。
Conventionally, a three-layer laminated body in which an insulating film is sandwiched between semiconductor layers or conductor layers has been used in various semiconductor devices. Recently, attention has been paid particularly to the above-mentioned MOS.
It is used as a charge storage capacitor of a dynamic memory. That is, although the high integration of this type of memory has been remarkable in recent years, the area of the capacitor must be reduced accordingly.

ところが、面積を縮小しても該キャパシタのキャパシタ
ンスは回路動作上、それ程減少させることができない。
そこで、この問題を解決するための一方法として、該3
層積層体の絶縁膜として誘電率の高い、例えば酸化タン
タル、酸化ニオブ、酸化チタン、酸化ハフニウム、酸化
ジルコニウム、酸化アルミニウム等を用いることが検討
されている。
However, even if the area is reduced, the capacitance of the capacitor cannot be reduced so much in terms of circuit operation.
Therefore, as one method for solving this problem,
It has been considered to use, for example, tantalum oxide, niobium oxide, titanium oxide, hafnium oxide, zirconium oxide, or aluminum oxide having a high dielectric constant as the insulating film of the layer stack.

従来、このような用途に用いられていた絶縁膜は、リー
ク電流の大きいことが欠点であった。この欠点を克服す
るため、比較的リーク電流の小さい陽極酸化膜を使う方
法〔例えば、IEEEトランスアクションズ オン エレク
トロン.デバイスズ(Trans.Electron.Devices),第ED
-29巻,pp.368-376,1982.参照〕や、上記酸化物膜と、リ
ーク電流の極めて小さいシリコン熱酸化膜との2層膜を
使う方法〔例えば、プロシーディングズ オブ シンポ
ジウム オン VLSI テクノロジー(Proc.Symp.VLSI T
ech.),pp.86-87,1983.参照〕等の検討が行なわれてい
る。
Conventionally, the insulating film used for such a purpose has a drawback that the leak current is large. To overcome this drawback, a method using an anodic oxide film with a relatively small leak current [eg, IEEE Transactions on Electron. Devices (Trans.Electron.Devices), ED
-29, pp.368-376, 1982.] or a method of using a two-layer film of the above oxide film and a silicon thermal oxide film with an extremely small leak current [eg, Proceedings of Symposium on VLSI Technology]. (Proc.Symp.VLSI T
ech.), pp.86-87, 1983.] and the like.

しかし、前者では電解液を用いているため、該電解液か
らの汚染の心配があり、また後者においてはシリコン熱
酸化膜の誘電率が低いため、実効的な誘電率が減少して
しまう等の欠点があり、いずれも満足できるものではな
かった。
However, since the former uses an electrolytic solution, there is a risk of contamination from the electrolytic solution, and the latter has a low dielectric constant of the silicon thermal oxide film, so that the effective dielectric constant decreases. There were drawbacks and none were satisfactory.

発明が解決しようとする問題点 以上述べたように電子計算機用のMOSダイナミックメモ
リーなどにおいては、その小型化、高集積化の要求か
ら、キャパシタの面積の縮小する必要がある。しかしな
がら、そのキャパシタンスは回路動作上の理由からそれ
程小さくすることはできない。
Problems to be Solved by the Invention As described above, in MOS dynamic memories for electronic computers and the like, it is necessary to reduce the area of capacitors because of the demand for miniaturization and high integration. However, its capacitance cannot be so small for reasons of circuit operation.

そこで、単位面積当たりのキャパシタンスの大きなキャ
パシタを開発する必要が生じ、そのために上記のような
各種方法が提案されたが、今のところ満足し得るものは
得られていない。
Therefore, it becomes necessary to develop a capacitor having a large capacitance per unit area, and various methods as described above have been proposed for that purpose, but no satisfactory method has been obtained so far.

一方、上記のような2つの文献に開示された解決法を利
用することなしに、通常のスパッタ法、蒸着法等で形成
した絶縁膜では、リーク電流が大きすぎ、実用化不可能
であった。
On the other hand, an insulating film formed by a usual sputtering method, a vapor deposition method or the like without utilizing the solutions disclosed in the above two documents was too large in leak current and could not be put into practical use. .

そこで、本発明の第1の目的は、絶縁膜のリーク電流を
減少させることにより、単位面積当たりのキャパシタン
スが大巾に改善された、該絶縁膜を半導体層又は導電体
層でサンドイッチ状に挟んだ3層積層体をキャパシタと
して含む半導体装置を提供することにある。
Therefore, a first object of the present invention is to sandwich the insulating film between a semiconductor layer or a conductor layer in which the capacitance per unit area is significantly improved by reducing the leak current of the insulating film. Another object of the present invention is to provide a semiconductor device including the three-layer laminated body as a capacitor.

また、本発明の第2の目的は上記のようなキャパシタを
含む半導体装置の製造方法を提供することである。
A second object of the present invention is to provide a method of manufacturing a semiconductor device including the above capacitor.

問題点を解決するための手段 本発明者等は上記のような3層積層構造のキャパシタを
有する半導体装置の上記のような現状に鑑みて、通常の
スパッタ法、蒸着法等で形成した絶縁膜のリーク電流を
小さくすべく種々検討した結果、該絶縁膜材料の純度を
高めることが極めて有利であることを見出し、本発明を
完成した。
Means for Solving the Problems In view of the above-mentioned present situation of the semiconductor device having the capacitor having the three-layer laminated structure as described above, the present inventors have made an insulating film formed by a usual sputtering method, an evaporation method or the like. As a result of various investigations to reduce the leakage current of, the inventors have found that it is extremely advantageous to increase the purity of the insulating film material, and have completed the present invention.

即ち、本発明の半導体装置は、第1の半導体層又は導電
体層と、その上に形成された絶縁膜と、該絶縁膜上に設
けられた第2の半導体層又は導電体層の3層積層体を含
む半導体装置において、前記絶縁膜がアルカリ金属、ア
ルカリ土類金属、重金属、半導体物質および放射性元素
を実質的に含まない高純度の膜であることを特徴とする
ものである。
That is, the semiconductor device of the present invention has a three-layer structure including a first semiconductor layer or a conductor layer, an insulating film formed thereon, and a second semiconductor layer or a conductor layer provided on the insulating film. In a semiconductor device including a laminated body, the insulating film is a high-purity film that is substantially free of alkali metals, alkaline earth metals, heavy metals, semiconductor substances and radioactive elements.

本発明の半導体装置において有用な絶縁膜材料としては
誘電率の高い絶縁材料、例えば酸化タンタル、酸化ニオ
ブ、酸化チタン、酸化ハフニウム、酸化ジルコニウム、
酸化アルミニウム等が例示できる。これらにおいてキャ
パシタンスに対し有害な作用を及ぼす、即ちキャパシタ
ンスを下げる恐れのある不純物としてはナトリウム、カ
リウム等のアルカリ金属、カルシウム等のアルカリ土類
金属、クロム、鉄、ニッケル等の重金属の他、モリブデ
ン、ニオブ、タングステン、ジルコニウムなどの金属、
シリコン等の半導体あるいはウラン等の放射性元素など
である。
As the insulating film material useful in the semiconductor device of the present invention, an insulating material having a high dielectric constant, such as tantalum oxide, niobium oxide, titanium oxide, hafnium oxide, zirconium oxide,
Aluminum oxide etc. can be illustrated. Impurities that have a detrimental effect on capacitance, that is, that may lower the capacitance, include alkali metals such as sodium and potassium, alkaline earth metals such as calcium, heavy metals such as chromium, iron and nickel, and molybdenum, Metals such as niobium, tungsten, zirconium,
It is a semiconductor such as silicon or a radioactive element such as uranium.

また、本発明における絶縁体膜は上記のような各種原料
の少なくとも1種の単層(複合層を含む)もしくは複数
の層からなる積層構造を有していてもよい。
Further, the insulating film in the present invention may have a single layer (including a composite layer) of at least one kind of various raw materials as described above or a laminated structure composed of a plurality of layers.

このように本発明に従う高純度の絶縁膜は以下のように
して作製することができる。即ち、反応性スパッタ法、
熱酸化法、化学気相成長法、蒸着法等各種の方法を利用
できるが、絶縁膜の純度を高いものに維持し得るような
工夫が必要である。
Thus, the high-purity insulating film according to the present invention can be manufactured as follows. That is, the reactive sputtering method,
Various methods such as a thermal oxidation method, a chemical vapor deposition method, and a vapor deposition method can be used, but it is necessary to devise such that the purity of the insulating film can be maintained high.

例えば、反応性スパッタ法で行う場合、半導体基板上に
あるい導電体層上に、高純度の金属をターゲットとし、
アルゴンと酸素との混合ガス雰囲気中で反応性スパッタ
して対応する酸化物絶縁膜を得るが、該金属ターゲット
としては金属を10-4Torr以上の高真空条件下で電子ビー
ム溶解してインゴットを形成する。この際該金属の融点
よりも低い融点を有する不純物は蒸発により除去され
る。この操作を少なくとも1回行うことにより高純度の
金属インゴットが得られるので、これを圧延、加工して
ターゲットとする。このものを蒸着源として使用し、後
に熱酸化するなどの方法も当然可能である。
For example, when the reactive sputtering method is used, a high-purity metal is used as a target on the conductor layer on the semiconductor substrate,
A corresponding oxide insulating film is obtained by reactive sputtering in a mixed gas atmosphere of argon and oxygen.The metal target is an ingot obtained by melting a metal with an electron beam under a high vacuum condition of 10 −4 Torr or more. Form. At this time, impurities having a melting point lower than that of the metal are removed by evaporation. By performing this operation at least once, a high-purity metal ingot can be obtained, and this is rolled and processed to be a target. Of course, a method of using this as a vapor deposition source and then performing thermal oxidation is possible.

また、化学気相成長法ではハロゲン化物、例えば塩化物
などの他メチル、エチルなどの低級アルキル基を含む有
機金属化合物が原料として使用され、熱分解、光による
分解により、金属膜の形成後酸化するか、あるいは酸素
雰囲気下で分解・酸化させて直接金属酸化物を得ること
ができる。この方法においても高純度の原料を使用する
ことにより本発明の目的とする高純度絶縁膜を得ること
が可能となる。
Further, in the chemical vapor deposition method, halides such as chlorides and other organometallic compounds containing a lower alkyl group such as methyl and ethyl are used as raw materials, and thermal decomposition and photodecomposition cause oxidation after the formation of a metal film. Alternatively, the metal oxide can be directly obtained by decomposing and oxidizing in an oxygen atmosphere. Also in this method, by using a high-purity raw material, it is possible to obtain the high-purity insulating film which is the object of the present invention.

以上の絶縁膜形成操作は、装置内を清浄に保ち、これが
汚染されないように十分に注意する必要がある。
It is necessary to keep the inside of the device clean in the above-mentioned insulating film forming operation and take sufficient care not to contaminate it.

作用 本発明で目的とする単位面積当たりの大きなキャパシタ
ンスを有するキャパシタを得るためには、絶縁膜のリー
ク電流を下げることが必要である。
Action To obtain a capacitor having a large capacitance per unit area, which is the object of the present invention, it is necessary to reduce the leak current of the insulating film.

即ち、本発明者等の知見によれば、既に述べた陽極酸化
膜を用いたり、シリコン熱酸化膜を併用したりする方法
を採用することなしに、通常のスパッタ法等で形成した
絶縁膜はリーク電流が大きく、その理由は該絶縁膜の純
度が低いことにあることがわかった。
That is, according to the knowledge of the present inventors, an insulating film formed by a normal sputtering method or the like without using the above-described method of using an anodized film or using a silicon thermal oxide film together It was found that the leak current was large and the reason was that the purity of the insulating film was low.

従って、通常の成膜法によっても、その純度さえ確保す
れば、特別な成膜法を利用したり、他の膜を併用したり
しなくとも、十分な単位面積当たりの大きなキャパシタ
ンスを得ることができる。このような観点からキャパシ
タの改良を試みた例は今のところ知られていない。
Therefore, even by the ordinary film forming method, as long as its purity is secured, a sufficient large capacitance per unit area can be obtained without using a special film forming method or using another film together. it can. From this point of view, an example of trying to improve the capacitor has not been known so far.

例えば、通常市販のタンタルターゲットをアルゴンと酸
素とを含む雰囲気中でスパッタして酸化タンタルをシリ
コン基板上に形成し、その上にアルミニウム層を形成し
た3層積層体からなるキャパシタのリーク電流特性は第
2図の曲線aに示すようになり、このとき使用したタン
タルターゲット中の主な不純物の濃度は以下の表の「従
来のターゲット」の欄に示すようなものであった。
For example, a leakage current characteristic of a capacitor composed of a three-layer laminated body in which a commercially available tantalum target is sputtered in an atmosphere containing argon and oxygen to form tantalum oxide on a silicon substrate, and an aluminum layer is formed thereon is The curve a in FIG. 2 was obtained, and the concentration of main impurities in the tantalum target used at this time was as shown in the column of "conventional target" in the table below.

上記表の結果はタンタルに関する分析結果であるが、不
純物元素の許容存在率の上限が該表の「本発明のターゲ
ット」の欄に示す数値であって、これについてはタンタ
ル以外のニオブ、チタン、ハフニウム、ジルコニウム、
アルミニウムについても同様である。勿論、ターゲット
元素と不純物とが一致する(例えばニオブ、ジルコニウ
ム)場合には前記不純物としての要件を満たす必要はな
い。
Although the results in the above table are the analysis results for tantalum, the upper limit of the allowable abundance of impurity elements is the numerical value shown in the column of "Target of the present invention" in the table, and niobium other than tantalum, titanium, Hafnium, zirconium,
The same applies to aluminum. Of course, when the target element and the impurity match (for example, niobium or zirconium), it is not necessary to satisfy the requirement as the impurity.

本発明において上記不純物の上限は臨界的であり、目的
とする性能の絶縁膜、ひいては所定物性の半導体装置を
得るためには必須の要件である。
In the present invention, the upper limit of the above impurities is critical, and is an essential requirement for obtaining an insulating film having a desired performance, and thus a semiconductor device having predetermined physical properties.

実施例 以下、実施例により本発明を更に具体的に説明すると共
に、その効果を実証するが、本発明の範囲はこれら実施
例により何等制限されない。
EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples and the effects thereof will be demonstrated, but the scope of the present invention is not limited to these Examples.

第1図に本発明により製作した3層積層体の断面図を示
す。シリコン基板1上に高純度タンタルをターゲットと
し、アルゴンと酸素との混合ガス雰囲気中で反応性スパ
ッタし、酸化タンタル膜2を形成する。次に、酸化タン
タル膜2上にアルミニウムを蒸着により形成し、ホトリ
ソグラフィによりパターニングして上部電極3を形成す
る。こうしてできた半導体装置は、半導体層であるシリ
コン基板1と導電体層であるアルミニウム上部電極3
に、高純度な絶縁膜である酸化タンタル膜2が挟まれて
いる3層積層体を含む半導体装置を構成している。
FIG. 1 shows a sectional view of a three-layer laminate manufactured according to the present invention. Tantalum oxide film 2 is formed on silicon substrate 1 by targeting high-purity tantalum and reactive sputtering in a mixed gas atmosphere of argon and oxygen. Next, aluminum is formed on the tantalum oxide film 2 by vapor deposition and patterned by photolithography to form the upper electrode 3. The semiconductor device thus formed has a silicon substrate 1 as a semiconductor layer and an aluminum upper electrode 3 as a conductor layer.
In addition, a semiconductor device including a three-layer laminated body in which a tantalum oxide film 2 which is a high-purity insulating film is sandwiched is formed.

このとき使用したタンタルターゲットは以下の手順で製
造した。まずタンタル粉末を焼結した後、この焼結体を
10-4Torrの高真空中で電子ビーム溶解して、インゴット
を形成した。このときタンタルの融点より低い融点を持
つ不純物は蒸発してしまい除去された。電子ビーム溶解
は1回でも効果があるが、繰返すごとに純度は向上する
ので、本実施例では3回行なった。その後、該インゴッ
トを圧延し、加工してターゲットを形成した。該ターゲ
ット中の主な不純物の濃度は前記表の「本発明のターゲ
ット」の欄に示す通りであった。即ち、カルシウム、ナ
トリウム、カリウム等のアルカリ金属もしくはアルカリ
土類金属は0.1ppm以下であり、従来のターゲットよりも
1桁以上減少している。又、クロム、鉄、ニッケル等の
重金属は0.5ppm以下であり、従来のターゲットよりも2
桁程度減少している。シリコン等の半導体は0.05ppm以
下であり、従来のターゲットよりも2桁以上減少してい
る。ウラン等の放射性元素に至っては0.0005ppm以下で
あり、従来のターゲットより3桁程度減少している。酸
化タンタル膜2の不純物濃度も概ね同様であった。これ
はスパッタ装置内を清浄に保ち、シリコン基板1を汚染
のないように極めて慎重に扱うことで達成できた。
The tantalum target used at this time was manufactured by the following procedure. First, after tantalum powder is sintered, this sintered body is
An ingot was formed by electron beam melting in a high vacuum of 10 -4 Torr. At this time, impurities having a melting point lower than that of tantalum were evaporated and removed. Although the electron beam melting is effective even once, the purity is improved with each repetition, so that the melting was performed three times in this example. Then, the ingot was rolled and processed to form a target. The concentrations of main impurities in the target were as shown in the column of "Target of the present invention" in the above table. That is, the amount of alkali metals or alkaline earth metals such as calcium, sodium and potassium is 0.1 ppm or less, which is decreased by one digit or more as compared with the conventional target. Also, heavy metals such as chromium, iron, and nickel are less than 0.5ppm, which is more than that of conventional targets.
It has decreased by an order of magnitude. The amount of semiconductors such as silicon is 0.05 ppm or less, which is more than two orders of magnitude lower than conventional targets. The amount of radioactive elements such as uranium is 0.0005ppm or less, which is about 3 orders of magnitude less than conventional targets. The impurity concentration of the tantalum oxide film 2 was almost the same. This could be achieved by keeping the inside of the sputter device clean and handling the silicon substrate 1 very carefully to avoid contamination.

さて該3層積層体よりなるキャパシタのリーク電流特性
を第2図の曲線bに示す。この図より従来のキャパシタ
に比して格段にリーク電流が減少していることは明らか
である。
The curve b of FIG. 2 shows the leakage current characteristic of the capacitor composed of the three-layer laminate. It is clear from this figure that the leakage current is significantly reduced compared to the conventional capacitor.

第2図のリーク電流特性によれば、従来例のキャパシタ
のリーク電流を示す曲線aも本実施例のキャパシタのリ
ーク電流を示す曲線bも、曲線の傾き自体にはそれ程違
いがない。いずれも絶縁膜中のトラップを介しての電子
のホッピング伝導による電流であるプール−フレンケル
型の電流と考えられる。従って本実施例のリーク電流が
小さいのはアルカリ金属、重金属、半導体等の不純物濃
度が低くなったため、絶縁膜中のトラップ密度が減った
ことによると考えられる。
According to the leakage current characteristics of FIG. 2, there is not much difference between the curve a indicating the leakage current of the capacitor of the conventional example and the curve b indicating the leakage current of the capacitor of the present embodiment, the slope itself. Both are considered to be pool-Frenkel type currents, which are currents due to hopping conduction of electrons through traps in the insulating film. Therefore, it is considered that the small leak current in this example is because the trap density in the insulating film is reduced because the impurity concentration of the alkali metal, the heavy metal, the semiconductor and the like is low.

上記実施例では、本発明の概念を下部電極としてはシリ
コン基板、上部電極としてはアルミニウムを用いて説明
したが、下部電極、上部電極共別の半導体、金属あるい
は他の導電性材料であっても同様の結果を与えることを
確認した。又、中間の絶縁膜として酸化タンタルを用い
て説明したが、要は高誘電率の絶縁膜であればよく、そ
の他に酸化ニオブ、酸化チタン、酸化ハフニウム、酸化
ジルコニウム、酸化アルミニウム等でも可能であり、も
ちろん、これらの膜のうちのいくつかによる多層膜ある
いは複合膜であっても同様の効果が得られることも確認
した。又、該絶縁膜の形成法として反応性スパッタ法を
用いて説明したが、該絶縁膜の純度が高純度に保たれる
形成法であれば熱酸化法、化学気相成長法、蒸着法のい
かなる方法であろうとも本発明の概念に含まれ、同様に
優れた結果を与える。
In the above embodiments, the concept of the present invention has been described using the silicon substrate as the lower electrode and the aluminum as the upper electrode, but the lower electrode and the upper electrode may be different semiconductors, metals or other conductive materials. It was confirmed to give similar results. Further, although tantalum oxide is used as the intermediate insulating film in the description, it suffices that the insulating film has a high dielectric constant, and niobium oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide or the like may be used. Of course, it was also confirmed that a similar effect can be obtained even with a multilayer film or a composite film made of some of these films. Further, although the reactive sputtering method has been used as the method for forming the insulating film, a thermal oxidation method, a chemical vapor deposition method, or a vapor deposition method may be used as long as the forming method can maintain the purity of the insulating film at a high level. Any method is included in the concept of the invention and gives equally good results.

さらに上記実施例では、本発明の概念を単純なキャパシ
タを用いて説明したが、絶縁膜が半導体層又は導電体層
に挟まれた3層積層体を含む半導体装置であれば、いか
なる装置にも本発明の概念を損なうことなく本発明を適
用できることは明らかであり、もちろん溝型MOSキャパ
シタにも適用できる。さらにMOS型FETのゲート部分であ
ってもよいことは言うまでもない。
Furthermore, although the concept of the present invention has been described in the above embodiments using a simple capacitor, any device may be used as long as it is a semiconductor device including a three-layer laminate in which an insulating film is sandwiched between semiconductor layers or conductor layers. It is obvious that the present invention can be applied without impairing the concept of the present invention, and can of course be applied to a groove type MOS capacitor. Needless to say, it may be the gate portion of the MOS type FET.

又、本発明によればリーク電流が減少することに加え
て、絶縁膜中にアルカリ金属、いいかえれば可動電荷が
少ないため、半導体装置の電気特性の経時変化が少な
い、又、放射性元素が殆ど含まれないため半導体装置が
いわゆるソフトエラーを起こさない等の効果もあり、半
導体装置の一層の特性向上がはかれる。
Further, according to the present invention, in addition to the reduction of the leak current, since the alkali metal in the insulating film, in other words, the mobile charge is small, there is little change in the electrical characteristics of the semiconductor device over time, and almost no radioactive element is contained. Therefore, there is an effect that the semiconductor device does not cause a so-called soft error, and the characteristics of the semiconductor device can be further improved.

発明の効果 以上説明したように本発明によれば絶縁膜のリーク電流
を大幅に減少させることができるので、単位面積当たり
のキャパシタンスが非常に大きく、かつ絶縁性に優れ
た、半導体層又は導電体層−絶縁膜−半導体層又は導電
体層の3層積層体が得られる。
EFFECTS OF THE INVENTION As described above, according to the present invention, the leakage current of the insulating film can be significantly reduced, so that the capacitance per unit area is very large, and the semiconductor layer or the conductor is excellent in insulation. A three-layer laminate of layer-insulating film-semiconductor layer or conductor layer is obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図はキャパシタを構成する3層積層体の断面図であ
り、 第2図は本発明及び従来例において形成された、第1図
に示す如きキャパシタのリーク電流特性図である。 (主な参照番号) 1……シリコン基板、2……酸化タンタル膜、3……ア
ルミニウム上部電極
FIG. 1 is a cross-sectional view of a three-layer laminated body forming a capacitor, and FIG. 2 is a leakage current characteristic diagram of the capacitor as shown in FIG. 1 formed in the present invention and the conventional example. (Main reference numbers) 1 ... Silicon substrate, 2 ... Tantalum oxide film, 3 ... Aluminum upper electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】第1の半導体層又は導電体層と、その上に
形成された絶縁膜と、該絶縁膜上に設けられた第2の半
導体層又は導電体層の3層積層体を含む半導体装置にお
いて、 前記絶縁膜がシリコン熱酸化膜よりも高い誘電率をもつ
材料を少なくとも1種類は構成物質として含み、 かつ前記絶縁膜が以下の元素を以下のような量を上限と
して含有するものであることを特徴とする上記半導体装
置。
1. A three-layer laminate of a first semiconductor layer or a conductor layer, an insulating film formed thereon, and a second semiconductor layer or a conductor layer provided on the insulating film. In a semiconductor device, the insulating film contains at least one kind of material having a higher dielectric constant than a silicon thermal oxide film as a constituent substance, and the insulating film contains the following elements with the following amounts as upper limits. The semiconductor device described above.
【請求項2】前記絶縁膜が酸化タンタル、酸化ニオブ、
酸化チタン、酸化ハフニウムまたは酸化アルミニウムの
うち少なくとも1種類を構成物質として含んだ膜である
ことを特徴とする特許請求の範囲第1項記載の半導体装
置。
2. The insulating film comprises tantalum oxide, niobium oxide,
The semiconductor device according to claim 1, which is a film containing at least one of titanium oxide, hafnium oxide, and aluminum oxide as a constituent material.
【請求項3】第1の半導体層又は導電体層上に絶縁膜と
第2の半導体層又は導電体層をこの順序で形成すること
により得られる3層積層体を含む半導体装置の製造方法
において、 前記絶縁膜がシリコン熱酸化膜よりも高い誘電率をもつ
材料を少なくとも1種類は構成物質として含む膜であ
り、かつ以下の元素を以下のような量を上限として含有
する原料を用いて反応性スパッタ法、熱酸化法、蒸着法
または化学気相成長法により形成されることを特徴とす
る上記半導体装置の製造方法。
3. A method of manufacturing a semiconductor device including a three-layer laminated body obtained by forming an insulating film and a second semiconductor layer or conductor layer on a first semiconductor layer or conductor layer in this order. , The insulating film is a film containing at least one kind of material having a dielectric constant higher than that of the thermal silicon oxide film as a constituent substance, and reacts using a raw material containing the following elements with the following amounts as upper limits. The method for manufacturing a semiconductor device as described above, which is formed by a reactive sputtering method, a thermal oxidation method, a vapor deposition method or a chemical vapor deposition method.
【請求項4】前記絶縁膜原料金属の精製が、高真空条件
下での少なくとも1回の電子ビーム溶解処理により行な
われることを特徴とする特許請求の範囲第3項記載の方
法。
4. The method according to claim 3, wherein the metal for the insulating film raw material is purified by at least one electron beam melting treatment under a high vacuum condition.
JP60107588A 1985-05-20 1985-05-20 Semiconductor device and manufacturing method thereof Expired - Lifetime JPH073852B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60107588A JPH073852B2 (en) 1985-05-20 1985-05-20 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60107588A JPH073852B2 (en) 1985-05-20 1985-05-20 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS61265860A JPS61265860A (en) 1986-11-25
JPH073852B2 true JPH073852B2 (en) 1995-01-18

Family

ID=14462960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60107588A Expired - Lifetime JPH073852B2 (en) 1985-05-20 1985-05-20 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH073852B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113264A (en) * 1980-12-29 1982-07-14 Fujitsu Ltd Manufacture of mis type capacitor
JPS6060750A (en) * 1983-09-14 1985-04-08 Hitachi Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS61265860A (en) 1986-11-25

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