KR940008370B1 - Semiconductor device - Google Patents
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- KR940008370B1 KR940008370B1 KR1019870007495A KR870007495A KR940008370B1 KR 940008370 B1 KR940008370 B1 KR 940008370B1 KR 1019870007495 A KR1019870007495 A KR 1019870007495A KR 870007495 A KR870007495 A KR 870007495A KR 940008370 B1 KR940008370 B1 KR 940008370B1
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- 239000004065 semiconductor Substances 0.000 title claims description 50
- 239000003990 capacitor Substances 0.000 claims description 75
- 238000006243 chemical reaction Methods 0.000 claims description 59
- 230000002265 prevention Effects 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 27
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000005368 silicate glass Substances 0.000 claims description 9
- 229910052715 tantalum Inorganic materials 0.000 claims description 9
- 229910016006 MoSi Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 229910008484 TiSi Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- -1 Si 3 N 4 Inorganic materials 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 7
- 229910052698 phosphorus Inorganic materials 0.000 claims 7
- 239000011574 phosphorus Substances 0.000 claims 7
- 230000001590 oxidative effect Effects 0.000 claims 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 239000010408 film Substances 0.000 description 142
- 238000010438 heat treatment Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- General Physics & Mathematics (AREA)
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Abstract
내용 없음.No content.
Description
제1도는 본 발명의 1실시예의 도시한 단면도.1 is a cross-sectional view of one embodiment of the present invention.
제2도는 본 발명의 효과의 1예를 도시한 그래프.2 is a graph showing an example of the effects of the present invention.
본 발명은 반도체 장치에 관한 것으로서, 특히 고유전율 절연막을 캐패시터용 절연막으로서 사용하는 고용량이며 또한 고신뢰성인 캐패시터를 갖는 반도체 장치에 관한 것이다.BACKGROUND OF THE
LSI(large scale integrated circuit)의 고집적화에 따라서, 그 구성요소인 캐패시터에 있어서도 미세화가 요구되어 왔다. 그 때문에, 비유전율이 22로 종래의 캐패시터용 절연막으로서 사용되는 이산화실리콘(SiO2)의 6배 이상 큰 비유전율을 갖는 산화탄탈륨(Ta2O5)를 사용해서 캐패시터의 용량을 크게 하고, 그것에 의해 반도체 장치의 치수를 축소하려는 시도가, 예를들면 일본국 특허 공개공보 소화58-61634호, 일본국 특허 공개공보 소화59-4152호 등에 기재되어 있다.With high integration of large scale integrated circuits (LSIs), miniaturization has also been required in capacitors as components. Therefore, the capacitance of the capacitor is increased by using tantalum oxide (Ta 2 O 5 ) having a relative dielectric constant of 22 or more and six times larger than that of silicon dioxide (SiO 2 ) used as an insulating film for a capacitor. An attempt to reduce the size of a semiconductor device is described in, for example, Japanese Patent Laid-Open No. 58-61634, Japanese Patent Laid-Open No. 59-4152, and the like.
그러나, 상기 Ta2O5의 일부는 캐패시터 형성후의 MOS LSI의 제조공정중에 있어서 실행되는 열처리에 의해서 상부전극중에 포함되는 원소, 예를들면 실리콘(Si)과 화학적으로 반응해서 Ta로 되어 캐패시터의 절연내압의 저하를 일으킨다. 이 때의 반응은 다음의 식(1)로 나타내진다.However, a part of the Ta 2 O 5 chemically reacts with an element included in the upper electrode, for example, silicon (Si), by the heat treatment performed during the manufacturing process of the MOS LSI after the formation of the capacitor to form Ta to insulate the capacitor. Causes a drop in internal pressure. Reaction at this time is represented by following formula (1).
2Ta2O3+5Si→4Ta+5SiO2…………………………………………………… (1)2Ta 2 O 3 + 5Si → 4Ta + 5SiO 2 . … … … … … … … … … … … … … … … … … … … (One)
반도체 장치의 캐패시터의 상부전극으로서는 반도체 장치의 제조공정에 있어서 가장 화학적으로 안정된 다결정 Si막이 가장 널리 사용되고 있다. 그러나, 캐패시터용 절연막으로서 반도체 장치의 고집적화에 적합한 상기 Ta2O5등의 고유전율 절연막을 사용하면, 상술한 바와 같이 반도체 장치의 제조공정중의 열처리에 의해 다결정 Si막의 Si가 Ta2O5막중으로 확산해서 그 Ta2O5막과 반응해 버린다는 문제가 발생한다.As the upper electrode of the capacitor of the semiconductor device, the most chemically stable polycrystalline Si film is most widely used in the manufacturing process of the semiconductor device. However, when a high dielectric constant insulating film such as Ta 2 O 5 suitable for high integration of a semiconductor device is used as the insulating film for a capacitor, the Si of the polycrystalline Si film is formed in the Ta 2 O 5 film by the heat treatment during the manufacturing process of the semiconductor device as described above. A problem arises in that it diffuses into and reacts with the Ta 2 O 5 film.
따라서, 상기 종래 기술에서는 상부전극의 Si와 Ta2O5막과의 반응을 방지하기 위해서, 화학양론적 조성비보다 낮은 농도의 Si를 포함하는 고융점 금속 또는 그들의 실리사이드 등의 합금을 상부전극으로서 사용하지 않으면 안되었다. 그러나, 상기 Si 농도가 낮은 고융점 금속 또는 그들의 합금은 화학적으로 불안정하고 제조공정중의 열처리에 의해서 용이하게 산화하거나 에칭액 등의 약품에 의해서 부식되기 쉽다는 문제가 있었다.Therefore, in the above prior art, in order to prevent the reaction between the Si and the Ta 2 O 5 film of the upper electrode, an alloy such as a high melting point metal or silicides thereof containing Si having a concentration lower than the stoichiometric composition ratio is used as the upper electrode. I had to do it. However, the high melting point metals or alloys thereof having a low Si concentration have a problem of being chemically unstable and easily oxidized by heat treatment during the manufacturing process or easily corroded by chemicals such as etching solution.
이와 같이, 종래기술에 있어서는 고유전율 절연막을 MOS LSI에 적용하는 것이 곤란하였다. 또, 미국 특허 4,151,607에는 캐패시터의 절연막으로서 SiO2막 대신에 Si3N4막을 사용하는 것이 소요면적의 감소에 유효하다는 것이 기재되어 있다. 그러나, Ta2O5와 실리콘과의 반응에 의해서 발생하는 누설전류의 증가에 대해서는 전혀 기재되어 있지 않다.As described above, in the prior art, it is difficult to apply the high dielectric constant insulating film to the MOS LSI. In addition, US Pat. No. 4,151,607 describes that the use of a Si 3 N 4 film instead of an SiO 2 film as an insulating film of a capacitor is effective for reducing the required area. However, there is no description of the increase in leakage current caused by the reaction of Ta 2 O 5 with silicon.
본 발명의 목적은 Ta2O5등의 고유전율 절연막과 Si를 함유하는 상부전극과의 반응을 방지하고, 캐패시터용 절연막으로서의 고유전율 절연막의 채용을 가능하게 하고, 따라서 반도체 장치의 고집적화를 달성할 수 있는 반도체 장치를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to prevent reaction between a high dielectric constant insulating film such as Ta 2 O 5 and an upper electrode containing Si, and to enable the adoption of a high dielectric constant insulating film as a capacitor insulating film, thereby achieving high integration of a semiconductor device. It is to provide a semiconductor device capable of.
상기 목적을 달성하기 위해서, 본 발명은 실리콘 기판 또는 실리콘을 포함하는 하부전극상에 형성된 고유전율 절연막과 다결정 Si나 고융점 금속 또는 그들의 실리사이드 등의 Si또는 Si를 포함하는 상부전극과의 사이에 반응 방지막으로서 SiO2막이나 질화실리콘(Si3N4)막 등을 얇게 개재시키는 것에 의해서, 해당 캐패시터 형성후의 그 반도체 장치의 제조공정중에 있어서의 열처리에 의해서 상부전극에 포함되는 Si 등의 원소와 고유전율 절연막이 반응하는 것을 방지하는 것을 특징으로 한다.In order to achieve the above object, the present invention reacts between a high-k dielectric insulating film formed on a silicon substrate or a lower electrode containing silicon and an upper electrode containing Si or Si such as polycrystalline Si or a high melting point metal or silicides thereof. By interposing a SiO 2 film, a silicon nitride (Si 3 N 4 ) film, or the like as a thin film, the heat treatment in the manufacturing process of the semiconductor device after the formation of the capacitor, such as Si contained in the upper electrode and intrinsic It is characterized by preventing the electric insulating film from reacting.
또한, 상기 반응 방지막의 막두께는 약 10Å∼100Å으로 하는 것이 바람직하고, 더욱 바람직하게는 20Å∼100Å이다. 막두께가 상기 범위 이하이면, 상부전극중에 포함되는 Si등이 그 막을 통과하여 상기 고유전율 절연막중으로 들어가기 쉽게 되어 반응 방지막으로서 작용하지 않게 된다. 한편, 막두께가 너무 두꺼우면, 캐패시터의 용량이 감소해 버린다.The film thickness of the reaction prevention film is preferably about 10 kPa to 100 kPa, more preferably 20 kPa to 100 kPa. If the film thickness is less than or equal to the above range, Si or the like contained in the upper electrode easily passes through the film and enters into the high dielectric constant insulating film, so that it does not act as a reaction prevention film. On the other hand, if the film thickness is too thick, the capacity of the capacitor decreases.
또한, 상기 반응 방지막의 형성후, 그 반응 방지막이 Si3N4막인 경우는 이 Si3N4을 산화하고, 그 반응 방지막이 SiO2막인 경우는 그 SiO2막을 질화하면 초기 절연파괴가 극도로 감소하여 더욱 우수한 캐패시터를 형성할 수가 있다.After the formation of the reaction prevention film, if the reaction prevention film is a Si 3 N 4 film, the Si 3 N 4 is oxidized, and if the reaction prevention film is a SiO 2 film, the SiO 2 film is nitrided so that the initial breakdown is extremely high. Can be reduced to form better capacitors.
상기 SiO2막이나 Si3N4막 등의 반응 방지막을 고유전율 절연막과 상부전극과의 사이에 배리어층으로서 마련한 것에 의해, 상기 캐패시터 형성후의 반도체 장치의 제조공정중의 열처리에 의해서 상부전극으로부터 고유전율 절연막으로 상부전극에 포함되는 Si 등의 원소가 확산되는 것이 방지되어 그 원소와 고유전율 절연막과의 반응을 방지할 수 있다. 따라서, 캐패시터의 절연내압이 저하하는 일없이 Ta2O5막 등의 고유전율 절연막을 캐패시터용 절연막으로서 사용할 수가 있고, 고용량이고 또한 고신뢰성이 캐패시터를 실현할 수가 있어 LSI의 고집적화에 매우 유효하다.By providing a reaction prevention film such as the SiO 2 film or the Si 3 N 4 film as a barrier layer between the high dielectric constant insulating film and the upper electrode, the film is intrinsic from the upper electrode by heat treatment during the manufacturing process of the semiconductor device after the capacitor formation. The diffusion of an element, such as Si, included in the upper electrode with the dielectric insulating film is prevented, and the reaction between the element and the high dielectric constant insulating film can be prevented. Therefore, a high dielectric constant insulating film such as a Ta 2 O 5 film or the like can be used as the insulating film for the capacitor without lowering the dielectric breakdown voltage of the capacitor, and the capacitor can realize a high capacity and high reliability, which is very effective for high integration of the LSI.
제1도는 본 발명의 1실시예의 캐패시터를 갖는 반도체 장치의 개략 단면도이다.1 is a schematic cross-sectional view of a semiconductor device having a capacitor of one embodiment of the present invention.
도면에 있어서 (1)은 Si기판, (2)는 Si기판(1)상에 자연 산화막으로서 형성된 막두께 약 20Å의 SiO2막, (3)은 SiO2막(2)상에 캐패시터용 절연막으로서 형성된 고유전율을 갖는 막두께 약 200Å의 Ta2O5막, (4)는 Ta2O5막(3)상에 반응 방지막으로서 형성된 막두께 약 30Å의 Si3N4막, (5)는 Si3N4막(4)상에 상부전극으로서 형성된 다결정 Si막을 각각 나타낸다.In Fig. 1, (1) is an Si substrate, (2) is a SiO 2 film having a film thickness of about 20 GPa formed as a natural oxide film on the Si substrate (1), and (3) is an insulating film for capacitors on the SiO 2 film (2). A Ta 2 O 5 film having a high dielectric constant formed thereon of about 200 GPa, (4) is an Si 3 N 4 film having a thickness of about 30 GPa formed as an anti-reaction film on the Ta 2 O 5 film (3), and (5) is Si The polycrystalline Si films formed as upper electrodes on the 3N 4 film 4 are respectively shown.
제1도에 도시한 반도체 장치는 다음과 같이 해서 형성된다. 먼저, Si기판(1)상에 공지의 CVD(화상 기상 성장법)법을 사용해서 캐패시터용 절연막으로서 Ta2O5막(3)을 형성하였다. 또한, 이 Ta2O5막(3)을 형성할 때에 Si기판(1)의 표면이 수증기에 접촉해서 가열되기 때문에, 그 Si기판(1)상에 SiO2막(2)가 자연 산화막으로서 막두께 약 20Å 정도로 형성되었다.The semiconductor device shown in FIG. 1 is formed as follows. First, a Ta 2 O 5 film 3 was formed on the
또한, 상기 Ta2O5막의 다른 형성방법으로서는 Ta의 금속 타겟을 아르곤과 산소의 혼합가스중에서 스퍼터해서 Ta2O5를 형성하는 반응성 스퍼터링법 등이 있다. 이 Ta2O5막을 반응성 스퍼터링법에 의해서 형성하는 경우는 방전에 의한 아르곤과 산소의 플라즈마에 의해서 상기 SiO2막(자연 산화층)이 20Å 정도의 두께로 형성된다.As another method for forming the Ta 2 O 5 film, there is a reactive sputtering method of forming Ta 2 O 5 by sputtering a metal target of Ta in a mixed gas of argon and oxygen. In the case where the Ta 2 O 5 film is formed by the reactive sputtering method, the SiO 2 film (natural oxide layer) is formed to a thickness of about 20 kW by plasma of argon and oxygen caused by discharge.
다음에, Ta2O5막(3)상에 공지의 CVD법에 의해서 반응 방지막으로서 Si3N4막(4)를 막두께 약 30Å 형성하였다. 그 후, 캐패시터용 절연막인 Ta2O5막(3)의 절연내압의 초기저하를 감소시키기 위해서 건조 산소분위기 중에서 1000℃, 30분의 열처리를 실행하고, 반응 방지막인 Si3N4막(4)의 표면을 얇게 산화하였다.Next, a Si 3 N 4 film 4 was formed on the Ta 2 O 5 film 3 by a known CVD method as a reaction prevention film. Subsequently, in order to reduce the initial drop of the dielectric breakdown voltage of the Ta 2 O 5 film 3 which is the insulating film for capacitors, heat treatment was performed at 1000 ° C. for 30 minutes in a dry oxygen atmosphere, and the Si 3 N 4 film as a reaction prevention film (4 ) Surface was thinly oxidized.
다음에, Si3N4막(4)상에 상부전극으로서 다결정 Si막(5)를 형성해서 캐패시터를 형성하였다.Next, a
즉, 본 실시예에서는 캐패시터용 고유전율 절연막인 Ta2O5막(3)과 상부전극의 다결정 Si막(5)와의 사이에 반응 방지막으로 막두께 약 30Å의 Si3N4막(4)을 마련한 것에 의해서, 상기 캐패시터 형성후의 반도체 장치의 제조공정후의 열처리에 의해 다결정 Si막(5)의 Si가 Ta2O5막(3)중으로 확산되어 그 Ta2O5막(3)과 반응하는 것을 방지할 수 있고, 따라서 그 캐패시터의 절연내압의 저하를 방지할 수 있다. 또, 본 실시예에서는 Si기판(1)과 Ta2O5막(3)과의 사이에도 막두께 약 30Å의 SiO2막이 자연 산화층으로서 형성되므로, 상기 제조공정중의 열처리에 의해서 Si기판(1)의 Si가 Ta2O5막(3)중으로 확산해서 그 Ta2O5막(3)과 반응하는 것을 방지할 수 있어 캐패시터의 절연내압의 저하를 방지할 수 있다.That is, in this embodiment, a Si 3 N 4 film 4 having a film thickness of about 30 GPa is formed as a reaction prevention film between the Ta 2 O 5 film 3, which is a high dielectric constant insulating film for capacitors, and the
제2도는 본 실시예에서 도시한 캐패시터에 있어서 그 캐패시터의 제조후에 실행한 열처리(어닐링)의 온도와 누설전류와의 관계를 본 발명에 의해서 반응 방지막을 마련한 경우와 마련하지 않은 경우를 비교해서 도시한 도면이다. 제2도에 있어서, 선 a는 본 발명에 의한 반응 방지막(4)를 갖는 경우, 선 b는 반응 방지막(4)를 갖지 않는 경우를 각각 나타낸다. 또한, 열처리의 조건은 500∼1000℃의 온도 범위이고, 열처리 시간은 30분이었다.FIG. 2 shows a comparison between the case where the reaction prevention film is provided by the present invention and the case where the reaction prevention film is not provided by the present invention in the capacitor shown in this embodiment. One drawing. In FIG. 2, the line a shows the case where the reaction prevention film 4 by this invention does not have the reaction prevention film 4, respectively. In addition, the conditions of heat processing were the temperature range of 500-1000 degreeC, and heat processing time was 30 minutes.
이 제2도의 선 a에서 명확한 바와 같이, 반응 방지막을 갖는 캐패시터에서는 통상의 LSI의 제조공정에 있어서의, 예를들면 불순물의 도우프 등의 열처리 온도인 1000℃의 어닐링을 실행하더라도 누설전류의 증대가 일어나지 않는다. 이것과 비교해서, Ta2O5막상에 반응 방지막이 없는 캐패시터에서는 제2도의 선 b에서 명확한 바와 같이 누설전류는 열처리 온도가 상승하면 급격하게 증대해 버린다.As is clear from the line a of FIG. 2, in the capacitor having the reaction prevention film, the leakage current increases even when annealing at a temperature of 1000 DEG C, which is a heat treatment temperature such as doping of impurities, is performed in a conventional LSI manufacturing process. Does not happen. In comparison with this, in a capacitor without a reaction prevention film on the Ta 2 O 5 film, the leakage current rapidly increases as the heat treatment temperature increases, as is clear from the line b in FIG.
이와 같이, 본 실시예에 의하면, 반응 방지막을 마련하는 것에 의해서, Si 등을 포함하는 상부전극과 캐패시터용 절연막 사이의 반응을 방지할 수 있으므로, 내열성이 높은 고용량 캐패시터를 실현할 수가 있다.As described above, according to this embodiment, by providing the reaction prevention film, the reaction between the upper electrode containing Si and the insulating film for the capacitor can be prevented, whereby a high capacity capacitor having high heat resistance can be realized.
그리고, 제2도에 도시한 결과에서 본 실시예의 캐패시터는 별도의 큰 효과를 갖는 것을 알 수 있다. 즉, 어닐링 온도가 500℃이하의 영역에 있어서도 누설전류값이 반응 방지막의 유무에 따라서 다른 결과가 얻어졌다. 즉, 제2도에서 명확한 바와 같이 본 실시예의 캐패시터는 반응 방지막이 존재하는 것에 의해서, 어닐링 온도가 낮은 경우에 있어서도 높은 경우와 마찬가지로 반응 방지막을 갖지 않는 캐패시터보다도 누설 전류값이 매우 작다. 즉, 본 실시예에서는 캐패시터의 절연막이 Si3N4/Ta2O5/SiO2인 3층 구조로 되어 있는 것에 의해서, 누설전류를 현저하게 감소할 수가 있었다. 또, Ta2O5막상의 Si3N4막(4)의 막두께는 30Å 정도 및 Si기판(1)상에 형성한 SiO2막(2)의 막두께는 20Å 정도로 매우 얇게 형성했으므로, 용량의 감소는 문제로 되지 않는다.In addition, it can be seen from the results shown in FIG. 2 that the capacitor of the present embodiment has a large effect. In other words, even in the region where the annealing temperature was 500 ° C. or less, a result was obtained in which the leakage current value was different depending on the presence or absence of the reaction prevention film. That is, as is clear from Fig. 2, the capacitor of the present embodiment has a smaller leakage current value than the capacitor having no reaction prevention film, similarly to the case where the annealing temperature is high, even when the annealing temperature is low. That is, in this embodiment, the insulating film of the capacitor has a three-layer structure of Si 3 N 4 / Ta 2 O 5 / SiO 2 , whereby the leakage current can be remarkably reduced. In addition, since the film thickness of the Si 3 N 4 film 4 on the Ta 2 O 5 film was about 30 mW and the film thickness of the SiO 2 film 2 formed on the
또한, 상기 실시예에 있어서 반응 방지막으로서 Si3N4막(4) 대신에 SiO2막을 형성한 경우도 마찬가지로 누설전류의 감소가 관측되었다. SiO2막을을 캐패시터의 절연막으로서 사용하는 경우는, 예를들면 CVD법에 의해서 SiO2막을 형성한 후 암모니아 분위기중에서 약 950℃, 30분의 열처리를 실행하여 SiO2막의 표면을 질화해서 초기에 있어서의 절연내압의 저하를 방지하였다.In addition, in the above embodiment, when the SiO 2 film was formed instead of the Si 3 N 4 film 4 as the reaction prevention film, the decrease in the leakage current was similarly observed. In the case where the SiO 2 film is used as the insulating film of the capacitor, for example, after the SiO 2 film is formed by the CVD method, the heat treatment is performed at about 950 ° C. for 30 minutes in an ammonia atmosphere to nitrate the surface of the SiO 2 film. Of the dielectric breakdown voltage was prevented.
본 발명에 있어서, 상기 반응 방지막으로서는 SiO2막 및 Si3N4막 이외에, 예를들면 인 실리케이트 글라스막 등에도 사용할 수가 있다. 이들 반응 방지막의 막두께는 상기한 바와 같이 10Å∼100Å이고, 바람직하게는 20Å∼100Å의 범위에서 선택된다.In the present invention, as the reaction prevention film, in addition to the SiO 2 film and the Si 3 N 4 film, for example, a silicate glass film can be used. The film thickness of these reaction prevention films is 10 kPa-100 kPa as mentioned above, Preferably it is selected in the range of 20 kPa-100 kPa.
상기 실시예에서는 고유전율 절연막의 재료로서 Ta2O5(산화탄탈륨)를 사용하였지만, 그 이외에도 산화니오븀(Nb2O5), 산화티타늄(TiO2), 산화지르코늄(Zr2O5), 산화알루미늄(Al2O3), 산화하프늄(HfO), 산화이트륨(Y2O3) 등의 금속 산화물을 사용하여도 마찬가지의 효과가 얻어졌다.In the above embodiment, Ta 2 O 5 (tantalum oxide) was used as the material of the high dielectric constant insulating film. In addition, niobium oxide (Nb 2 O 5 ), titanium oxide (TiO 2 ), zirconium oxide (Zr 2 O 5 ), and oxidation were used. aluminum (Al 2 O 3), also the same effect is obtained by using a metal oxide such as hafnium (HfO), yttrium oxide (Y 2 O 3).
이들 캐패시터 절연막은 막두께가 작을수록 용량이 크게 되지만, 20Å보다 얇은 상기 재료의 절연막을 핀홀없이 형성하는 것은 곤란하다. 또, 막두께가 350Å 이상이면 그 후에 실행되는 결정의 성장이 현저하게 되고, 절연막으로서의 특성이 현저하게 저하해 버린다. 이와 같은 이유에 의해서, 캐패시터 절연막의 막두께는 20Å∼350Å의 범위에서 선택된다.These capacitor insulating films have a larger capacity as the film thickness is smaller, but it is difficult to form an insulating film of the material thinner than 20 kPa without a pinhole. In addition, when the film thickness is 350 GPa or more, the growth of crystals to be performed thereafter becomes remarkable, and the characteristics as the insulating film significantly decrease. For this reason, the film thickness of the capacitor insulating film is selected in the range of 20 kV to 350 kV.
상부전극의 금속으로서는 다결정 실리콘 이외에 WSi2, MoSi2, TaSi2, TiSi2등 각종 실리사이드를 사용할 수가 있다. 또, W, Mo, Ta, TiN 또는 Cr 등 실리콘을 포함하지 않는 도전성 물질의 막을 사용한 경우도 상기의 식(1)과 유사한 반응, 즉 Ta2O5가 금속에 의해서 환원되어 Ta로 되는 반응이 일어나서 캐패시터의 절연내압의 저하가 발생한다. 본 발명에 의해 반응 방지막을 캐패시터 절연막과 상부전극 사이에 개재시키는 것에 의해서 상기 반응을 방지할 수 있으므로, 다결정 실리콘이나 실리사이드 뿐만 아니라 실리콘을 포함하지 않은 상기 각종 도전성 물질의 막도 상부전극으로서 사용할 수가 있다.As the metal of the upper electrode, various silicides such as WSi 2 , MoSi 2 , TaSi 2 , and TiSi 2 can be used in addition to polycrystalline silicon. In the case of using a film of a conductive material that does not contain silicon such as W, Mo, Ta, TiN, or Cr, a reaction similar to the above formula (1), ie, a reaction in which Ta 2 O 5 is reduced by metal and becomes Ta, This causes a drop in the dielectric breakdown voltage of the capacitor. According to the present invention, the reaction can be prevented by interposing the reaction prevention film between the capacitor insulating film and the upper electrode, so that not only polycrystalline silicon or silicide but also films of the various conductive materials not containing silicon can be used as the upper electrode. .
하부전극으로서는 상기 실시예에서 실리콘 기판을 사용한 예를 도시하였지만, 그 이외에도 상기 다결정 실리콘이나 실리사이드 또는 실리콘을 포함하지 않는 각종 도전성 물질의 막을 상부전극의 경우와 마찬가지로 하부전극으로서 사용할 수 있는 것은 물론이다.As the lower electrode, an example in which the silicon substrate is used in the above embodiment is shown, but besides, the film of various conductive materials not containing polycrystalline silicon, silicide or silicon can be used as the lower electrode as well as the upper electrode.
캐패시터 절연막을 형성할 때, 이들 하부전극상에는 산화막이 형성되고, 이것이 반응 방지막으로서 작용하므로, 통상의 경우는 캐패시터 절연막을 형성하기 전에 반응 방지막을 형성할 필요는 없다.When forming a capacitor insulating film, an oxide film is formed on these lower electrodes, and this acts as a reaction prevention film, and therefore it is not usually necessary to form a reaction prevention film before forming the capacitor insulating film.
그러나, 하부전극을 형성한 후 캐패시터 절연막을 형성하기 전에 SiO2막, Si3N4막 또는 인 실리케이트 글라스막 등을 제2의 반응 방지막으로서 형성하여도 아무런 지장이 없는 것은 물론이고, 캐패시터의 신뢰성은 더욱 향상된다.However, even if the SiO 2 film, the Si 3 N 4 film, or the silicate glass film is formed as the second reaction prevention film after forming the lower electrode and before the capacitor insulating film is formed, the reliability of the capacitor is of course no problem. Is further improved.
이상 설명한 바와 같이, 본 발명은 고유전율 절연막과 상부전극과의 사이에 배리어층으로서 반응 방지막을 마련한 것에 의해, 통상의 LSI의 제조공정에서 필요로 되는 약 1000℃까지의 열처리에 견딜 수 있는 고유전율 절연막을 사용한 캐패시터의 내열성을 확보할 수 있으므로, MOS 다이나믹 메모리 등의 작은 면적의 캐패시터를 필요로 하는 장치에 적용할 수 있다는 효과가 있다.As described above, the present invention provides a high dielectric constant capable of withstanding heat treatment up to about 1000 ° C. required in a conventional LSI manufacturing process by providing a reaction prevention film as a barrier layer between the high dielectric constant insulating film and the upper electrode. Since the heat resistance of the capacitor using the insulating film can be ensured, there is an effect that it can be applied to a device requiring a small area capacitor such as a MOS dynamic memory.
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| JP61181916A JPS6338248A (en) | 1986-08-04 | 1986-08-04 | Semiconductor device and manufacture thereof |
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| KR100944831B1 (en) * | 2003-10-30 | 2010-03-03 | 도쿄엘렉트론가부시키가이샤 | Method for manufacturing semiconductor device and film forming apparatus |
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| KR100358066B1 (en) | 1999-06-25 | 2002-10-25 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
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| US4038167A (en) * | 1976-02-09 | 1977-07-26 | Corning Glass Works | Method of forming a thin film capacitor |
| DE2967538D1 (en) * | 1978-06-14 | 1985-12-05 | Fujitsu Ltd | Process for producing a semiconductor device having an insulating layer of silicon dioxide covered by a film of silicon oxynitride |
| JPS5861763A (en) * | 1981-10-09 | 1983-04-12 | 武笠 均 | Feel sensor fire fighting apparatus |
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| JPS60153158A (en) * | 1984-01-23 | 1985-08-12 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
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1986
- 1986-08-04 JP JP61181916A patent/JPS6338248A/en active Pending
-
1987
- 1987-07-13 KR KR1019870007495A patent/KR940008370B1/en not_active IP Right Cessation
- 1987-08-04 US US07/081,231 patent/US4891684A/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100944831B1 (en) * | 2003-10-30 | 2010-03-03 | 도쿄엘렉트론가부시키가이샤 | Method for manufacturing semiconductor device and film forming apparatus |
| KR20190006030A (en) * | 2011-09-01 | 2019-01-16 | 인터몰레큘러 인코퍼레이티드 | Atomic layer deposition of metal oxide materials for memory applications |
| KR20190007073A (en) * | 2011-09-01 | 2019-01-21 | 인터몰레큘러 인코퍼레이티드 | Atomic layer deposition of metal oxide materials for memory applications |
Also Published As
| Publication number | Publication date |
|---|---|
| US4891684A (en) | 1990-01-02 |
| KR880003417A (en) | 1988-05-17 |
| JPS6338248A (en) | 1988-02-18 |
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